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The Art of Timing Closure [[electronic resource] ] : Advanced ASIC Design Implementation / / by Khosrow Golshan
| The Art of Timing Closure [[electronic resource] ] : Advanced ASIC Design Implementation / / by Khosrow Golshan |
| Autore | Golshan Khosrow |
| Edizione | [1st ed. 2020.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 |
| Descrizione fisica | 1 online resource (XIX, 204 p. 46 illus.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Electronic circuits
Microprocessors Electronics Microelectronics Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation |
| ISBN | 3-030-49636-8 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Chapter 1. Introduction -- Chapter 2. Design Implementation Data Structures and Settings -- Chapter 3. Design Constraints Development -- Chapter 4. Multiple Modes and Multiple Corners Development -- Chapter 5. Concurrent Floor Planning and Placement -- Chapter 6. Placement and Timing Analysis -- Chapter 7. Clock Tree Synthesis and Timing Analysis -- Chapter 8. Detail Route and Timing, Power Analysis -- Chapter 9. Final Route and Timing Closure in all Modes and Corners -- Chapter 10. Functional and Physical Verification. |
| Record Nr. | UNISA-996465468303316 |
Golshan Khosrow
|
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
The Art of Timing Closure : Advanced ASIC Design Implementation / / by Khosrow Golshan
| The Art of Timing Closure : Advanced ASIC Design Implementation / / by Khosrow Golshan |
| Autore | Golshan Khosrow |
| Edizione | [1st ed. 2020.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 |
| Descrizione fisica | 1 online resource (XIX, 204 p. 46 illus.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Electronic circuits
Microprocessors Electronics Microelectronics Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation |
| ISBN | 3-030-49636-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Chapter 1. Introduction -- Chapter 2. Design Implementation Data Structures and Settings -- Chapter 3. Design Constraints Development -- Chapter 4. Multiple Modes and Multiple Corners Development -- Chapter 5. Concurrent Floor Planning and Placement -- Chapter 6. Placement and Timing Analysis -- Chapter 7. Clock Tree Synthesis and Timing Analysis -- Chapter 8. Detail Route and Timing, Power Analysis -- Chapter 9. Final Route and Timing Closure in all Modes and Corners -- Chapter 10. Functional and Physical Verification. |
| Record Nr. | UNINA-9910416082903321 |
|
Golshan Khosrow
|
||
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ASIC Design Implementation Process : A Complete Framework
| ASIC Design Implementation Process : A Complete Framework |
| Autore | Golshan Khosrow |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Cham : , : Springer, , 2024 |
| Descrizione fisica | 1 online resource (143 pages) |
| ISBN |
9783031586538
9783031586521 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Intro -- Foreword -- Trademarks -- Preface -- Acknowledgments -- Disclaimer -- Contents -- About the Author -- Chapter 1: Design Requirements -- 1.1 Specifications -- 1.2 Architecture -- 1.3 Initial Design -- 1.4 Summary -- References -- Chapter 2: Design Validation -- 2.1 FPGA Design -- 2.2 FPGA Programming -- 2.3 Reference Board Design -- 2.4 Hardware and Software Validation -- 2.5 Summary -- References -- Chapter 3: Design Synthesis -- 3.1 Timing Constraints -- 3.2 Optimization Constraints -- 3.3 Design Rule Constraints -- 3.4 Summary -- References -- Chapter 4: Physical Design -- 4.1 Floorplanning -- 4.2 Placement -- 4.3 Clock Tree Synthesis -- 4.4 Routing -- 4.5 Summary -- References -- Chapter 5: Design Verification -- 5.1 Functional Verification -- 5.2 Timing Verification -- 5.3 Physical Verification -- 5.4 Summary -- References -- Chapter 6: ASIC Testing -- 6.1 Functional Test -- 6.2 Scan Test -- 6.3 Boundary Scan Test -- 6.4 Fault Detection -- 6.5 Parametric Test -- 6.6 Current and Very Low-Level Voltage Test -- 6.7 Built-In-Self-Test -- 6.8 Parallel Module Test -- 6.9 System Test -- 6.10 Summary -- References -- Chapter 7: ASIC Qualification -- 7.1 Electro-Static Discharge Test -- 7.2 Latch-up Test -- 7.3 Wafer Acceptance Test -- 7.4 Summary -- References -- Index. |
| Record Nr. | UNINA-9910865259303321 |
|
Golshan Khosrow
|
||
| Cham : , : Springer, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||