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Field Programmable Logic and Applications [[electronic resource] ] : 7th International Workshop, FPL '97, London, UK, September, 1-3, 1997, Proceedings. / / edited by Wayne Luk, Peter Y.K. Cheung, Manfred Glesner
| Field Programmable Logic and Applications [[electronic resource] ] : 7th International Workshop, FPL '97, London, UK, September, 1-3, 1997, Proceedings. / / edited by Wayne Luk, Peter Y.K. Cheung, Manfred Glesner |
| Edizione | [1st ed. 1997.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1997 |
| Descrizione fisica | 1 online resource (XII, 512 p.) |
| Disciplina | 621.39/5 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Computer engineering
Architecture, Computer Programming languages (Electronic computers) Computer hardware Computational complexity Mathematical logic Computer Engineering Computer System Implementation Programming Languages, Compilers, Interpreters Computer Hardware Complexity Mathematical Logic and Formal Languages |
| ISBN | 3-540-69557-5 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Multicontext dynamic reconfiguration and real-time probing on a novel mixed signal programmable device with on-chip microprocessor -- CAD-oriented FPGA and dedicated CAD system for telecommunications -- Rothko: A three dimensional FPGA architecture, its fabrication, and design tools -- Extending dynamic circuit switching to meet the challenges of new FPGA architectures -- Performance evaluation of a full speed PCI initiator and target subsystem using FPGAs -- Implementation of pipelined multipliers on Xilinx FPGAs -- The XC620ODS development system -- Thermal monitoring on FPGAs using ring-oscillators -- A reconfigurable approach to low cost media processing -- Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research -- Stream synthesis for a wormhole run-time reconfigurable platform -- Pipeline morphing and virtual pipelines -- Parallel graph colouring using FPGAs -- Run-time compaction of FPGA designs -- Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement -- A case study of partially evaluated hardware circuits: Key-specific DES -- Run-time parameterised circuits for the Xilinx XC6200 -- Automatic identification of swappable logic units in XC6200 circuitry -- Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic -- Exploiting reconfigurability through domain-specific systems -- Technology mapping by binate covering -- VPR: a new packing, placement and routing tool for FPGA research -- Technology mapping of heterogeneous LUT-based FPGAs -- Technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAs -- Technology mapping of LUT based FPGAs for delay optimisation -- Automatic Mapping of Algorithms onto multiple FPGA-SRAM Modules -- FPLD HDL synthesis employing high-level evolutionary algorithm optimisation -- An hardware/software partitioning algorithm for custom computing machines -- The Java Environment for Reconfigurable Computing -- Data scheduling to increase performance of parallel accelerators -- An operating system for custom computing machines based on the Xputer paradigm -- Fast parallel implementation of DFT using configurable devices -- Enhancing fixed point DSP processor performance by adding CPLD's as coprocessing elements -- A case study of algorithm implementation in reconfigurable hardware and software -- A reconfigurable data-localised array for morphological algorithms -- Virtual radix array processors (V-RaAP) -- An FPGA implementation of a matched filter detector for spread spectrum communications systems -- An NTSC and PAL closed caption processor -- A 800Mpixel/sec reconfigurable image correlator on XC6216 -- A reconfigurable coprocessor for a PCI-based real time computer vision system -- Real-time stereopsis using FPGAs -- FPGAs Implementation of a digital IQ demodulator using VHDL -- Hardware compilation, configurable platforms and ASICs for self-validating sensors -- PostScript™ rendering with virtual hardware -- P4: A platform for FPGA implementation of protocol boosters -- Satisfiability on reconfigurable hardware -- Auto-configurable array for GCD computation -- Structural versus algorithmic approaches for efficient adders on xilinx 5200 FPGA -- FPGA implementation of real-time digital controllers using on-line arithmetic -- A prototyping environment for fuzzy controllers -- A reconfigurable sensor-data processing system for personal robots. |
| Record Nr. | UNISA-996465493603316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1997 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Field Programmable Logic and Applications [[electronic resource] ] : 7th International Workshop, FPL '97, London, UK, September, 1-3, 1997, Proceedings. / / edited by Wayne Luk, Peter Y.K. Cheung, Manfred Glesner
| Field Programmable Logic and Applications [[electronic resource] ] : 7th International Workshop, FPL '97, London, UK, September, 1-3, 1997, Proceedings. / / edited by Wayne Luk, Peter Y.K. Cheung, Manfred Glesner |
| Edizione | [1st ed. 1997.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1997 |
| Descrizione fisica | 1 online resource (XII, 512 p.) |
| Disciplina | 621.39/5 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Computer engineering
Architecture, Computer Programming languages (Electronic computers) Computer hardware Computational complexity Mathematical logic Computer Engineering Computer System Implementation Programming Languages, Compilers, Interpreters Computer Hardware Complexity Mathematical Logic and Formal Languages |
| ISBN | 3-540-69557-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Multicontext dynamic reconfiguration and real-time probing on a novel mixed signal programmable device with on-chip microprocessor -- CAD-oriented FPGA and dedicated CAD system for telecommunications -- Rothko: A three dimensional FPGA architecture, its fabrication, and design tools -- Extending dynamic circuit switching to meet the challenges of new FPGA architectures -- Performance evaluation of a full speed PCI initiator and target subsystem using FPGAs -- Implementation of pipelined multipliers on Xilinx FPGAs -- The XC620ODS development system -- Thermal monitoring on FPGAs using ring-oscillators -- A reconfigurable approach to low cost media processing -- Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research -- Stream synthesis for a wormhole run-time reconfigurable platform -- Pipeline morphing and virtual pipelines -- Parallel graph colouring using FPGAs -- Run-time compaction of FPGA designs -- Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement -- A case study of partially evaluated hardware circuits: Key-specific DES -- Run-time parameterised circuits for the Xilinx XC6200 -- Automatic identification of swappable logic units in XC6200 circuitry -- Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic -- Exploiting reconfigurability through domain-specific systems -- Technology mapping by binate covering -- VPR: a new packing, placement and routing tool for FPGA research -- Technology mapping of heterogeneous LUT-based FPGAs -- Technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAs -- Technology mapping of LUT based FPGAs for delay optimisation -- Automatic Mapping of Algorithms onto multiple FPGA-SRAM Modules -- FPLD HDL synthesis employing high-level evolutionary algorithm optimisation -- An hardware/software partitioning algorithm for custom computing machines -- The Java Environment for Reconfigurable Computing -- Data scheduling to increase performance of parallel accelerators -- An operating system for custom computing machines based on the Xputer paradigm -- Fast parallel implementation of DFT using configurable devices -- Enhancing fixed point DSP processor performance by adding CPLD's as coprocessing elements -- A case study of algorithm implementation in reconfigurable hardware and software -- A reconfigurable data-localised array for morphological algorithms -- Virtual radix array processors (V-RaAP) -- An FPGA implementation of a matched filter detector for spread spectrum communications systems -- An NTSC and PAL closed caption processor -- A 800Mpixel/sec reconfigurable image correlator on XC6216 -- A reconfigurable coprocessor for a PCI-based real time computer vision system -- Real-time stereopsis using FPGAs -- FPGAs Implementation of a digital IQ demodulator using VHDL -- Hardware compilation, configurable platforms and ASICs for self-validating sensors -- PostScript™ rendering with virtual hardware -- P4: A platform for FPGA implementation of protocol boosters -- Satisfiability on reconfigurable hardware -- Auto-configurable array for GCD computation -- Structural versus algorithmic approaches for efficient adders on xilinx 5200 FPGA -- FPGA implementation of real-time digital controllers using on-line arithmetic -- A prototyping environment for fuzzy controllers -- A reconfigurable sensor-data processing system for personal robots. |
| Record Nr. | UNINA-9910144916003321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1997 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream [[electronic resource] ] : Reconfigurable Computing Is Going Mainstream / / edited by Manfred Glesner, Peter Zipf, Michel Renovell
| Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream [[electronic resource] ] : Reconfigurable Computing Is Going Mainstream / / edited by Manfred Glesner, Peter Zipf, Michel Renovell |
| Edizione | [1st ed. 2002.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2002 |
| Descrizione fisica | 1 online resource (XLIV, 1192 p. 330 illus.) |
| Disciplina | 621.39/5 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Architecture, Computer
Software engineering Logic design Computer memory systems Microprocessors Computer communication systems Computer System Implementation Software Engineering/Programming and Operating Systems Logic Design Memory Structures Processor Architectures Computer Communication Networks |
| ISBN | 3-540-46117-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynote Address -- Trends -- Rapid Prototyping -- FPGA Synthesis -- Custom Computing Engines -- DSP Applications 1 -- Reconfigurable Fabrics -- Dynamic Reconfiguration 1 -- DSP Applications 2 -- Routing & Placement -- Dynamic Reconfiguration 2 -- Power Estimation -- Synthesis Issues -- Keynote Address -- Communication Applications 1 -- New Technologies -- Reconfigurable Architectures -- Communication Applications 2 -- Multimedia Applications -- FPGA-based Arithmetic 1 -- Reconfigurable Processors -- Testing & Fault-Toloerance -- FPGA-based Arithmetic 2 -- Reconfigurable Systems -- Image Processing -- Crypto Applications 1 -- Keynote Address -- Multitasking -- Special Architectures -- Crypto Applications 2 -- Compilation Techniques -- DSP Applications 3 -- Complex Applications -- Architecture Implementation -- Design Flow -- Miscellaneous -- Short Papers. |
| Record Nr. | UNISA-996466219203316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream : Reconfigurable Computing Is Going Mainstream / / edited by Manfred Glesner, Peter Zipf, Michel Renovell
| Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream : Reconfigurable Computing Is Going Mainstream / / edited by Manfred Glesner, Peter Zipf, Michel Renovell |
| Edizione | [1st ed. 2002.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2002 |
| Descrizione fisica | 1 online resource (XLIV, 1192 p. 330 illus.) |
| Disciplina | 621.39/5 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Architecture, Computer
Software engineering Logic design Computer memory systems Microprocessors Computer communication systems Computer System Implementation Software Engineering/Programming and Operating Systems Logic Design Memory Structures Processor Architectures Computer Communication Networks |
| ISBN | 3-540-46117-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynote Address -- Trends -- Rapid Prototyping -- FPGA Synthesis -- Custom Computing Engines -- DSP Applications 1 -- Reconfigurable Fabrics -- Dynamic Reconfiguration 1 -- DSP Applications 2 -- Routing & Placement -- Dynamic Reconfiguration 2 -- Power Estimation -- Synthesis Issues -- Keynote Address -- Communication Applications 1 -- New Technologies -- Reconfigurable Architectures -- Communication Applications 2 -- Multimedia Applications -- FPGA-based Arithmetic 1 -- Reconfigurable Processors -- Testing & Fault-Toloerance -- FPGA-based Arithmetic 2 -- Reconfigurable Systems -- Image Processing -- Crypto Applications 1 -- Keynote Address -- Multitasking -- Special Architectures -- Crypto Applications 2 -- Compilation Techniques -- DSP Applications 3 -- Complex Applications -- Architecture Implementation -- Design Flow -- Miscellaneous -- Short Papers. |
| Record Nr. | UNINA-9910143903203321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Field-Programmable Logic, Smart Applications, New Paradigms and Compilers [[electronic resource] ] : 6th International Workshop on Field-Programmable Logic and Applications, FPL '96, Darmstadt, Germany, September 23 - 25, Proceedings / / edited by Reiner W. Hartenstein, Manfred Glesner
| Field-Programmable Logic, Smart Applications, New Paradigms and Compilers [[electronic resource] ] : 6th International Workshop on Field-Programmable Logic and Applications, FPL '96, Darmstadt, Germany, September 23 - 25, Proceedings / / edited by Reiner W. Hartenstein, Manfred Glesner |
| Edizione | [1st ed. 1996.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1996 |
| Descrizione fisica | 1 online resource (X, 436 p.) |
| Disciplina | 621.39/5 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Architecture, Computer
Logic design Microprocessors Computational complexity Computer-aided engineering Electronics Microelectronics Computer System Implementation Logic Design Register-Transfer-Level Implementation Complexity Computer-Aided Engineering (CAD, CAE) and Design Electronics and Microelectronics, Instrumentation |
| ISBN | 3-540-70670-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Portable pipeline synthesis for FCCMs -- Performance-directed technology mapping for LUT-based FPGAs — What role do decomposition and covering play? -- A framework for developing parametrised FPGA libraries -- FACT: Co-evaluation environment for FPGA architecture and CAD system -- An universal CLA adder generator for SRAM-based FPGAs -- An emulation system of the WASMII: A data driven computer on a virtual hardware -- Costum computing machines vs. Hardware/Software Co-Design: From a globalized point of view -- The design of a coprocessor board using Xilinx's XC6200 FPGA — An experience report -- RACE: Reconfigurable and adaptive computing environment -- Computing 2-D DFTs using FPGAs -- CAPpartx: Computer aided prototyping partitioning for Xilinx FPGAs, a hierarchical partitioning tool for rapid prototyping -- Architectural synthesis and efficient circuit implementation for field programmable gate arrays -- RaPiD — Reconfigurable pipelined datapath -- Solving satisfiability problems on FPGAs -- FPGA implementation of the block-matching algorithm for motion estimation in image coding -- Parallel CRC computation in FPGAs -- Coherent demodulation with FPGAs -- The Trianus system and its application to custom computing -- Logic synthesis for FPGAs using a mixed exclusive-/inclusive-OR form -- Flexible codesign target architecture for early prototyping of CMIST systems -- Attempt-1: A reconfigurable multiprocessor testbed -- A slow motion engine for the analysis of FPGA-based prototypes -- Implementing reconfigurable datapaths in FPGAs for adaptive filter design -- A fast constant coefficient multiplier for the XC6200 -- Key issues for user acceptance of FPGA design tools -- Reconfigurable DSP demonstrators for the development of spacecraft payload processors -- Reconfigurable logic based fibre channel network card with sub 2 ?s raw latency -- An asynchronous transfer mode (ATM) stream demultiplexer and switch -- Optically reconfigurable FPGAs: Is this a future trend? -- CCSimP — An instruction-level costum-configurable processor for FPLDs -- Architectural synthesis techniques for dynamically reconfigurable logic -- Fast reconfigurable crossbar switching in FPGAs -- Growable FPGA macro generator -- Architectural strategies for implementing an image processing algorithm on XC6000 FPGA -- A virtual hardware operating system for the Xilinx XC6200 -- An experimental programmable environment for prototyping digital circuits -- Migration from schematic-based designs to a VHDL synthesis environment -- ASIC design and FPGA design: A unified design methodology applied to different technologies -- FIR filtering with FPGAs using quadrature sigma-delta modulation encoding -- A new FPGA technology mapping approach by cluster merging -- An EPLD based transient recorder for simulation of video signal processing devices in a VHDL environment close to system level conditions -- Convolutional error decoding with FPGAs -- Metastability characteristics testing for programmable logic design -- Implementing ?? modulator prototype designs on an FPGA -- Design of a VME parameterized library for FPGAs -- Development of a telephone answering machine in a lab — FPGAs in Education -- FPGA design migration: Some remarks -- Concurrent design of hardware/software dedicated systems -- The implementation of a field programmable logic based co-processor for the acceleration of discrete event simulators -- Computing weight distributions of binary linear block codes on a CCM. |
| Record Nr. | UNISA-996465857503316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1996 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Ninth International Workshop on Rapid System Prototyping: Jnue 3-5, 1998, Leuven, Belgium
| Ninth International Workshop on Rapid System Prototyping: Jnue 3-5, 1998, Leuven, Belgium |
| Autore | Becker Jürgen |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society Press, 1998 |
| Soggetto topico |
Engineering & Applied Sciences
Computer Science |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996217756003316 |
Becker Jürgen
|
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| [Place of publication not identified], : IEEE Computer Society Press, 1998 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Ninth International Workshop on Rapid System Prototyping: Jnue 3-5, 1998, Leuven, Belgium
| Ninth International Workshop on Rapid System Prototyping: Jnue 3-5, 1998, Leuven, Belgium |
| Autore | Becker Jürgen |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society Press, 1998 |
| Soggetto topico |
Engineering & Applied Sciences
Computer Science |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910872645903321 |
|
Becker Jürgen
|
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| [Place of publication not identified], : IEEE Computer Society Press, 1998 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||