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Embedded hardware [[electronic resource] /] / Jack Ganssle ... [et al.]
| Embedded hardware [[electronic resource] /] / Jack Ganssle ... [et al.] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier/Newnes, c2008 |
| Descrizione fisica | 1 online resource (537 p.) |
| Disciplina | 004.16 |
| Altri autori (Persone) | GanssleJack G |
| Collana | Newnes know it all series |
| Soggetto topico | Embedded computer systems |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-281-77201-1
9786611772017 0-08-056074-1 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Embedded Hardware; Copyright Page; Contents; About the Authors; Chapter 1 Embedded Hardware Basics; 1.1 Lesson One on Hardware: Reading Schematics; 1.2 The Embedded Board and the von Neumann Model; 1.3 Powering the Hardware; 1.3.1 A Quick Comment on Analog Vs. Digital Signals; 1.4 Basic Electronics; 1.4.1 DC Circuits; 1.4.2 AC Circuits; 1.4.3 Active Devices; 1.5 Putting It Together: A Power Supply; 1.5.1 The Scope; 1.5.2 Controls; 1.5.3 Probes; Endnotes; Chapter 2 Logic Circuits; 2.1 Coding; 2.1.1 BCD; 2.2 Combinatorial Logic; 2.2.1 NOT Gate; 2.2.2 AND and NAND Gates
2.2.3 OR and NOR Gates2.2.4 XOR; 2.2.5 Circuits; 2.2.6 Tristate Devices; 2.3 Sequential Logic; 2.3.1 Logic Wrap-Up; 2.4 Putting It All Together: The Integrated Circuit; Endnotes; Chapter 3 Embedded Processors; 3.1 Introduction; 3.2 ISA Architecture Models; 3.2.1 Operations; 3.2.2 Operands; 3.2.3 Storage; 3.2.4 Addressing Modes; 3.2.5 Interrupts and Exception Handling; 3.2.6 Application-Specific ISA Models; 3.2.7 General-Purpose ISA Models; 3.2.8 Instruction-Level Parallelism ISA Models; 3.3 Internal Processor Design; 3.3.1 Central Processing Unit (CPU); 3.3.2 On-Chip Memory 3.3.3 Processor Input/Output (I/O)3.3.4 Processor Buses; 3.4 Processor Performance; 3.4.1 Benchmarks; Endnotes; Chapter 4 Embedded Board Buses and I/O; 4.1 Board I/O; 4.2 Managing Data: Serial vs. Parallel I/O; 4.2.1 Serial I/O Example 1: Networking and Communications: RS-232; 4.2.2 Example: Motorola/Freescale MPC823 FADS Board RS-232 System Model; 4.2.3 Serial I/O Example 2: Networking and Communications: IEEE 802.11 Wireless LAN; 4.2.4 Parallel I/O; 4.2.5 Parallel I/O Example 3: ""Parallel"" Output and Graphics I/O 4.2.6 Parallel and Serial I/O Example 4: Networking and Communications-Ethernet4.2.7 Example 1: Motorola/Freescale MPC823 FADS Board Ethernet System Model; 4.2.8 Example 2: Net Silicon ARM7 (6127001) Development Board Ethernet System Model; 4.2.9 Example 3: Adastra Neptune x86 Board Ethernet System Model; 4.3 Interfacing the I/O Components; 4.3.1 Interfacing the I/O Device with the Embedded Board; 4.3.2 Interfacing an I/O Controller and the Master CPU; 4.4 I/O and Performance; 4.5 Board Buses; 4.6 Bus Arbitration and Timing; 4.6.1 Nonexpandable Bus: I[sup(2)]C Bus Example 4.6.2 PCI (Peripheral Component Interconnect) Bus Example: Expandable4.7 Integrating the Bus with Other Board Components; 4.8 Bus Performance; Chapter 5 Memory Systems; 5.1 Introduction; 5.2 Memory Spaces; 5.2.1 L1 Instruction Memory; 5.2.2 Using L1 Instruction Memory for Data Placement; 5.2.3 L1 Data Memory; 5.3 Cache Overview; 5.3.1 What Is Cache?; 5.3.2 Direct-Mapped Cache; 5.3.3 Fully Associative Cache; 5.3.4 N-Way Set-Associative Cache; 5.3.5 More Cache Details; 5.3.6 Write-Through and Write-Back Data Cache; 5.4 External Memory; 5.4.1 Synchronous Memory; 5.4.2 Asynchronous Memory 5.4.3 Nonvolatile Memories |
| Record Nr. | UNINA-9910456081903321 |
| Amsterdam ; ; Boston, : Elsevier/Newnes, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Embedded hardware [[electronic resource] /] / Jack Ganssle ... [et al.]
| Embedded hardware [[electronic resource] /] / Jack Ganssle ... [et al.] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier/Newnes, c2008 |
| Descrizione fisica | 1 online resource (537 p.) |
| Disciplina | 004.16 |
| Altri autori (Persone) | GanssleJack G |
| Collana | Newnes know it all series |
| Soggetto topico | Embedded computer systems |
| ISBN |
1-281-77201-1
9786611772017 0-08-056074-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Embedded Hardware; Copyright Page; Contents; About the Authors; Chapter 1 Embedded Hardware Basics; 1.1 Lesson One on Hardware: Reading Schematics; 1.2 The Embedded Board and the von Neumann Model; 1.3 Powering the Hardware; 1.3.1 A Quick Comment on Analog Vs. Digital Signals; 1.4 Basic Electronics; 1.4.1 DC Circuits; 1.4.2 AC Circuits; 1.4.3 Active Devices; 1.5 Putting It Together: A Power Supply; 1.5.1 The Scope; 1.5.2 Controls; 1.5.3 Probes; Endnotes; Chapter 2 Logic Circuits; 2.1 Coding; 2.1.1 BCD; 2.2 Combinatorial Logic; 2.2.1 NOT Gate; 2.2.2 AND and NAND Gates
2.2.3 OR and NOR Gates2.2.4 XOR; 2.2.5 Circuits; 2.2.6 Tristate Devices; 2.3 Sequential Logic; 2.3.1 Logic Wrap-Up; 2.4 Putting It All Together: The Integrated Circuit; Endnotes; Chapter 3 Embedded Processors; 3.1 Introduction; 3.2 ISA Architecture Models; 3.2.1 Operations; 3.2.2 Operands; 3.2.3 Storage; 3.2.4 Addressing Modes; 3.2.5 Interrupts and Exception Handling; 3.2.6 Application-Specific ISA Models; 3.2.7 General-Purpose ISA Models; 3.2.8 Instruction-Level Parallelism ISA Models; 3.3 Internal Processor Design; 3.3.1 Central Processing Unit (CPU); 3.3.2 On-Chip Memory 3.3.3 Processor Input/Output (I/O)3.3.4 Processor Buses; 3.4 Processor Performance; 3.4.1 Benchmarks; Endnotes; Chapter 4 Embedded Board Buses and I/O; 4.1 Board I/O; 4.2 Managing Data: Serial vs. Parallel I/O; 4.2.1 Serial I/O Example 1: Networking and Communications: RS-232; 4.2.2 Example: Motorola/Freescale MPC823 FADS Board RS-232 System Model; 4.2.3 Serial I/O Example 2: Networking and Communications: IEEE 802.11 Wireless LAN; 4.2.4 Parallel I/O; 4.2.5 Parallel I/O Example 3: ""Parallel"" Output and Graphics I/O 4.2.6 Parallel and Serial I/O Example 4: Networking and Communications-Ethernet4.2.7 Example 1: Motorola/Freescale MPC823 FADS Board Ethernet System Model; 4.2.8 Example 2: Net Silicon ARM7 (6127001) Development Board Ethernet System Model; 4.2.9 Example 3: Adastra Neptune x86 Board Ethernet System Model; 4.3 Interfacing the I/O Components; 4.3.1 Interfacing the I/O Device with the Embedded Board; 4.3.2 Interfacing an I/O Controller and the Master CPU; 4.4 I/O and Performance; 4.5 Board Buses; 4.6 Bus Arbitration and Timing; 4.6.1 Nonexpandable Bus: I[sup(2)]C Bus Example 4.6.2 PCI (Peripheral Component Interconnect) Bus Example: Expandable4.7 Integrating the Bus with Other Board Components; 4.8 Bus Performance; Chapter 5 Memory Systems; 5.1 Introduction; 5.2 Memory Spaces; 5.2.1 L1 Instruction Memory; 5.2.2 Using L1 Instruction Memory for Data Placement; 5.2.3 L1 Data Memory; 5.3 Cache Overview; 5.3.1 What Is Cache?; 5.3.2 Direct-Mapped Cache; 5.3.3 Fully Associative Cache; 5.3.4 N-Way Set-Associative Cache; 5.3.5 More Cache Details; 5.3.6 Write-Through and Write-Back Data Cache; 5.4 External Memory; 5.4.1 Synchronous Memory; 5.4.2 Asynchronous Memory 5.4.3 Nonvolatile Memories |
| Record Nr. | UNINA-9910780761003321 |
| Amsterdam ; ; Boston, : Elsevier/Newnes, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Embedded hardware / / Jack Ganssle ... [et al.]
| Embedded hardware / / Jack Ganssle ... [et al.] |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier/Newnes, c2008 |
| Descrizione fisica | 1 online resource (537 p.) |
| Disciplina | 004.16 |
| Altri autori (Persone) | GanssleJack G |
| Collana | Newnes know it all series |
| Soggetto topico | Embedded computer systems |
| ISBN |
1-281-77201-1
9786611772017 0-08-056074-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Embedded Hardware; Copyright Page; Contents; About the Authors; Chapter 1 Embedded Hardware Basics; 1.1 Lesson One on Hardware: Reading Schematics; 1.2 The Embedded Board and the von Neumann Model; 1.3 Powering the Hardware; 1.3.1 A Quick Comment on Analog Vs. Digital Signals; 1.4 Basic Electronics; 1.4.1 DC Circuits; 1.4.2 AC Circuits; 1.4.3 Active Devices; 1.5 Putting It Together: A Power Supply; 1.5.1 The Scope; 1.5.2 Controls; 1.5.3 Probes; Endnotes; Chapter 2 Logic Circuits; 2.1 Coding; 2.1.1 BCD; 2.2 Combinatorial Logic; 2.2.1 NOT Gate; 2.2.2 AND and NAND Gates
2.2.3 OR and NOR Gates2.2.4 XOR; 2.2.5 Circuits; 2.2.6 Tristate Devices; 2.3 Sequential Logic; 2.3.1 Logic Wrap-Up; 2.4 Putting It All Together: The Integrated Circuit; Endnotes; Chapter 3 Embedded Processors; 3.1 Introduction; 3.2 ISA Architecture Models; 3.2.1 Operations; 3.2.2 Operands; 3.2.3 Storage; 3.2.4 Addressing Modes; 3.2.5 Interrupts and Exception Handling; 3.2.6 Application-Specific ISA Models; 3.2.7 General-Purpose ISA Models; 3.2.8 Instruction-Level Parallelism ISA Models; 3.3 Internal Processor Design; 3.3.1 Central Processing Unit (CPU); 3.3.2 On-Chip Memory 3.3.3 Processor Input/Output (I/O)3.3.4 Processor Buses; 3.4 Processor Performance; 3.4.1 Benchmarks; Endnotes; Chapter 4 Embedded Board Buses and I/O; 4.1 Board I/O; 4.2 Managing Data: Serial vs. Parallel I/O; 4.2.1 Serial I/O Example 1: Networking and Communications: RS-232; 4.2.2 Example: Motorola/Freescale MPC823 FADS Board RS-232 System Model; 4.2.3 Serial I/O Example 2: Networking and Communications: IEEE 802.11 Wireless LAN; 4.2.4 Parallel I/O; 4.2.5 Parallel I/O Example 3: ""Parallel"" Output and Graphics I/O 4.2.6 Parallel and Serial I/O Example 4: Networking and Communications-Ethernet4.2.7 Example 1: Motorola/Freescale MPC823 FADS Board Ethernet System Model; 4.2.8 Example 2: Net Silicon ARM7 (6127001) Development Board Ethernet System Model; 4.2.9 Example 3: Adastra Neptune x86 Board Ethernet System Model; 4.3 Interfacing the I/O Components; 4.3.1 Interfacing the I/O Device with the Embedded Board; 4.3.2 Interfacing an I/O Controller and the Master CPU; 4.4 I/O and Performance; 4.5 Board Buses; 4.6 Bus Arbitration and Timing; 4.6.1 Nonexpandable Bus: I[sup(2)]C Bus Example 4.6.2 PCI (Peripheral Component Interconnect) Bus Example: Expandable4.7 Integrating the Bus with Other Board Components; 4.8 Bus Performance; Chapter 5 Memory Systems; 5.1 Introduction; 5.2 Memory Spaces; 5.2.1 L1 Instruction Memory; 5.2.2 Using L1 Instruction Memory for Data Placement; 5.2.3 L1 Data Memory; 5.3 Cache Overview; 5.3.1 What Is Cache?; 5.3.2 Direct-Mapped Cache; 5.3.3 Fully Associative Cache; 5.3.4 N-Way Set-Associative Cache; 5.3.5 More Cache Details; 5.3.6 Write-Through and Write-Back Data Cache; 5.4 External Memory; 5.4.1 Synchronous Memory; 5.4.2 Asynchronous Memory 5.4.3 Nonvolatile Memories |
| Record Nr. | UNINA-9910816699103321 |
| Amsterdam ; ; Boston, : Elsevier/Newnes, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Embedded systems [[electronic resource] /] / Jack Ganssle [editor] ; with Stuart Ball ... [et al.]
| Embedded systems [[electronic resource] /] / Jack Ganssle [editor] ; with Stuart Ball ... [et al.] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier/Newnes, c2008 |
| Descrizione fisica | 1 online resource (583 p.) |
| Disciplina | 004.16 |
| Altri autori (Persone) |
GanssleJack G
BallStuart R. <1956-> |
| Collana | World class designs |
| Soggetto topico | Embedded computer systems - Design and construction |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-281-77202-X
9786611772024 0-08-055686-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Embedded Systems; Copyright Page; Table of Contents; About the Editor; About the Authors; Preface; Chapter 1: Motors; 1.1 Stepper Motors; 1.2 DC Motors; 1.3 Brushless DC Motors; 1.4 Tradeoffs Between Motors; 1.5 Motor Torque; Chapter 2: Testing; 2.1 Why Test?; 2.2 When to Test?; 2.3 Which Tests?; 2.4 When to Stop?; 2.5 Choosing Test Cases; 2.6 Testing Embedded Software; 2.7 Performance Testing; 2.8 Maintenance and Testing; Additional Reading; Summary; References; Chapter 3: System-Level Design; 3.1 Dissecting the Requirements Document; 3.2 Communications; 3.3 System Priorities
3.4 Error Handling 3.5 System-Level Design; Chapter 4: Some Example Sensor, Actuator, and Control Applications and Circuits (Hard Tasks); 4.1 Introduction; 4.2 E2BUS PC-Host Interface; 4.3 Host-to-Module Communications Protocol; 4.4 Speed-Controlled DC Motor with Tach Feedback and Thermal Cutoff; 4.5 Two-Axis Attitude Sensor Using MEMS Accelerometer; 4.6 RS-422-Compatible Indicator Panel; Chapter 5: Installing and Using a Version Control System; 5.1 Introduction; 5.2 The Power and Elegance of Simplicity; 5.3 Version Control 5.4 Typical Symptoms of Not (Fully) Utilizing a Version Control System 5.5 Simple Version Control Systems; 5.6 Advanced Version Control Systems; 5.7 What Files to Put Under Version Control; 5.8 Sharing of Files and the Version Control Client; 5.9 Integrated Development Environment Issues; 5.10 Graphical User Interface (GUI) Issues; 5.11 Common Source Code Control Specification; 5.12 World Wide Web Browser Interface or Java Version Control Client; 5.13 Bug Tracking; 5.14 Non-Configuration Management Tools; 5.15 Closing Comments; Suggested Reading, References, and Resources Chapter 6: Embedded State Machine Implementation 6.1 State Machines; 6.2 An Example; 6.3 Implementation; 6.4 Testing; 6.5 Crank It; References; Chapter 7: Firmware Musings; 7.1 Hacking Peripheral Drivers; 7.2 Selecting Stack Size; 7.3 The Curse of Malloc( ); 7.4 Banking; 7.5 Logical to Physical; 7.6 Hardware Issues; 7.7 The Software; 7.8 Predicting ROM Requirements; 7.9 RAM Diagnostics; 7.10 Inverting Bits; 7.11 Noise Issues; 7.12 A Few Notes on Software Prototyping; Chapter 8: Hardware Musings; 8.1 Debuggable Designs; 8.2 Test Points Galore; 8.3 Resistors; 8.4 Unused Inputs; 8.5 Clocks 8.6 Reset 8.7 Small CPUs; 8.8 Watchdog Timers; 8.9 Making PCBs; 8.10 Changing PCBs; 8.11 Planning; Chapter 9: Closed Loop Controls, Rabbits and Hounds; 9.1 Basic PID Controls; 9.2 Predictive Controls; 9.3 Combined Reactive and Predictive Controls; 9.4 Various PID Enhancements; 9.5 Robot Drive Controls; 9.6 Tuning Controls; 9.7 Rabbits Chasing Rabbits; 9.8 Conclusions; Chapter 10: Application Examples; 10.1 Introduction; 10.2 Automotive Driver Assistance; 10.3 Baseline JPEG Compression Overview; 10.4 MPEG-2 Encoding; 10.5 Code Optimization Study Using Open-Source Algorithms Chapter 11: Analog I/Os |
| Record Nr. | UNINA-9910453422103321 |
| Amsterdam ; ; Boston, : Elsevier/Newnes, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Embedded systems [[electronic resource] /] / Jack Ganssle [editor] ; with Stuart Ball ... [et al.]
| Embedded systems [[electronic resource] /] / Jack Ganssle [editor] ; with Stuart Ball ... [et al.] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier/Newnes, c2008 |
| Descrizione fisica | 1 online resource (583 p.) |
| Disciplina | 004.16 |
| Altri autori (Persone) |
GanssleJack G
BallStuart R. <1956-> |
| Collana | World class designs |
| Soggetto topico | Embedded computer systems - Design and construction |
| ISBN |
1-281-77202-X
9786611772024 0-08-055686-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Embedded Systems; Copyright Page; Table of Contents; About the Editor; About the Authors; Preface; Chapter 1: Motors; 1.1 Stepper Motors; 1.2 DC Motors; 1.3 Brushless DC Motors; 1.4 Tradeoffs Between Motors; 1.5 Motor Torque; Chapter 2: Testing; 2.1 Why Test?; 2.2 When to Test?; 2.3 Which Tests?; 2.4 When to Stop?; 2.5 Choosing Test Cases; 2.6 Testing Embedded Software; 2.7 Performance Testing; 2.8 Maintenance and Testing; Additional Reading; Summary; References; Chapter 3: System-Level Design; 3.1 Dissecting the Requirements Document; 3.2 Communications; 3.3 System Priorities
3.4 Error Handling 3.5 System-Level Design; Chapter 4: Some Example Sensor, Actuator, and Control Applications and Circuits (Hard Tasks); 4.1 Introduction; 4.2 E2BUS PC-Host Interface; 4.3 Host-to-Module Communications Protocol; 4.4 Speed-Controlled DC Motor with Tach Feedback and Thermal Cutoff; 4.5 Two-Axis Attitude Sensor Using MEMS Accelerometer; 4.6 RS-422-Compatible Indicator Panel; Chapter 5: Installing and Using a Version Control System; 5.1 Introduction; 5.2 The Power and Elegance of Simplicity; 5.3 Version Control 5.4 Typical Symptoms of Not (Fully) Utilizing a Version Control System 5.5 Simple Version Control Systems; 5.6 Advanced Version Control Systems; 5.7 What Files to Put Under Version Control; 5.8 Sharing of Files and the Version Control Client; 5.9 Integrated Development Environment Issues; 5.10 Graphical User Interface (GUI) Issues; 5.11 Common Source Code Control Specification; 5.12 World Wide Web Browser Interface or Java Version Control Client; 5.13 Bug Tracking; 5.14 Non-Configuration Management Tools; 5.15 Closing Comments; Suggested Reading, References, and Resources Chapter 6: Embedded State Machine Implementation 6.1 State Machines; 6.2 An Example; 6.3 Implementation; 6.4 Testing; 6.5 Crank It; References; Chapter 7: Firmware Musings; 7.1 Hacking Peripheral Drivers; 7.2 Selecting Stack Size; 7.3 The Curse of Malloc( ); 7.4 Banking; 7.5 Logical to Physical; 7.6 Hardware Issues; 7.7 The Software; 7.8 Predicting ROM Requirements; 7.9 RAM Diagnostics; 7.10 Inverting Bits; 7.11 Noise Issues; 7.12 A Few Notes on Software Prototyping; Chapter 8: Hardware Musings; 8.1 Debuggable Designs; 8.2 Test Points Galore; 8.3 Resistors; 8.4 Unused Inputs; 8.5 Clocks 8.6 Reset 8.7 Small CPUs; 8.8 Watchdog Timers; 8.9 Making PCBs; 8.10 Changing PCBs; 8.11 Planning; Chapter 9: Closed Loop Controls, Rabbits and Hounds; 9.1 Basic PID Controls; 9.2 Predictive Controls; 9.3 Combined Reactive and Predictive Controls; 9.4 Various PID Enhancements; 9.5 Robot Drive Controls; 9.6 Tuning Controls; 9.7 Rabbits Chasing Rabbits; 9.8 Conclusions; Chapter 10: Application Examples; 10.1 Introduction; 10.2 Automotive Driver Assistance; 10.3 Baseline JPEG Compression Overview; 10.4 MPEG-2 Encoding; 10.5 Code Optimization Study Using Open-Source Algorithms Chapter 11: Analog I/Os |
| Record Nr. | UNINA-9910782360703321 |
| Amsterdam ; ; Boston, : Elsevier/Newnes, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Embedded systems / / Jack Ganssle [editor] ; with Stuart Ball ... [et al.]
| Embedded systems / / Jack Ganssle [editor] ; with Stuart Ball ... [et al.] |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier/Newnes, c2008 |
| Descrizione fisica | 1 online resource (583 p.) |
| Disciplina | 004.16 |
| Altri autori (Persone) |
GanssleJack G
BallStuart R. <1956-> |
| Collana | World class designs |
| Soggetto topico | Embedded computer systems - Design and construction |
| ISBN |
1-281-77202-X
9786611772024 0-08-055686-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Embedded Systems; Copyright Page; Table of Contents; About the Editor; About the Authors; Preface; Chapter 1: Motors; 1.1 Stepper Motors; 1.2 DC Motors; 1.3 Brushless DC Motors; 1.4 Tradeoffs Between Motors; 1.5 Motor Torque; Chapter 2: Testing; 2.1 Why Test?; 2.2 When to Test?; 2.3 Which Tests?; 2.4 When to Stop?; 2.5 Choosing Test Cases; 2.6 Testing Embedded Software; 2.7 Performance Testing; 2.8 Maintenance and Testing; Additional Reading; Summary; References; Chapter 3: System-Level Design; 3.1 Dissecting the Requirements Document; 3.2 Communications; 3.3 System Priorities
3.4 Error Handling 3.5 System-Level Design; Chapter 4: Some Example Sensor, Actuator, and Control Applications and Circuits (Hard Tasks); 4.1 Introduction; 4.2 E2BUS PC-Host Interface; 4.3 Host-to-Module Communications Protocol; 4.4 Speed-Controlled DC Motor with Tach Feedback and Thermal Cutoff; 4.5 Two-Axis Attitude Sensor Using MEMS Accelerometer; 4.6 RS-422-Compatible Indicator Panel; Chapter 5: Installing and Using a Version Control System; 5.1 Introduction; 5.2 The Power and Elegance of Simplicity; 5.3 Version Control 5.4 Typical Symptoms of Not (Fully) Utilizing a Version Control System 5.5 Simple Version Control Systems; 5.6 Advanced Version Control Systems; 5.7 What Files to Put Under Version Control; 5.8 Sharing of Files and the Version Control Client; 5.9 Integrated Development Environment Issues; 5.10 Graphical User Interface (GUI) Issues; 5.11 Common Source Code Control Specification; 5.12 World Wide Web Browser Interface or Java Version Control Client; 5.13 Bug Tracking; 5.14 Non-Configuration Management Tools; 5.15 Closing Comments; Suggested Reading, References, and Resources Chapter 6: Embedded State Machine Implementation 6.1 State Machines; 6.2 An Example; 6.3 Implementation; 6.4 Testing; 6.5 Crank It; References; Chapter 7: Firmware Musings; 7.1 Hacking Peripheral Drivers; 7.2 Selecting Stack Size; 7.3 The Curse of Malloc( ); 7.4 Banking; 7.5 Logical to Physical; 7.6 Hardware Issues; 7.7 The Software; 7.8 Predicting ROM Requirements; 7.9 RAM Diagnostics; 7.10 Inverting Bits; 7.11 Noise Issues; 7.12 A Few Notes on Software Prototyping; Chapter 8: Hardware Musings; 8.1 Debuggable Designs; 8.2 Test Points Galore; 8.3 Resistors; 8.4 Unused Inputs; 8.5 Clocks 8.6 Reset 8.7 Small CPUs; 8.8 Watchdog Timers; 8.9 Making PCBs; 8.10 Changing PCBs; 8.11 Planning; Chapter 9: Closed Loop Controls, Rabbits and Hounds; 9.1 Basic PID Controls; 9.2 Predictive Controls; 9.3 Combined Reactive and Predictive Controls; 9.4 Various PID Enhancements; 9.5 Robot Drive Controls; 9.6 Tuning Controls; 9.7 Rabbits Chasing Rabbits; 9.8 Conclusions; Chapter 10: Application Examples; 10.1 Introduction; 10.2 Automotive Driver Assistance; 10.3 Baseline JPEG Compression Overview; 10.4 MPEG-2 Encoding; 10.5 Code Optimization Study Using Open-Source Algorithms Chapter 11: Analog I/Os |
| Record Nr. | UNINA-9910813158203321 |
| Amsterdam ; ; Boston, : Elsevier/Newnes, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||