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Hardware Security : A Look into the Future
| Hardware Security : A Look into the Future |
| Autore | Tehranipoor Mark |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing AG, , 2024 |
| Descrizione fisica | 1 online resource (0 pages) |
| Altri autori (Persone) |
Zamiri AzarKimia
AsadizanjaniNavid RahmanFahim Mardani KamaliHadi FarahmandiFarimah |
| ISBN |
9783031586873
9783031586866 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910865240903321 |
Tehranipoor Mark
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| Cham : , : Springer International Publishing AG, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Hardware Security Training, Hands-on! [[electronic resource] /] / by Mark Tehranipoor, N. Nalla Anandakumar, Farimah Farahmandi
| Hardware Security Training, Hands-on! [[electronic resource] /] / by Mark Tehranipoor, N. Nalla Anandakumar, Farimah Farahmandi |
| Autore | Tehranipoor Mark |
| Edizione | [1st ed. 2023.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023 |
| Descrizione fisica | 1 online resource (XXIV, 320 p. 250 illus., 218 illus. in color.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Electronic circuits
Embedded computer systems Electronic circuit design Electronic Circuits and Systems Embedded Systems Electronics Design and Verification |
| ISBN | 3-031-31034-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Chapter 1. Physical Unclonable Functions (PUFs) -- Chapter 2. True Random Number Generator (TRNG) -- Chapter 3. Recycled Chip Detection using RO-based Odometer -- Chapter 4. Recycled FPGA Detection -- Chapter 5. Hardware Trojan Insertion -- Chapter 6. Hardware Trojan Detection -- Chapter 7. Security Verification -- Chapter 8. Power Analysis Attacks on AES -- Chapter 9. EM Side-Channel Attack on AES -- Chapter 10. Logic Locking Insertion and Assessment -- Chapter 11. Clock Glitch Fault Attack on FSM in AES Controller -- Chapter 12. Voltage Glitch Attack on an FPGA AES Implementation -- Chapter 13. Laser Fault Injection Attack (FIA) -- Chapter 14. Optical Probing Attack on Logic Locking -- Chapter 15. Universal Fault Sensor -- Chapter 16. Scanning Electron Microscope Training. |
| Record Nr. | UNINA-9910742492103321 |
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Tehranipoor Mark
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Post-Silicon Validation and Debug [[electronic resource] /] / edited by Prabhat Mishra, Farimah Farahmandi
| Post-Silicon Validation and Debug [[electronic resource] /] / edited by Prabhat Mishra, Farimah Farahmandi |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (393 pages) |
| Disciplina | 005.14 |
| Soggetto topico |
Electronic circuits
Microprocessors Electronics Microelectronics Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation |
| ISBN | 3-319-98116-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Part 1. Introduction -- Post-Silicon SoC Validation Challenges -- Part 2. Debug Infrastructure -- SoC Instrumentations: Pre-silicon Preparation for Post-silicon Readiness -- Structure-based Signal Selection for Post-silicon Validation -- Simulation-based Signal Selection -- Hybrid Signal Selection -- Post-Silicon Signal Selection using Machine Learning -- Part 3. Generation of Tests and Assertions -- Observability-aware Post-Silicon Test Generation -- On-chip Constrained-Random Stimuli Generation -- Test Generation and Lightweight Checking for Multi-core Memory Consistency -- Selection of Post-Silicon Hardware Assertions -- Part 4. Post-Silicon Debug -- Debug Data Reduction Techniques -- High-level Debugging of Post-silicon Failures -- Post-silicon Fault Localization with Satisfiability Solvers -- Coverage Evaluation and Analysis of Post-silicon Tests with Virtual Prototypes -- Utilization of Debug Infrastructure for Post-Silicon Coverage Analysis -- Part 5. Case Studies -- Network-on-Chip Validation and Debug -- Post-silicon Validation of the IBM Power8 Processor -- Part 6. Conclusion and Future Directions -- SoC Security versus Post-Silicon Debug Conflict -- The Future of Post-Silicon Debug. |
| Record Nr. | UNINA-9910337649803321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Understanding Logic Locking [[electronic resource] /] / by Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark Tehranipoor
| Understanding Logic Locking [[electronic resource] /] / by Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark Tehranipoor |
| Autore | Zamiri Azar Kimia |
| Edizione | [1st ed. 2024.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024 |
| Descrizione fisica | 1 online resource (385 pages) |
| Disciplina | 005.8 |
| Altri autori (Persone) |
Mardani KamaliHadi
FarahmandiFarimah TehranipoorMark |
| Soggetto topico |
Electronic circuit design
Embedded computer systems Electronic circuits Electronics Design and Verification Embedded Systems Electronic Circuits and Systems |
| ISBN | 3-031-37989-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Basics of VLSI Design -- Basics of VLSI Testing and Debug -- IP Protection in VLSI Design: A Historical View -- Making a Case for Logic Locking -- Fundamentals of Logic Locking -- Infrastructure around Logic Locking -- Impact of Satisfiability Solvers on Logic Locking -- Post-Satisfiability Era: Countermeasures and Threats -- Design-for-Testability and its Impact on Logic Locking -- Emergence of Cutting-edge Technologies on Logic Locking -- Logic Locking in Future IC Supply Chain Environments -- Multilayer Approach to Logic Locking -- A Step-by-Step Guide for Protecting/Locking Your IP -- A Step-by-Step Guide for Security Evaluation of Protected/Locked IP. |
| Record Nr. | UNINA-9910760263503321 |
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Zamiri Azar Kimia
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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