ESD in silicon integrated circuits |
Autore | Amerasekera E. A |
Edizione | [2nd ed.] |
Pubbl/distr/stampa | [Place of publication not identified], : J Wiley, 2002 |
Descrizione fisica | 1 online resource (421 pages) |
Disciplina | 621.3815/2 |
Soggetto topico |
Semiconductors - Protection
Integrated circuits - Protection Electrostatics Static eliminators Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
ISBN |
1-280-55472-X
9786610554720 0-470-85212-7 0-470-84605-4 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Record Nr. | UNINA-9910146249503321 |
Amerasekera E. A | ||
[Place of publication not identified], : J Wiley, 2002 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|
System level ESD co-design / / edited by Charvaka Duvvury, Harald Gossner |
Pubbl/distr/stampa | West Sussex, England : , : Wiley-IEEE Press, , 2015 |
Descrizione fisica | 1 online resource (533 p.) |
Disciplina | 537/.2 |
Collana | Wiley - IEEE |
Soggetto topico |
Shielding (Electricity)
Electronic apparatus and appliances - Design and construction Integrated circuits - Design and construction Integrated circuits - Protection Electrostatics Static eliminators |
ISBN |
1-118-86188-4
1-118-86184-1 9781118861899 |
Classificazione | TEC031000 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | Machine generated contents note: Chapter 1 Introduction Charvaka Duvvury Chapter 2 Component Versus System Level ESD Charvaka Duvvury and Harald Gossner Chapter 3 System Level Testing for ESD Susceptibility Michael Hopkins Chapter 4 PCB/IC Co-Design Concepts for SEED Harald Gossner and Charvaka Duvvury Chapter 5 Hard Fails & PCB Protection Devices Robert Ashton Chapter 6 Soft Fail and PCB design measures David Pommerenke and Pratik Maheshwari Chapter 7 ESD in Mobile Devices Matti Uusimaki Chapter 8 ESD for Automotive Applications Wolfgang Reinprecht Chapter 9 Futire Applications of SEED Methodology Harald Gossner and Charvaka Duvvury Chapter 10 Co-Design Tradeoffs: Balancing Robustness, Performance and Cost Jeffery C. Dunnihoo Index . |
Record Nr. | UNINA-9910166633803321 |
West Sussex, England : , : Wiley-IEEE Press, , 2015 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|
System level ESD co-design / / edited by Charvaka Duvvury, Harald Gossner |
Pubbl/distr/stampa | West Sussex, England : , : Wiley-IEEE Press, , 2015 |
Descrizione fisica | 1 online resource (533 p.) |
Disciplina | 537/.2 |
Collana | Wiley - IEEE |
Soggetto topico |
Shielding (Electricity)
Electronic apparatus and appliances - Design and construction Integrated circuits - Design and construction Integrated circuits - Protection Electrostatics Static eliminators |
ISBN |
1-118-86188-4
1-118-86184-1 9781118861899 |
Classificazione | TEC031000 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | Machine generated contents note: Chapter 1 Introduction Charvaka Duvvury Chapter 2 Component Versus System Level ESD Charvaka Duvvury and Harald Gossner Chapter 3 System Level Testing for ESD Susceptibility Michael Hopkins Chapter 4 PCB/IC Co-Design Concepts for SEED Harald Gossner and Charvaka Duvvury Chapter 5 Hard Fails & PCB Protection Devices Robert Ashton Chapter 6 Soft Fail and PCB design measures David Pommerenke and Pratik Maheshwari Chapter 7 ESD in Mobile Devices Matti Uusimaki Chapter 8 ESD for Automotive Applications Wolfgang Reinprecht Chapter 9 Futire Applications of SEED Methodology Harald Gossner and Charvaka Duvvury Chapter 10 Co-Design Tradeoffs: Balancing Robustness, Performance and Cost Jeffery C. Dunnihoo Index . |
Record Nr. | UNINA-9910807341103321 |
West Sussex, England : , : Wiley-IEEE Press, , 2015 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|