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CODES+ISSS 2007 : Embedded Systems Week 2007 : International Conference on Hardware/Software Codesign and System Synthesis : Sept. 30 - Oct. 3, 2007, Salzburg, Austria
| CODES+ISSS 2007 : Embedded Systems Week 2007 : International Conference on Hardware/Software Codesign and System Synthesis : Sept. 30 - Oct. 3, 2007, Salzburg, Austria |
| Autore | Ha Soonhoi |
| Pubbl/distr/stampa | [Place of publication not identified], : ACM, 2007 |
| Descrizione fisica | 1 online resource (266 pages) |
| Collana | ACM Conferences |
| Soggetto topico |
Electrical & Computer Engineering
Engineering & Applied Sciences Electrical Engineering |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | CODES+ISSS '07 |
| Record Nr. | UNISA-996199660303316 |
Ha Soonhoi
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| [Place of publication not identified], : ACM, 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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CODES+ISSS 2007 : Embedded Systems Week 2007 : International Conference on Hardware/Software Codesign and System Synthesis : Sept. 30 - Oct. 3, 2007, Salzburg, Austria
| CODES+ISSS 2007 : Embedded Systems Week 2007 : International Conference on Hardware/Software Codesign and System Synthesis : Sept. 30 - Oct. 3, 2007, Salzburg, Austria |
| Autore | Ha Soonhoi |
| Pubbl/distr/stampa | [Place of publication not identified], : ACM, 2007 |
| Descrizione fisica | 1 online resource (266 pages) |
| Collana | ACM Conferences |
| Soggetto topico |
Electrical & Computer Engineering
Engineering & Applied Sciences Electrical Engineering |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | CODES+ISSS '07 |
| Record Nr. | UNINA-9910138565603321 |
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Ha Soonhoi
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| [Place of publication not identified], : ACM, 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Dependable embedded systems / / editors, Jörg Henkel, Nikil Dutt
| Dependable embedded systems / / editors, Jörg Henkel, Nikil Dutt |
| Autore | Henkel Jörg |
| Edizione | [1st edition 2021.] |
| Pubbl/distr/stampa | Springer Nature, 2021 |
| Descrizione fisica | 1 online resource (XIII, 608 p. 293 illus., 250 illus. in color.) |
| Disciplina | 621.3815 |
| Collana | Embedded systems (Springer (Firm)) |
| Soggetto topico |
Electronic circuits
Computer engineering Internet of things Embedded computer systems Microprocessors |
| ISBN | 3-030-52017-X |
| Classificazione | COM011000TEC007000TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Design of efficient, dependable SoCs based on cross-layer-reliability approach with emphasis on wireless communication as application and DRAM memories -- CRAU: Compositional System-Level Reliability Analysis in the Presence of Uncertainties -- Semantics-aware Soft Error Handling for Embedded Systems using Compiler-OS Interaction -- ARES: Self-Adaptive Coarse-Grained Reconfigurable Architectures as Reliability Enhancers in Embedded Systems -- Cross-Layer Techniques for Dependable Software Execution on Embedded Systems -- Ambrosia: Cross-layer Modeling and Mitigation of Aging Effects in Embedded Systems -- Cross-Layer Dependability for Embedded Hardware/Software Systems -- Fault-Tolerant Computing with Heterogeneous Hardware/Software Hardening Modes -- Robust Computing for Machine Learning-Based Systems -- Hardening embedded system software -- LIFT: Lifting Device-Level Characteristics for Error Resilient System Level Design: A Crosslayer Approach -- VirTherm-3D: Communication Virtualization Enabling System Management for Dependable 3D MPSoCs -- OTERA: Online Test Strategies for Reliable Reconfigurable Architectures -- Variability-Aware Software: Recent Results and Contributions -- EM Lifetime Constrained Optimization for Multi-Segment Power Grid Networks -- Lightweight Software-Assisted Memory Error Correction -- Reliability-Driven Resource Management for Multi-Core Systems-on-Chip -- Monitor Circuits for Device-Circuit Interaction -- PERCIES: Providing Efficient Reliability in Critical Embedded Systems. |
| Record Nr. | UNINA-9910427734503321 |
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Henkel Jörg
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| Springer Nature, 2021 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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On-chip communication architectures : system on chip interconnect / / Sudeep Pasricha, Nikil Dutt
| On-chip communication architectures : system on chip interconnect / / Sudeep Pasricha, Nikil Dutt |
| Autore | Pasricha Sudeep |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier / Morgan Kaufmann Publishers, c2008 |
| Descrizione fisica | 1 online resource (541 p.) |
| Disciplina | 621.3815 |
| Altri autori (Persone) | DuttNikil |
| Collana | Systems on Silicon |
| Soggetto topico |
Systems on a chip
Microcomputers - Buses Computer architecture Interconnects (Integrated circuit technology) |
| ISBN |
9786611370947
9781281370945 1281370940 9780080558288 0080558283 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; On-Chip Communication Architectures: System on Chip Interconnect; Copyright Page; Contents; Preface; About the Authors; Acknowledgments; List of Contributors; CHAPTER 1 Introduction; 1.1. Trends in System-On-Chip Design; 1.2. Coping with Soc Design Complexity; 1.3. ESL Design Flow; 1.4. On-Chip Communication Architectures: A Quick Look; 1.5. Book Outline; CHAPTER 2 Basic Concepts of Bus-Based Communication Architectures; 2.1. Terminology; 2.2. Characteristics of Bus-Based Communication Architectures; 2.3. Data Transfer Modes; 2.4. Bus Topology Types
2.5. Physical Implementation of Bus Wires2.6. Discussion: Buses in the DSM Era; 2.7. Summary; CHAPTER 3 On-Chip Communication Architecture Standards; 3.1. Standard On-Chip Bus-Based Communication Architectures; 3.2. Socket-Based On-Chip Bus Interface Standards; 3.3. Discussion: Off-Chip Bus Architecture Standards; 3.4. Summary; CHAPTER 4 Models for Performance Exploration; 4.1. Static Performance Estimation Models; 4.2. Dynamic (Simulation-Based) Performance Estimation Models; 4.3. Hybrid Communication Architecture Performance Estimation Approaches; 4.4. Summary CHAPTER 5 Models for Power and Thermal Estimation5.1. Bus Wire Power Models; 5.2. Comprehensive Bus Architecture Power Models; 5.3. Bus Wire Thermal Models; 5.4. Discussion: PVT Variation-Aware Power Estimation; 5.5. Summary; CHAPTER 6 Synthesis of On-Chip Communication Architectures; 6.1. Bus Topology Synthesis; 6.2. Bus Protocol Parameter Synthesis; 6.3. Bus Topology and Protocol Parameter Synthesis; 6.4. Physical Implementation Aware Synthesis; 6.5. Memory-Communication Architecture Co-synthesis; 6.6. Discussion: Physical and Circuit Level Design of On-Chip Communication Architectures 6.7. SummaryCHAPTER 7 Encoding Techniques for On-Chip Communication Architectures; 7.1. Techniques for Power Reduction; 7.2. Techniques for Reducing Capacitive Crosstalk Delay; 7.3. Techniques for Reducing Power and Capacitive Crosstalk Effects; 7.4. Techniques for Reducing Inductive Crosstalk Effects; 7.5. Techniques for Fault Tolerance and Reliability; 7.6. Summary; CHAPTER 8 Custom Bus-Based On-Chip Communication Architecture Design; 8.1. Split Bus Architectures; 8.2. Serial Bus Architectures; 8.3. CDMA-Based Bus Architectures; 8.4. Asynchronous Bus Architectures 8.5. Dynamically Reconfigurable Bus Architectures8.6. Summary; CHAPTER 9 On-Chip Communication Architecture Refinement and Interface Synthesis; 9.1. On-Chip Communication Architecture Refinement; 9.2. Interface Synthesis; 9.3. Discussion: Interface Synthesis; 9.4. Summary; CHAPTER 10 Verification and Security Issues in On-Chip Communication Architecture Design; 10.1. Verification of On-Chip Communication Protocols; 10.2. Compliance Verification for IP Block Integration; 10.3. Basic Concepts of SoC Security; 10.4. Security Support in Standard Bus Protocols 10.5. Communication Architecture Enhancements for Improving SoC Security |
| Record Nr. | UNINA-9911006627103321 |
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Pasricha Sudeep
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| Amsterdam ; ; Boston, : Elsevier / Morgan Kaufmann Publishers, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Proceedings of the 48th Design Automation Conference
| Proceedings of the 48th Design Automation Conference |
| Pubbl/distr/stampa | [Place of publication not identified], : ACM, 2011 |
| Descrizione fisica | 1 online resource (1055 pages) |
| Collana | ACM Conferences |
| Soggetto topico |
Civil & Environmental Engineering
Engineering & Applied Sciences Civil Engineering |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | DAC '11 |
| Record Nr. | UNISA-996206195903316 |
| [Place of publication not identified], : ACM, 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Proceedings of the 48th Design Automation Conference
| Proceedings of the 48th Design Automation Conference |
| Pubbl/distr/stampa | [Place of publication not identified], : ACM, 2011 |
| Descrizione fisica | 1 online resource (1055 pages) |
| Collana | ACM Conferences |
| Soggetto topico |
Civil & Environmental Engineering
Engineering & Applied Sciences Civil Engineering |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | DAC '11 |
| Record Nr. | UNINA-9910139622903321 |
| [Place of publication not identified], : ACM, 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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