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Applied Reconfigurable Computing [[electronic resource] ] : 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings / / edited by Kentaro Sano, Dimitrios Soudris, Michael Hübner, Pedro C. Diniz
Applied Reconfigurable Computing [[electronic resource] ] : 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings / / edited by Kentaro Sano, Dimitrios Soudris, Michael Hübner, Pedro C. Diniz
Edizione [1st ed. 2015.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015
Descrizione fisica 1 online resource (XVIII, 557 p. 257 illus.)
Disciplina 004
Collana Theoretical Computer Science and General Issues
Soggetto topico Computers
Computer engineering
Computer networks
Algorithms
Artificial intelligence
Application software
Computer Hardware
Computer Engineering and Networks
Artificial Intelligence
Computer and Information Systems Applications
ISBN 3-319-16214-4
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Architecture and Modeling -- Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks -- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators -- Hierarchical Dynamic Power-Gating in FPGAs -- Tools and Compilers -- Hardware Synthesis from Functional Embedded Domain-Specific Languages: A Case Study in Regular Expression Compilation -- ArchHDL: A Novel Hardware RTL Design Environment in C++ -- Operand-Value-Based Modeling of Dynamic Energy Consumption of Soft Processors in FPGA -- Systems and Applications -- Preemptive Hardware Multitasking in ReconOS -- A Fully Parallel Particle Filter Architecture for FPGAs -- TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools -- Tools and Compilers -- Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures -- SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs -- Advanced SystemC Tracing and Analysis Framework for Extra-Functional Properties -- Run-Time Partial Reconfiguration Simulation Framework Based on Dynamically Loadable Components -- Network-on-a-Chip Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays -- Centralized and Software-Based Run-Time Traffic Management Inside Configurable Regions of Interest in Mesh-Based Networks-on-Chip -- Survey on Real-Time Network-on-Chip Architectures -- Cryptography Applications Efficient SR-Latch PUF -- Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study -- Dual CLEFIA/AES Cipher Core on FPGA -- Systems and Applications -- An Efficient and Flexible FPGA Implementation of a Face Detection System -- A Flexible Software Framework for Dynamic Task Allocation on MPSoCs Evaluated in an Automotive Context -- A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank -- The Effects of System Hyper Pipelining on Three Computational Benchmarks Using FPGAs -- Extended Abstracts (Posters) -- A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable Architectures -- Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA. -- A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware -- Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures -- Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects -- Modular Acquisition and Stimulation System for Timestamp-Driven Neuroscience Experiments -- DRAM Row Activation Energy Optimization for Stride Memory Access on FPGA-Based Systems -- Acceleration of Data Streaming Classification Using Reconfigurable Technology -- On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach -- Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform -- A Challenge of Portable and High-Speed FPGA Accelerator -- Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate Array -- Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture -- Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization -- DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost -- A Flexible Multilayer Perceptron Co-processor for FPGAs -- Reconfigurable Hardware Assist for Linux Process Scheduling in Heterogeneous Multicore SoCs -- Towards Performance Modeling of 3D Memory Integrated FPGA Architectures -- Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL -- Special Session 1: Funded R&D Running and Completed Projects (Invited Papers) -- Towards Unification of Accelerated Computing and Interconnection For Extreme-Scale Computing -- SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms -- Hardware Task Scheduling for Partially Reconfigurable FPGAs -- SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring -- Special Session 2: Horizon 2020 Funded Projects (Invited Papers) -- DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications -- Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Perspective -- Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach -- COSSIM : A Novel, Comprehensible, Ultra-Fast, Security-Aware CPS Simulator.
Record Nr. UNISA-996200347303316
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
Applied Reconfigurable Computing [[electronic resource] ] : 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings / / edited by Kentaro Sano, Dimitrios Soudris, Michael Hübner, Pedro C. Diniz
Applied Reconfigurable Computing [[electronic resource] ] : 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings / / edited by Kentaro Sano, Dimitrios Soudris, Michael Hübner, Pedro C. Diniz
Edizione [1st ed. 2015.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015
Descrizione fisica 1 online resource (XVIII, 557 p. 257 illus.)
Disciplina 004
Collana Theoretical Computer Science and General Issues
Soggetto topico Computers
Computer engineering
Computer networks
Algorithms
Artificial intelligence
Application software
Computer Hardware
Computer Engineering and Networks
Artificial Intelligence
Computer and Information Systems Applications
ISBN 3-319-16214-4
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Architecture and Modeling -- Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks -- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators -- Hierarchical Dynamic Power-Gating in FPGAs -- Tools and Compilers -- Hardware Synthesis from Functional Embedded Domain-Specific Languages: A Case Study in Regular Expression Compilation -- ArchHDL: A Novel Hardware RTL Design Environment in C++ -- Operand-Value-Based Modeling of Dynamic Energy Consumption of Soft Processors in FPGA -- Systems and Applications -- Preemptive Hardware Multitasking in ReconOS -- A Fully Parallel Particle Filter Architecture for FPGAs -- TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools -- Tools and Compilers -- Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures -- SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs -- Advanced SystemC Tracing and Analysis Framework for Extra-Functional Properties -- Run-Time Partial Reconfiguration Simulation Framework Based on Dynamically Loadable Components -- Network-on-a-Chip Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays -- Centralized and Software-Based Run-Time Traffic Management Inside Configurable Regions of Interest in Mesh-Based Networks-on-Chip -- Survey on Real-Time Network-on-Chip Architectures -- Cryptography Applications Efficient SR-Latch PUF -- Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study -- Dual CLEFIA/AES Cipher Core on FPGA -- Systems and Applications -- An Efficient and Flexible FPGA Implementation of a Face Detection System -- A Flexible Software Framework for Dynamic Task Allocation on MPSoCs Evaluated in an Automotive Context -- A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank -- The Effects of System Hyper Pipelining on Three Computational Benchmarks Using FPGAs -- Extended Abstracts (Posters) -- A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable Architectures -- Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA. -- A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware -- Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures -- Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects -- Modular Acquisition and Stimulation System for Timestamp-Driven Neuroscience Experiments -- DRAM Row Activation Energy Optimization for Stride Memory Access on FPGA-Based Systems -- Acceleration of Data Streaming Classification Using Reconfigurable Technology -- On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach -- Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform -- A Challenge of Portable and High-Speed FPGA Accelerator -- Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate Array -- Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture -- Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization -- DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost -- A Flexible Multilayer Perceptron Co-processor for FPGAs -- Reconfigurable Hardware Assist for Linux Process Scheduling in Heterogeneous Multicore SoCs -- Towards Performance Modeling of 3D Memory Integrated FPGA Architectures -- Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL -- Special Session 1: Funded R&D Running and Completed Projects (Invited Papers) -- Towards Unification of Accelerated Computing and Interconnection For Extreme-Scale Computing -- SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms -- Hardware Task Scheduling for Partially Reconfigurable FPGAs -- SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring -- Special Session 2: Horizon 2020 Funded Projects (Invited Papers) -- DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications -- Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Perspective -- Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach -- COSSIM : A Novel, Comprehensible, Ultra-Fast, Security-Aware CPS Simulator.
Record Nr. UNINA-9910485011303321
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Applied Reconfigurable Computing. Architectures, Tools, and Applications [[electronic resource] ] : 20th International Symposium, ARC 2024, Aveiro, Portugal, March 20–22, 2024, Proceedings / / edited by Iouliia Skliarova, Piedad Brox Jiménez, Mário Véstias, Pedro C. Diniz
Applied Reconfigurable Computing. Architectures, Tools, and Applications [[electronic resource] ] : 20th International Symposium, ARC 2024, Aveiro, Portugal, March 20–22, 2024, Proceedings / / edited by Iouliia Skliarova, Piedad Brox Jiménez, Mário Véstias, Pedro C. Diniz
Autore Skliarova Iouliia
Edizione [1st ed. 2024.]
Pubbl/distr/stampa Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2024
Descrizione fisica 1 online resource (311 pages)
Disciplina 004
Altri autori (Persone) Brox JiménezPiedad
VéstiasMário
DinizPedro C
Collana Lecture Notes in Computer Science
Soggetto topico Computers
Computer engineering
Computer networks
Software engineering
Computer Hardware
Computer Engineering and Networks
Software Engineering
ISBN 3-031-55673-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Design Methods and Tools -- Applications and Architectures -- Special Projects Session.
Record Nr. UNINA-9910842497503321
Skliarova Iouliia  
Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2024
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Applied Reconfigurable Computing. Architectures, Tools, and Applications [[electronic resource] ] : 20th International Symposium, ARC 2024, Aveiro, Portugal, March 20–22, 2024, Proceedings / / edited by Iouliia Skliarova, Piedad Brox Jiménez, Mário Véstias, Pedro C. Diniz
Applied Reconfigurable Computing. Architectures, Tools, and Applications [[electronic resource] ] : 20th International Symposium, ARC 2024, Aveiro, Portugal, March 20–22, 2024, Proceedings / / edited by Iouliia Skliarova, Piedad Brox Jiménez, Mário Véstias, Pedro C. Diniz
Autore Skliarova Iouliia
Edizione [1st ed. 2024.]
Pubbl/distr/stampa Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2024
Descrizione fisica 1 online resource (311 pages)
Disciplina 004
Altri autori (Persone) Brox JiménezPiedad
VéstiasMário
DinizPedro C
Collana Lecture Notes in Computer Science
Soggetto topico Computers
Computer engineering
Computer networks
Software engineering
Computer Hardware
Computer Engineering and Networks
Software Engineering
ISBN 3-031-55673-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Design Methods and Tools -- Applications and Architectures -- Special Projects Session.
Record Nr. UNISA-996589546703316
Skliarova Iouliia  
Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2024
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
Applied Reconfigurable Computing. Architectures, Tools, and Applications [[electronic resource] ] : 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings / / edited by Nikolaos Voros, Michael Huebner, Georgios Keramidas, Diana Goehringer, Christos Antonopoulos, Pedro C. Diniz
Applied Reconfigurable Computing. Architectures, Tools, and Applications [[electronic resource] ] : 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings / / edited by Nikolaos Voros, Michael Huebner, Georgios Keramidas, Diana Goehringer, Christos Antonopoulos, Pedro C. Diniz
Edizione [1st ed. 2018.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018
Descrizione fisica 1 online resource (XVI, 753 p. 333 illus.)
Disciplina 004
Collana Theoretical Computer Science and General Issues
Soggetto topico Computers
Software engineering
Computer engineering
Computer networks
Computer vision
Artificial intelligence
Computer Hardware
Software Engineering
Computer Engineering and Networks
Computer Vision
Artificial Intelligence
ISBN 3-319-78890-6
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Machine Learning and Neural Networks -- Approximate FPGA-based LSTMs under Computation Time Constraints -- Redundancy-reduced MobileNet Acceleration on Reconfigurable Logic For ImageNet Classification -- Accuracy to Throughput Trade-offs for Reduced Precision Neural Networks on Reconfigurable Logic -- Deep Learning on High Performance FPGA Switching Boards: Flow-in-Cloud -- SqueezeJet: High-level Synthesis Accelerator Design for Deep Convolutional Neural Networks -- Efficient hardware acceleration of recommendation engines: a use case on collaborative filtering -- FPGA-based Design and CGRA Optimizations -- VerCoLib: Fast and Versatile Communication for FPGAs via PCI Express -- Performance Estimation of FPGA Modules for Modular Design Methodology using Artificial Neural Network -- Achieving Efficient Realization of Kalman Filter on CGRA through Algorithm-Architecture Co-design -- FPGA-based Memory Efficient Shift-And Algorithm for Regular Expression Matching -- Towards an optimized multi FPGA architecture with STDM network: a preliminary study -- Applications and Surveys -- An FPGA/HMC-based Accelerator for Resolution Proof Checking -- An Efficient FPGA Implementation of the Big Bang-Big Crunch Optimization Algorithm -- ReneGENE-GI: Empowering Precision Genomics with FPGAs on HPCs.-FPGA-based Parallel Pattern Matching -- Embedded Vision Systems: A Review of the Literature -- A Survey of Low Power Design Techniques for Last Level Caches -- Fault-Tolerance, Security and Communication Architectures -- ISA-DTMR: Selective Protection in Configurable Heterogeneous Multicores -- Analyzing AXI Streaming Interface for Hardware Acceleration in AP-SoC under Soft Errors -- High Performance UDP/IP 40Gb Ethernet Stack for FPGAs -- Tackling Wireless Sensor Network Heterogeneity Through Novel Reconfigurable Gateway Approach -- A Low-Power FPGA-Based Architecture for Microphone Arrays in Wireless Sensor Networks -- A Hybrid FPGA Trojan Detection Technique Based-on Combinatorial Testing and On-chip Sensing -- HoneyWiN: Novel Honeycomb-based Wireless NoC Architecture in Many-Core Era -- Reconfigurable and Adaptive Architectures -- Fast Partial Reconfiguration on SRAM-based FPGAs: A Frame-Driven Routing Approach -- A Dynamic Partial Reconfigurable Overlay Framework for Python -- Runtime Adaptive Cache for the LEON3 Processor -- Exploiting Partial Reconfiguration on a Dynamic Coarse Grained Reconfigurable Architecture -- DIM-VEX: Exploiting Design Time Configurability and Runtime Reconfigurability -- The use of HACP+SBT lossless compression in optimizing memory bandwidth requirement for hardware implementation of background modelling algorithms -- A Reconfigurable PID Controller -- Design Methods and Fast Prototyping -- High-Level Synthesis of Software-defined MPSoCs -- Improved High-Level Synthesis for Complex CellML Models -- An Intrusive Dynamic Reconfigurable Cycle-accurate Debugging System for Embedded Processors -- Rapid prototyping and verification of hardware modules generated using HLS -- Comparing C and SystemC Based HLS Methods for Reconfigurable Systems Design -- Fast DSE for Automated Parallelization of Embedded Legacy Applications -- Control Flow Analysis for Embedded Multi-Core Hybrid Systems -- FPGA-based Design and Applications -- A Low-Cost BRAM-based Function Reuse for Configurable Soft-Core Processors in FPGAs -- A Parallel-Pipelined OFDM Baseband Modulator with Dynamic Frequency Scaling for 5G Systems -- Area-Energy Aware Dataow Optimisation of Visual Tracking Systems -- Fast Carry Chain based Architectures for Two's Complement to CSD Recoding on FPGAs -- Exploring Functional Acceleration of OpenCL on FPGAs and GPUs Through Platform-Independent Optimizations -- ReneGENE-Novo: Co-designed Algorithm-Architecture for Accelerated Preprocessing and Assembly of Genomic Short Reads -- An OpenCL Implementation of WebP Accelerator on FPGAs -- Efficient Multitasking on FPGA Using HDL-based Checkpointing -- High Level Synthesis Implementation of Object Tracking Algorithm on Reconfigurable Hardware -- Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks for Quantum Computing Systems -- Reconfigurable IP-Based Spectral Interference Canceller -- FPGA-Assisted Distribution Grid Simulator -- Analyzing the Use of Taylor Series Approximation in Hardware and Embedded Software for Good Cost-Accuracy Tradeoffs -- Special Session: Research Projects -- CGRA Tool Flow for Fast Run-Time Reconfiguration -- Seamless FPGA deployment over Spark in cloud computing: A use case on Machine learning hardware acceleration -- The ARAMiS Project Initiative: Multicore Systems in Safety- and Mixed-Critical Applications -- Mapping and scheduling hard real time applications on multicore systems - The ARGO approach -- Robots in assisted living environments as an unobtrusive, efficient, reliable and modular solution for independent ageing: The RADIO Experience -- HLS Algorithmic Explorations for HPC Execution on Reconfigurable Hardware ECOSCALE -- Supporting uTilities for Heterogeneous EMbedded image processing platforms (STHEM): An Overview.
Record Nr. UNISA-996466234403316
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
Applied Reconfigurable Computing. Architectures, Tools, and Applications [[electronic resource] ] : 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings / / edited by Nikolaos Voros, Michael Huebner, Georgios Keramidas, Diana Goehringer, Christos Antonopoulos, Pedro C. Diniz
Applied Reconfigurable Computing. Architectures, Tools, and Applications [[electronic resource] ] : 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings / / edited by Nikolaos Voros, Michael Huebner, Georgios Keramidas, Diana Goehringer, Christos Antonopoulos, Pedro C. Diniz
Edizione [1st ed. 2018.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018
Descrizione fisica 1 online resource (XVI, 753 p. 333 illus.)
Disciplina 004
Collana Theoretical Computer Science and General Issues
Soggetto topico Computers
Software engineering
Computer engineering
Computer networks
Computer vision
Artificial intelligence
Computer Hardware
Software Engineering
Computer Engineering and Networks
Computer Vision
Artificial Intelligence
ISBN 3-319-78890-6
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Machine Learning and Neural Networks -- Approximate FPGA-based LSTMs under Computation Time Constraints -- Redundancy-reduced MobileNet Acceleration on Reconfigurable Logic For ImageNet Classification -- Accuracy to Throughput Trade-offs for Reduced Precision Neural Networks on Reconfigurable Logic -- Deep Learning on High Performance FPGA Switching Boards: Flow-in-Cloud -- SqueezeJet: High-level Synthesis Accelerator Design for Deep Convolutional Neural Networks -- Efficient hardware acceleration of recommendation engines: a use case on collaborative filtering -- FPGA-based Design and CGRA Optimizations -- VerCoLib: Fast and Versatile Communication for FPGAs via PCI Express -- Performance Estimation of FPGA Modules for Modular Design Methodology using Artificial Neural Network -- Achieving Efficient Realization of Kalman Filter on CGRA through Algorithm-Architecture Co-design -- FPGA-based Memory Efficient Shift-And Algorithm for Regular Expression Matching -- Towards an optimized multi FPGA architecture with STDM network: a preliminary study -- Applications and Surveys -- An FPGA/HMC-based Accelerator for Resolution Proof Checking -- An Efficient FPGA Implementation of the Big Bang-Big Crunch Optimization Algorithm -- ReneGENE-GI: Empowering Precision Genomics with FPGAs on HPCs.-FPGA-based Parallel Pattern Matching -- Embedded Vision Systems: A Review of the Literature -- A Survey of Low Power Design Techniques for Last Level Caches -- Fault-Tolerance, Security and Communication Architectures -- ISA-DTMR: Selective Protection in Configurable Heterogeneous Multicores -- Analyzing AXI Streaming Interface for Hardware Acceleration in AP-SoC under Soft Errors -- High Performance UDP/IP 40Gb Ethernet Stack for FPGAs -- Tackling Wireless Sensor Network Heterogeneity Through Novel Reconfigurable Gateway Approach -- A Low-Power FPGA-Based Architecture for Microphone Arrays in Wireless Sensor Networks -- A Hybrid FPGA Trojan Detection Technique Based-on Combinatorial Testing and On-chip Sensing -- HoneyWiN: Novel Honeycomb-based Wireless NoC Architecture in Many-Core Era -- Reconfigurable and Adaptive Architectures -- Fast Partial Reconfiguration on SRAM-based FPGAs: A Frame-Driven Routing Approach -- A Dynamic Partial Reconfigurable Overlay Framework for Python -- Runtime Adaptive Cache for the LEON3 Processor -- Exploiting Partial Reconfiguration on a Dynamic Coarse Grained Reconfigurable Architecture -- DIM-VEX: Exploiting Design Time Configurability and Runtime Reconfigurability -- The use of HACP+SBT lossless compression in optimizing memory bandwidth requirement for hardware implementation of background modelling algorithms -- A Reconfigurable PID Controller -- Design Methods and Fast Prototyping -- High-Level Synthesis of Software-defined MPSoCs -- Improved High-Level Synthesis for Complex CellML Models -- An Intrusive Dynamic Reconfigurable Cycle-accurate Debugging System for Embedded Processors -- Rapid prototyping and verification of hardware modules generated using HLS -- Comparing C and SystemC Based HLS Methods for Reconfigurable Systems Design -- Fast DSE for Automated Parallelization of Embedded Legacy Applications -- Control Flow Analysis for Embedded Multi-Core Hybrid Systems -- FPGA-based Design and Applications -- A Low-Cost BRAM-based Function Reuse for Configurable Soft-Core Processors in FPGAs -- A Parallel-Pipelined OFDM Baseband Modulator with Dynamic Frequency Scaling for 5G Systems -- Area-Energy Aware Dataow Optimisation of Visual Tracking Systems -- Fast Carry Chain based Architectures for Two's Complement to CSD Recoding on FPGAs -- Exploring Functional Acceleration of OpenCL on FPGAs and GPUs Through Platform-Independent Optimizations -- ReneGENE-Novo: Co-designed Algorithm-Architecture for Accelerated Preprocessing and Assembly of Genomic Short Reads -- An OpenCL Implementation of WebP Accelerator on FPGAs -- Efficient Multitasking on FPGA Using HDL-based Checkpointing -- High Level Synthesis Implementation of Object Tracking Algorithm on Reconfigurable Hardware -- Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks for Quantum Computing Systems -- Reconfigurable IP-Based Spectral Interference Canceller -- FPGA-Assisted Distribution Grid Simulator -- Analyzing the Use of Taylor Series Approximation in Hardware and Embedded Software for Good Cost-Accuracy Tradeoffs -- Special Session: Research Projects -- CGRA Tool Flow for Fast Run-Time Reconfiguration -- Seamless FPGA deployment over Spark in cloud computing: A use case on Machine learning hardware acceleration -- The ARAMiS Project Initiative: Multicore Systems in Safety- and Mixed-Critical Applications -- Mapping and scheduling hard real time applications on multicore systems - The ARGO approach -- Robots in assisted living environments as an unobtrusive, efficient, reliable and modular solution for independent ageing: The RADIO Experience -- HLS Algorithmic Explorations for HPC Execution on Reconfigurable Hardware ECOSCALE -- Supporting uTilities for Heterogeneous EMbedded image processing platforms (STHEM): An Overview.
Record Nr. UNINA-9910349424103321
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui