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Computer Aided Verification [[electronic resource] ] : 31st International Conference, CAV 2019, New York City, NY, USA, July 15-18, 2019, Proceedings, Part II / / edited by Isil Dillig, Serdar Tasiran
| Computer Aided Verification [[electronic resource] ] : 31st International Conference, CAV 2019, New York City, NY, USA, July 15-18, 2019, Proceedings, Part II / / edited by Isil Dillig, Serdar Tasiran |
| Autore | Dillig Isil |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (XX, 549 p. 1209 illus., 42 illus. in color.) |
| Disciplina | 005.1 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Software engineering
Computer science Machine theory Electronic digital computers—Evaluation Computers Professions Logic programming Software Engineering Computer Science Logic and Foundations of Programming Formal Languages and Automata Theory System Performance and Evaluation The Computing Profession Logic in AI |
| ISBN | 3-030-25543-3 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Logics, Decision Procedures, and Solvers -- Satisfiability Checking for Mission-Time LTL -- High-Level Abstractions for Simplifying Extended String Constraints in SMT -- Alternating Automata Modulo First Order Theories -- Q3B: An Efficient BDD-based SMT Solver for Quantified Bit-Vectors -- CVC4SY: Smart and Fast Term Enumeration for Syntax-Guided Synthesis -- Incremental Determinization for Quantifier Elimination and Functional Synthesis -- Numerical Programs -- Loop Summarization with Rational Vector Addition Systems -- Invertibility Conditions for Floating-Point Formulas -- Numerically-Robust Inductive Proof Rules for Continuous Dynamical Systems -- Icing: Supporting Fast-math Style Optimizations in a Verified Compiler -- Sound Approximation of Programs with Elementary Functions -- Verification -- Formal verification of quantum algorithms using quantum Hoare logic -- SecCSL: Security Concurrent Separation Logic -- Reachability Analysis for AWS-based Networks -- Distributed Systems and Networks -- Verification of Threshold-Based Distributed Algorithms by Decomposition to Decidable Logics -- Gradual Consistency Checking -- Checking Robustness Against Snapshot Isolation -- Efficient verification of network fault tolerance via counterexampleguided refinement -- On the Complexity of Checking Consistency for Replicated Data Types -- Communication-closed asynchronous protocols -- Verification and Invariants -- Interpolating Strong Induction -- Verifying Asynchronous Event-Driven Programs Using Partial Abstract Transformers -- Inferring Inductive Invariants from Phase Structures -- Termination of Triangular Integer Loops is Decidable -- AliveInLean: A Verified LLVM Peephole Optimization Verifier -- Concurrency -- Automated Parameterized Verification of CRDTs -- What's wrong with on-the-y partial order reduction -- Integrating Formal Schedulability Analysis into a Verifed OS Kernel -- Rely-guarantee Reasoning about Concurrent Memory Management in Zephyr RTOS -- Violat: Generating Tests of Observational Refinement for Concurrent Objects. . |
| Record Nr. | UNISA-996466366803316 |
Dillig Isil
|
||
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Computer Aided Verification [[electronic resource] ] : 31st International Conference, CAV 2019, New York City, NY, USA, July 15-18, 2019, Proceedings, Part I / / edited by Isil Dillig, Serdar Tasiran
| Computer Aided Verification [[electronic resource] ] : 31st International Conference, CAV 2019, New York City, NY, USA, July 15-18, 2019, Proceedings, Part I / / edited by Isil Dillig, Serdar Tasiran |
| Autore | Dillig Isil |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (XIX, 673 p. 1003 illus., 106 illus. in color.) |
| Disciplina | 005.1 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Software engineering
Compilers (Computer programs) Computer science Artificial intelligence Computer simulation Computer engineering Computer networks Software Engineering Compilers and Interpreters Theory of Computation Artificial Intelligence Computer Modelling Computer Engineering and Networks |
| ISBN | 3-030-25540-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Automata and Timed Systems -- Symbolic Register Automata -- Abstraction Refinement Algorithms for Timed Automata -- Fast Algorithms for Handling Diagonal Constraints in Timed Automata -- Safety and co-safety comparator automata for discounted-sum inclusion -- Clock Bound Repair for Timed Systems -- Verifying Asynchronous Interactions via Communicating Session Automata -- Security and Hyperproperties -- Verifying Hyperliveness -- Quantitative Mitigation of Timing Side Channels -- Property Directed Self Composition -- Security-Aware Synthesis Using Delayed-Action Games -- Automated Hypersafety Verification -- Automated Synthesis of Secure Platform Mappings -- Synthesis -- Synthesizing Approximate Implementations for Unrealizable Specifications -- Quantified Invariants via Syntax-Guided Synthesis -- Efficient Synthesis with Probabilistic Constraints -- Membership-based Synthesis of Linear Hybrid Automata -- Overfitting in Synthesis: Theory and Practice -- Proving Unrealizability for Syntax-Guided Synthesis -- Model Checking -- BMC for Weak Memory Models: Relation Analysis for Compact SMT Encodings -- When Human Intuition Fails: Using Formal Methods to Find an Error in the "Proof" of a Multi-Agent Protocol -- Extending NUXMV with Timed Transition Systems and Timed Temporal Properties -- Cerberus-BMC: a Principled Reference Semantics and Exploration Tool for Concurrent and Sequential C -- Cyber-physical Systems and Machine Learning -- Multi-Armed Bandits for Boolean Connectives in Hybrid System Falsification -- StreamLAB: Stream-based Monitoring of Cyber-Physical Systems -- VerifAI: A Toolkit for the Formal Design and Analysis of Artificial Intelligence-Based Systems -- The Marabou Framework for Verification and Analysis of Deep Neural Networks -- Probabilistic Systems, Runtime Techniques -- Probabilistic Bisimulation for Parameterized Systems -- Semi-Quantitative Abstraction and Analysis of Chemical Reaction Networks -- PAC Statistical Model Checking for Markov Decision Processes and Stochastic Games -- Symbolic Monitoring against Specifications Parametric in Time and Data -- STAMINA: STochastic Approximate Model-checker for INfinite-state Analysis -- Dynamical, Hybrid, and Reactive Systems -- Local and Compositional Reasoning For Optimized Reactive Systems -- Robust Controller Synthesis in Timed Büchi Automata: A Symbolic Approach -- Flexible Computational Pipelines for Robust Abstraction-based Control Synthesis -- Temporal Stream Logic: Synthesis beyond the Bools -- Run-Time Optimization for Learned Controllers through Quantitative Games -- Taming Delays in Dynamical Systems: Unbounded Verification of Delay Differential Equations. |
| Record Nr. | UNISA-996466366403316 |
|
Dillig Isil
|
||
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Computer Aided Verification : 31st International Conference, CAV 2019, New York City, NY, USA, July 15-18, 2019, Proceedings, Part II / / edited by Isil Dillig, Serdar Tasiran
| Computer Aided Verification : 31st International Conference, CAV 2019, New York City, NY, USA, July 15-18, 2019, Proceedings, Part II / / edited by Isil Dillig, Serdar Tasiran |
| Autore | Dillig Isil |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (XX, 549 p. 1209 illus., 42 illus. in color.) |
| Disciplina | 005.1 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Software engineering
Computer science Machine theory Electronic digital computers—Evaluation Computers Professions Logic programming Software Engineering Computer Science Logic and Foundations of Programming Formal Languages and Automata Theory System Performance and Evaluation The Computing Profession Logic in AI |
| ISBN | 3-030-25543-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Logics, Decision Procedures, and Solvers -- Satisfiability Checking for Mission-Time LTL -- High-Level Abstractions for Simplifying Extended String Constraints in SMT -- Alternating Automata Modulo First Order Theories -- Q3B: An Efficient BDD-based SMT Solver for Quantified Bit-Vectors -- CVC4SY: Smart and Fast Term Enumeration for Syntax-Guided Synthesis -- Incremental Determinization for Quantifier Elimination and Functional Synthesis -- Numerical Programs -- Loop Summarization with Rational Vector Addition Systems -- Invertibility Conditions for Floating-Point Formulas -- Numerically-Robust Inductive Proof Rules for Continuous Dynamical Systems -- Icing: Supporting Fast-math Style Optimizations in a Verified Compiler -- Sound Approximation of Programs with Elementary Functions -- Verification -- Formal verification of quantum algorithms using quantum Hoare logic -- SecCSL: Security Concurrent Separation Logic -- Reachability Analysis for AWS-based Networks -- Distributed Systems and Networks -- Verification of Threshold-Based Distributed Algorithms by Decomposition to Decidable Logics -- Gradual Consistency Checking -- Checking Robustness Against Snapshot Isolation -- Efficient verification of network fault tolerance via counterexampleguided refinement -- On the Complexity of Checking Consistency for Replicated Data Types -- Communication-closed asynchronous protocols -- Verification and Invariants -- Interpolating Strong Induction -- Verifying Asynchronous Event-Driven Programs Using Partial Abstract Transformers -- Inferring Inductive Invariants from Phase Structures -- Termination of Triangular Integer Loops is Decidable -- AliveInLean: A Verified LLVM Peephole Optimization Verifier -- Concurrency -- Automated Parameterized Verification of CRDTs -- What's wrong with on-the-y partial order reduction -- Integrating Formal Schedulability Analysis into a Verifed OS Kernel -- Rely-guarantee Reasoning about Concurrent Memory Management in Zephyr RTOS -- Violat: Generating Tests of Observational Refinement for Concurrent Objects. . |
| Record Nr. | UNINA-9910349314103321 |
|
Dillig Isil
|
||
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Computer Aided Verification : 31st International Conference, CAV 2019, New York City, NY, USA, July 15-18, 2019, Proceedings, Part I / / edited by Isil Dillig, Serdar Tasiran
| Computer Aided Verification : 31st International Conference, CAV 2019, New York City, NY, USA, July 15-18, 2019, Proceedings, Part I / / edited by Isil Dillig, Serdar Tasiran |
| Autore | Dillig Isil |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (XIX, 673 p. 1003 illus., 106 illus. in color.) |
| Disciplina | 005.1 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Software engineering
Compilers (Computer programs) Computer science Artificial intelligence Computer simulation Computer engineering Computer networks Software Engineering Compilers and Interpreters Theory of Computation Artificial Intelligence Computer Modelling Computer Engineering and Networks |
| ISBN | 3-030-25540-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Automata and Timed Systems -- Symbolic Register Automata -- Abstraction Refinement Algorithms for Timed Automata -- Fast Algorithms for Handling Diagonal Constraints in Timed Automata -- Safety and co-safety comparator automata for discounted-sum inclusion -- Clock Bound Repair for Timed Systems -- Verifying Asynchronous Interactions via Communicating Session Automata -- Security and Hyperproperties -- Verifying Hyperliveness -- Quantitative Mitigation of Timing Side Channels -- Property Directed Self Composition -- Security-Aware Synthesis Using Delayed-Action Games -- Automated Hypersafety Verification -- Automated Synthesis of Secure Platform Mappings -- Synthesis -- Synthesizing Approximate Implementations for Unrealizable Specifications -- Quantified Invariants via Syntax-Guided Synthesis -- Efficient Synthesis with Probabilistic Constraints -- Membership-based Synthesis of Linear Hybrid Automata -- Overfitting in Synthesis: Theory and Practice -- Proving Unrealizability for Syntax-Guided Synthesis -- Model Checking -- BMC for Weak Memory Models: Relation Analysis for Compact SMT Encodings -- When Human Intuition Fails: Using Formal Methods to Find an Error in the "Proof" of a Multi-Agent Protocol -- Extending NUXMV with Timed Transition Systems and Timed Temporal Properties -- Cerberus-BMC: a Principled Reference Semantics and Exploration Tool for Concurrent and Sequential C -- Cyber-physical Systems and Machine Learning -- Multi-Armed Bandits for Boolean Connectives in Hybrid System Falsification -- StreamLAB: Stream-based Monitoring of Cyber-Physical Systems -- VerifAI: A Toolkit for the Formal Design and Analysis of Artificial Intelligence-Based Systems -- The Marabou Framework for Verification and Analysis of Deep Neural Networks -- Probabilistic Systems, Runtime Techniques -- Probabilistic Bisimulation for Parameterized Systems -- Semi-Quantitative Abstraction and Analysis of Chemical Reaction Networks -- PAC Statistical Model Checking for Markov Decision Processes and Stochastic Games -- Symbolic Monitoring against Specifications Parametric in Time and Data -- STAMINA: STochastic Approximate Model-checker for INfinite-state Analysis -- Dynamical, Hybrid, and Reactive Systems -- Local and Compositional Reasoning For Optimized Reactive Systems -- Robust Controller Synthesis in Timed Büchi Automata: A Symbolic Approach -- Flexible Computational Pipelines for Robust Abstraction-based Control Synthesis -- Temporal Stream Logic: Synthesis beyond the Bools -- Run-Time Optimization for Learned Controllers through Quantitative Games -- Taming Delays in Dynamical Systems: Unbounded Verification of Delay Differential Equations. |
| Record Nr. | UNINA-9910349314203321 |
|
Dillig Isil
|
||
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||