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Nano-Tera.ch : Engineering the Future of Systems for Health, Environment and Energy / / by Anil Leblebici, Patrick Mayor, Martin Rajman, Giovanni De Micheli
| Nano-Tera.ch : Engineering the Future of Systems for Health, Environment and Energy / / by Anil Leblebici, Patrick Mayor, Martin Rajman, Giovanni De Micheli |
| Autore | Leblebici Anil |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (232 pages) |
| Disciplina | 620.5 |
| Soggetto topico |
Electronic circuits
Signal processing Image processing Speech processing systems Electronics Microelectronics Circuits and Systems Signal, Image and Speech Processing Electronics and Microelectronics, Instrumentation |
| ISBN | 3-319-99109-4 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Output of selected research activities -- Impact of the program -- References and contributors -- Conclusions. |
| Record Nr. | UNINA-9910337655203321 |
Leblebici Anil
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Networks on chips [[electronic resource] ] : technology and tools / / Luca Benini and Giovanni De Micheli
| Networks on chips [[electronic resource] ] : technology and tools / / Luca Benini and Giovanni De Micheli |
| Autore | Benini Luca <1967-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006 |
| Descrizione fisica | 1 online resource (408 p.) |
| Disciplina | 621.3815 |
| Altri autori (Persone) | De MicheliGiovanni |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Systems on a chip
Computer networks - Equipment and supplies |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-280-96683-1
9786610966837 0-08-047356-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Title page; Copyright Page; Table of contents; About The Authors; List of Contributors; 1 Networks on Chip; 1.1 Why On-Chip Networking?; 1.2 Technology Trends; 1.3 SoC Objectives and NoC Needs; 1.4 Once Over Lightly; 1.5 Perspectives; 2 Network Architecture: Principles and Examples; 2.1 Network Architecture; 2.2 Network Architectures for On-Chip Realization; 2.3 Ad Hoc Network Architectures; 2.4 Component Design for NoCs; 2.5 Properties of Network Architectures; 2.6 Summary; 3 Physical Network Layer; 3.1 Interconnection in DSM SoC; 3.2 High-Performance Signaling
3.3 Building Blocks3.4 Summary; 4 The Data-Link Layer in NoC Design; 4.1 Tasks of the Data-Link Layer; 4.2 On-Chip Communication Reliability; 4.3 Fault Models for NoCs; 4.4 Principles of Coding Theory; 4.5 The Power-Reliability Trade-Off; 4.6 Unified Coding Framework; 4.7 Adaptive Error Protection; 4.8 Data-Link Layer Architecture: Case Studies; 4.9 On-Chip Stochastic Communication; 4.10 Link-Level versus End-to-End Error Protection; 4.11 Flow Control; 4.12 Performance Exploration; 4.13 Summary; 5 Network and Transport Layers in Network on Chip; 5.1 Network and Transport Layers in NoCs 5.2 NoC QoS5.3 NoC Topology; 5.4 Switching Techniques; 5.5 NoC Addressing and Routing; 5.6 NoC Addressing; 5.7 Congestion Control and Flow Control; 5.8 Summary; 6 Network Interface Architecture and Design Issues; 6.1 NI Services; 6.2 NI Structure; 6.3 Evolution of Communication Protocols; 6.4 Point-to-Point Communication Protocols; 6.5 Latest Advances in Processor Interfaces; 6.6 The Packetization Stage; 6.7 End-to-End Flow Control; 6.8 Packet and Circuit Switching; 6.9 NI Architecture: The Aethereal Case Study; 6.10 NI Architecture: The xpipes Case Study 6.11 NIs for Asynchronous NoCs: The Mango Case Study6.12 Summary; 7 NoC Programming; 7.1 Architectural Template; 7.2 Task-Level Parallel Programming; 7.3 Communication-Exposed Programming; 7.4 Computer-Aided Software Development Tools; 7.5 Summary; 8 Design Methodologies and CAD Tool Flows for NoCs; 8.1 Network Analysis and Simulation; 8.2 Network Synthesis and Optimization; 8.3 Design Flows for NoCs; 8.4 Tool Kits for Designing Bus-Based Interconnect; 8.5 Summary; 9 Designs and Implementations of NoC-Based SoCs; 9.1 KAIST BONE Series; 9.2 NoC-Based Experimental Systems; 9.3 Summary; Index |
| Record Nr. | UNINA-9910458595103321 |
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Benini Luca <1967->
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| Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Networks on chips [[electronic resource] ] : technology and tools / / Luca Benini and Giovanni De Micheli
| Networks on chips [[electronic resource] ] : technology and tools / / Luca Benini and Giovanni De Micheli |
| Autore | Benini Luca <1967-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006 |
| Descrizione fisica | 1 online resource (408 p.) |
| Disciplina | 621.3815 |
| Altri autori (Persone) | De MicheliGiovanni |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Systems on a chip
Computer networks - Equipment and supplies |
| ISBN |
1-280-96683-1
9786610966837 0-08-047356-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Title page; Copyright Page; Table of contents; About The Authors; List of Contributors; 1 Networks on Chip; 1.1 Why On-Chip Networking?; 1.2 Technology Trends; 1.3 SoC Objectives and NoC Needs; 1.4 Once Over Lightly; 1.5 Perspectives; 2 Network Architecture: Principles and Examples; 2.1 Network Architecture; 2.2 Network Architectures for On-Chip Realization; 2.3 Ad Hoc Network Architectures; 2.4 Component Design for NoCs; 2.5 Properties of Network Architectures; 2.6 Summary; 3 Physical Network Layer; 3.1 Interconnection in DSM SoC; 3.2 High-Performance Signaling
3.3 Building Blocks3.4 Summary; 4 The Data-Link Layer in NoC Design; 4.1 Tasks of the Data-Link Layer; 4.2 On-Chip Communication Reliability; 4.3 Fault Models for NoCs; 4.4 Principles of Coding Theory; 4.5 The Power-Reliability Trade-Off; 4.6 Unified Coding Framework; 4.7 Adaptive Error Protection; 4.8 Data-Link Layer Architecture: Case Studies; 4.9 On-Chip Stochastic Communication; 4.10 Link-Level versus End-to-End Error Protection; 4.11 Flow Control; 4.12 Performance Exploration; 4.13 Summary; 5 Network and Transport Layers in Network on Chip; 5.1 Network and Transport Layers in NoCs 5.2 NoC QoS5.3 NoC Topology; 5.4 Switching Techniques; 5.5 NoC Addressing and Routing; 5.6 NoC Addressing; 5.7 Congestion Control and Flow Control; 5.8 Summary; 6 Network Interface Architecture and Design Issues; 6.1 NI Services; 6.2 NI Structure; 6.3 Evolution of Communication Protocols; 6.4 Point-to-Point Communication Protocols; 6.5 Latest Advances in Processor Interfaces; 6.6 The Packetization Stage; 6.7 End-to-End Flow Control; 6.8 Packet and Circuit Switching; 6.9 NI Architecture: The Aethereal Case Study; 6.10 NI Architecture: The xpipes Case Study 6.11 NIs for Asynchronous NoCs: The Mango Case Study6.12 Summary; 7 NoC Programming; 7.1 Architectural Template; 7.2 Task-Level Parallel Programming; 7.3 Communication-Exposed Programming; 7.4 Computer-Aided Software Development Tools; 7.5 Summary; 8 Design Methodologies and CAD Tool Flows for NoCs; 8.1 Network Analysis and Simulation; 8.2 Network Synthesis and Optimization; 8.3 Design Flows for NoCs; 8.4 Tool Kits for Designing Bus-Based Interconnect; 8.5 Summary; 9 Designs and Implementations of NoC-Based SoCs; 9.1 KAIST BONE Series; 9.2 NoC-Based Experimental Systems; 9.3 Summary; Index |
| Record Nr. | UNINA-9910784651503321 |
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Benini Luca <1967->
|
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| Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Networks on chips : technology and tools / / Luca Benini and Giovanni De Micheli
| Networks on chips : technology and tools / / Luca Benini and Giovanni De Micheli |
| Autore | Benini Luca <1967-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006 |
| Descrizione fisica | 1 online resource (408 p.) |
| Disciplina | 621.3815 |
| Altri autori (Persone) | De MicheliGiovanni |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Systems on a chip
Computer networks - Equipment and supplies |
| ISBN |
1-280-96683-1
9786610966837 0-08-047356-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Title page; Copyright Page; Table of contents; About The Authors; List of Contributors; 1 Networks on Chip; 1.1 Why On-Chip Networking?; 1.2 Technology Trends; 1.3 SoC Objectives and NoC Needs; 1.4 Once Over Lightly; 1.5 Perspectives; 2 Network Architecture: Principles and Examples; 2.1 Network Architecture; 2.2 Network Architectures for On-Chip Realization; 2.3 Ad Hoc Network Architectures; 2.4 Component Design for NoCs; 2.5 Properties of Network Architectures; 2.6 Summary; 3 Physical Network Layer; 3.1 Interconnection in DSM SoC; 3.2 High-Performance Signaling
3.3 Building Blocks3.4 Summary; 4 The Data-Link Layer in NoC Design; 4.1 Tasks of the Data-Link Layer; 4.2 On-Chip Communication Reliability; 4.3 Fault Models for NoCs; 4.4 Principles of Coding Theory; 4.5 The Power-Reliability Trade-Off; 4.6 Unified Coding Framework; 4.7 Adaptive Error Protection; 4.8 Data-Link Layer Architecture: Case Studies; 4.9 On-Chip Stochastic Communication; 4.10 Link-Level versus End-to-End Error Protection; 4.11 Flow Control; 4.12 Performance Exploration; 4.13 Summary; 5 Network and Transport Layers in Network on Chip; 5.1 Network and Transport Layers in NoCs 5.2 NoC QoS5.3 NoC Topology; 5.4 Switching Techniques; 5.5 NoC Addressing and Routing; 5.6 NoC Addressing; 5.7 Congestion Control and Flow Control; 5.8 Summary; 6 Network Interface Architecture and Design Issues; 6.1 NI Services; 6.2 NI Structure; 6.3 Evolution of Communication Protocols; 6.4 Point-to-Point Communication Protocols; 6.5 Latest Advances in Processor Interfaces; 6.6 The Packetization Stage; 6.7 End-to-End Flow Control; 6.8 Packet and Circuit Switching; 6.9 NI Architecture: The Aethereal Case Study; 6.10 NI Architecture: The xpipes Case Study 6.11 NIs for Asynchronous NoCs: The Mango Case Study6.12 Summary; 7 NoC Programming; 7.1 Architectural Template; 7.2 Task-Level Parallel Programming; 7.3 Communication-Exposed Programming; 7.4 Computer-Aided Software Development Tools; 7.5 Summary; 8 Design Methodologies and CAD Tool Flows for NoCs; 8.1 Network Analysis and Simulation; 8.2 Network Synthesis and Optimization; 8.3 Design Flows for NoCs; 8.4 Tool Kits for Designing Bus-Based Interconnect; 8.5 Summary; 9 Designs and Implementations of NoC-Based SoCs; 9.1 KAIST BONE Series; 9.2 NoC-Based Experimental Systems; 9.3 Summary; Index |
| Record Nr. | UNINA-9910809103403321 |
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Benini Luca <1967->
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||
| Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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VLSI-SoC: New Technology Enabler [[electronic resource] ] : 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco, Peru, October 6–9, 2019, Revised and Extended Selected Papers / / edited by Carolina Metzler, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Carlos Silva-Cardenas, Ricardo Reis
| VLSI-SoC: New Technology Enabler [[electronic resource] ] : 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco, Peru, October 6–9, 2019, Revised and Extended Selected Papers / / edited by Carolina Metzler, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Carlos Silva-Cardenas, Ricardo Reis |
| Edizione | [1st ed. 2020.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 |
| Descrizione fisica | 1 online resource (XVII, 345 p. 214 illus., 129 illus. in color.) |
| Disciplina | 621.395 |
| Collana | IFIP Advances in Information and Communication Technology |
| Soggetto topico |
Computer organization
Microprogramming Input-output equipment (Computers) Operating systems (Computers) Computer Systems Organization and Communication Networks Control Structures and Microprogramming Input/Output and Data Communications Operating Systems |
| ISBN | 3-030-53273-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Software-Based Self-Test for Delay Faults -- On Test Generation for Microprocessors for Extended Class of Functional Faults -- Robust FinFET Schmitt Trigger Designs for Low Power Applications -- An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults -- Process Variability Impact on the SET Response of FinFET Multi-level Design -- Efficient Soft Error Vulnerability Analysis Using Non-Intrusive Fault Injection Techniques -- A Statistical Wafer Scale Error and Redundancy Analysis Simulator -- Hardware-enabled Secure Firmware Updates in Embedded Systems -- Reliability Enhanced Digital Low-Dropout Regulator with Improved Transient Performance -- Security Aspects of Real-time MPSoCs: The Flaws and Opportunities of Preemptive NoCs -- Offset-Compensation Systems for Multi-Gbit/s Optical Receivers -- Accelerating Inference on Binary Neural Networks with Digital RRAM Processing -- Semi- and Fully-Random Access LUTs for Smooth Functions -- A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors -- Exploiting Heterogeneous Mobile Architectures through a Unified Runtime Framework. |
| Record Nr. | UNISA-996465341603316 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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VLSI-SoC: New Technology Enabler : 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco, Peru, October 6–9, 2019, Revised and Extended Selected Papers / / edited by Carolina Metzler, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Carlos Silva-Cardenas, Ricardo Reis
| VLSI-SoC: New Technology Enabler : 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco, Peru, October 6–9, 2019, Revised and Extended Selected Papers / / edited by Carolina Metzler, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Carlos Silva-Cardenas, Ricardo Reis |
| Edizione | [1st ed. 2020.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 |
| Descrizione fisica | 1 online resource (XVII, 345 p. 214 illus., 129 illus. in color.) |
| Disciplina | 621.395 |
| Collana | IFIP Advances in Information and Communication Technology |
| Soggetto topico |
Computer organization
Microprogramming Input-output equipment (Computers) Operating systems (Computers) Computer Systems Organization and Communication Networks Control Structures and Microprogramming Input/Output and Data Communications Operating Systems |
| ISBN | 3-030-53273-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Software-Based Self-Test for Delay Faults -- On Test Generation for Microprocessors for Extended Class of Functional Faults -- Robust FinFET Schmitt Trigger Designs for Low Power Applications -- An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults -- Process Variability Impact on the SET Response of FinFET Multi-level Design -- Efficient Soft Error Vulnerability Analysis Using Non-Intrusive Fault Injection Techniques -- A Statistical Wafer Scale Error and Redundancy Analysis Simulator -- Hardware-enabled Secure Firmware Updates in Embedded Systems -- Reliability Enhanced Digital Low-Dropout Regulator with Improved Transient Performance -- Security Aspects of Real-time MPSoCs: The Flaws and Opportunities of Preemptive NoCs -- Offset-Compensation Systems for Multi-Gbit/s Optical Receivers -- Accelerating Inference on Binary Neural Networks with Digital RRAM Processing -- Semi- and Fully-Random Access LUTs for Smooth Functions -- A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors -- Exploiting Heterogeneous Mobile Architectures through a Unified Runtime Framework. |
| Record Nr. | UNINA-9910413438303321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Vlsi-soc: research trends in vlsi and systems on chip : fourteenth international conference on very large scale integration of system on chip (vlsi-soc2006), october 16-18, 2006, nice, france / / edited by Giovanni De Micheli, Salvador Mir, Ricardo Reis
| Vlsi-soc: research trends in vlsi and systems on chip : fourteenth international conference on very large scale integration of system on chip (vlsi-soc2006), october 16-18, 2006, nice, france / / edited by Giovanni De Micheli, Salvador Mir, Ricardo Reis |
| Edizione | [1st ed. 2008.] |
| Pubbl/distr/stampa | New York, New York : , : Springer, , [2008] |
| Descrizione fisica | 1 online resource (396 p.) |
| Disciplina | 621.395 |
| Collana | IFIP Advances in Information and Communication Technology |
| Soggetto topico |
Cytogenetik
Pflanzenzüchtung Schwingel |
| ISBN | 0-387-74909-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Architectures for High Dynamic Range, High Speed Image Sensor Readout Circuits -- Oversampled Time Estimation Techniques for Precision Photonic Detectors -- Innovative Optoeletronic Approaches to Biomolecular Analysis with Arrays of Silicon Devices -- Electronic Detection of DNA Adsorption and Hybridization -- Probabilistic amp; Statistical Design—the Wave of the Future -- A CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs -- Probabilistic Design: A Survey of Probabilistic CMOS Technology and Future Directions for Terascale IC Design -- Reliability Issues in Deep Deep Submicron Technologies: Time-Dependent Variability and its Impact on Embedded System Design -- Soft Error Resilient System Design through Error Correction -- Library Compatible Variational Delay Computation -- A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures -- Frequency and Speed Setting for Energy Conservation in Autonomous Mobile Robots -- Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation -- Logic Synthesis of EXOR Projected Sum of Products -- A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits -- CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization -- Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation -- Comparison of an Æthereal Network on Chip and Traditional Interconnects - Two Case Studies -- Designing Routing and Message-Dependent Deadlock Free Networks on Chips -- Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model -- Human++: Emerging Technology for Body Area Networks. |
| Record Nr. | UNINA-9910482956003321 |
| New York, New York : , : Springer, , [2008] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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