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Compiler Construction [[electronic resource] ] : 22nd International Conference, CC 2013, Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2013, Rome, Italy, March 16-24, 2013, Proceedings / / edited by Koen De Bosschere, Ranjit Jhala
| Compiler Construction [[electronic resource] ] : 22nd International Conference, CC 2013, Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2013, Rome, Italy, March 16-24, 2013, Proceedings / / edited by Koen De Bosschere, Ranjit Jhala |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 |
| Descrizione fisica | 1 online resource (XVIII, 265 p. 96 illus.) |
| Disciplina | 005.453 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Compilers (Computer programs)
Software engineering Operating systems (Computers) Compilers and Interpreters Software Engineering Operating Systems |
| ISBN | 3-642-37051-9 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Programming with People: Integrating Human-Based and Digital -- Optimal Register Allocation in Polynomial Time -- Optimal and Heuristic Global Code Motion for Minimal Spilling -- Efficient and Effective Handling of Exceptions in Java Points-to Analysis -- An Incremental Points-to Analysis with CFL-Reachability -- FESA: Fold- and Expand-Based Shape Analysis -- Simple and Efficient Construction of Static Single Assignment Form -- PolyGLoT: A Polyhedral Loop Transformation Framework for a Graphical Dataflow Language -- Architecture-Independent Dynamic Information Flow Tracking -- On the Determination of Inlining Vectors for Program Optimization -- Automatic Generation of Program Affinity Policies Using Machine Learning -- Compiler-Guided Identification of Critical Sections in Parallel Code -- Refactoring MATLAB -- On LR Parsing with Selective Delays. |
| Record Nr. | UNISA-996465683903316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Compiler Construction [[electronic resource] ] : 22nd International Conference, CC 2013, Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2013, Rome, Italy, March 16-24, 2013, Proceedings / / edited by Koen De Bosschere, Ranjit Jhala
| Compiler Construction [[electronic resource] ] : 22nd International Conference, CC 2013, Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2013, Rome, Italy, March 16-24, 2013, Proceedings / / edited by Koen De Bosschere, Ranjit Jhala |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 |
| Descrizione fisica | 1 online resource (XVIII, 265 p. 96 illus.) |
| Disciplina | 005.453 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Compilers (Computer programs)
Software engineering Operating systems (Computers) Compilers and Interpreters Software Engineering Operating Systems |
| ISBN | 3-642-37051-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Programming with People: Integrating Human-Based and Digital -- Optimal Register Allocation in Polynomial Time -- Optimal and Heuristic Global Code Motion for Minimal Spilling -- Efficient and Effective Handling of Exceptions in Java Points-to Analysis -- An Incremental Points-to Analysis with CFL-Reachability -- FESA: Fold- and Expand-Based Shape Analysis -- Simple and Efficient Construction of Static Single Assignment Form -- PolyGLoT: A Polyhedral Loop Transformation Framework for a Graphical Dataflow Language -- Architecture-Independent Dynamic Information Flow Tracking -- On the Determination of Inlining Vectors for Program Optimization -- Automatic Generation of Program Affinity Policies Using Machine Learning -- Compiler-Guided Identification of Critical Sections in Parallel Code -- Refactoring MATLAB -- On LR Parsing with Selective Delays. |
| Record Nr. | UNINA-9910483044603321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
High Performance Embedded Architectures and Compilers [[electronic resource] ] : Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings / / edited by Koen De Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer
| High Performance Embedded Architectures and Compilers [[electronic resource] ] : Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings / / edited by Koen De Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer |
| Edizione | [1st ed. 2007.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 |
| Descrizione fisica | 1 online resource (297 p.) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Computer arithmetic and logic units Microprocessors Computer architecture Computer input-output equipment Logic design Computer networks Theory of Computation Arithmetic and Logic Structures Processor Architectures Input/Output and Data Communications Logic Design Computer Communication Networks |
| ISBN | 3-540-69338-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Program -- Keynote: Insight, Not (Random) Numbers: An Embedded Perspective -- I Secure and Low-Power Embedded Memory Systems -- Compiler-Assisted Memory Encryption for Embedded Processors -- Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems -- Applying Decay to Reduce Dynamic Power in Set-Associative Caches -- II Architecture/Compiler Optimizations for Efficient Embedded Processing -- Virtual Registers: Reducing Register Pressure Without Enlarging the Register File -- Bounds Checking with Taint-Based Analysis -- Reducing Exit Stub Memory Consumption in Code Caches -- III Adaptive Microarchitectures -- Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling -- Fetch Gating Control Through Speculative Instruction Window Weighting -- Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches -- Branch History Matching: Branch Predictor Warmup for Sampled Simulation -- Sunflower : Full-System, Embedded Microarchitecture Evaluation -- Efficient Program Power Behavior Characterization -- Generation of Efficient Embedded Applications -- Performance/Energy Optimization of DSP Transforms on the XScale Processor -- Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms -- A Throughput-Driven Task Creation and Mapping for Network Processors -- Optimizations and Architectural Tradeoffs for Embedded Systems -- MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization -- Evaluation of Offset Assignment Heuristics -- Customizing the Datapath and ISA of Soft VLIW Processors -- Instruction Set Extension Generation with Considering Physical Constraints. |
| Record Nr. | UNISA-996466023003316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
High Performance Embedded Architectures and Compilers [[electronic resource] ] : Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings / / edited by Koen De Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer
| High Performance Embedded Architectures and Compilers [[electronic resource] ] : Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings / / edited by Koen De Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer |
| Edizione | [1st ed. 2007.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 |
| Descrizione fisica | 1 online resource (297 p.) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Computer arithmetic and logic units Microprocessors Computer architecture Computer input-output equipment Logic design Computer networks Theory of Computation Arithmetic and Logic Structures Processor Architectures Input/Output and Data Communications Logic Design Computer Communication Networks |
| ISBN | 3-540-69338-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Program -- Keynote: Insight, Not (Random) Numbers: An Embedded Perspective -- I Secure and Low-Power Embedded Memory Systems -- Compiler-Assisted Memory Encryption for Embedded Processors -- Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems -- Applying Decay to Reduce Dynamic Power in Set-Associative Caches -- II Architecture/Compiler Optimizations for Efficient Embedded Processing -- Virtual Registers: Reducing Register Pressure Without Enlarging the Register File -- Bounds Checking with Taint-Based Analysis -- Reducing Exit Stub Memory Consumption in Code Caches -- III Adaptive Microarchitectures -- Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling -- Fetch Gating Control Through Speculative Instruction Window Weighting -- Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches -- Branch History Matching: Branch Predictor Warmup for Sampled Simulation -- Sunflower : Full-System, Embedded Microarchitecture Evaluation -- Efficient Program Power Behavior Characterization -- Generation of Efficient Embedded Applications -- Performance/Energy Optimization of DSP Transforms on the XScale Processor -- Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms -- A Throughput-Driven Task Creation and Mapping for Network Processors -- Optimizations and Architectural Tradeoffs for Embedded Systems -- MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization -- Evaluation of Offset Assignment Heuristics -- Customizing the Datapath and ISA of Soft VLIW Processors -- Instruction Set Extension Generation with Considering Physical Constraints. |
| Record Nr. | UNINA-9910484914503321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||