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ASPLOS XXI : Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems : April 2-6, 2016, Atlanta, Georgia, USA / / Tom Conte, Yuanyuan Zhou, editors
| ASPLOS XXI : Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems : April 2-6, 2016, Atlanta, Georgia, USA / / Tom Conte, Yuanyuan Zhou, editors |
| Pubbl/distr/stampa | New York, NY : , : Association for Computing Machinery, , 2016 |
| Descrizione fisica | 1 online resource (806 pages) : illustrations |
| Disciplina | 621.381952 |
| Collana | ACM international conference proceedings series |
| Soggetto topico |
Computer architecture
Operating systems (Computers) |
| ISBN | 1-4503-4091-1 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910376539003321 |
| New York, NY : , : Association for Computing Machinery, , 2016 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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High Performance Embedded Architectures and Compilers [[electronic resource] ] : First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings / / edited by Tom Conte, Nacho Navarro, Wen-mei W. Hwu, Mateo Valero, Theo Ungerer
| High Performance Embedded Architectures and Compilers [[electronic resource] ] : First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings / / edited by Tom Conte, Nacho Navarro, Wen-mei W. Hwu, Mateo Valero, Theo Ungerer |
| Edizione | [1st ed. 2005.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2005 |
| Descrizione fisica | 1 online resource (XIV, 318 p.) |
| Disciplina | 004 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer arithmetic and logic units
Computer systems Compilers (Computer programs) Computer input-output equipment Logic design Microprocessors Computer architecture Arithmetic and Logic Structures Computer System Implementation Compilers and Interpreters Input/Output and Data Communications Logic Design Processor Architectures |
| Classificazione | 54.31 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Program -- Keynote 1: Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications -- Keynote 2: The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges -- Software Defined Radio – A High Performance Embedded Challenge -- I Analysis and Evaluation Techniques -- A Practical Method for Quickly Evaluating Program Optimizations -- Efficient Sampling Startup for Sampled Processor Simulation -- Enhancing Network Processor Simulation Speed with Statistical Input Sampling -- II Novel Memory and Interconnect Architectures -- Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems -- Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation -- Streaming Sparse Matrix Compression/Decompression -- XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs -- III Security Architecture -- Memory-Centric Security Architecture -- A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management -- Arc3D: A 3D Obfuscation Architecture -- IV Novel Compiler and Runtime Techniques -- Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations -- Induction Variable Analysis with Delayed Abstractions -- Garbage Collection Hints -- V DomainSpecificArchitectures -- Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors -- Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture -- A Single (Unified) Shader GPU Microarchitecture for Embedded Systems -- A Low-Power DSP-Enhanced 32-Bit EISC Processor. |
| Record Nr. | UNISA-996465731103316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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High performance embedded architectures and compilers : first international conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005 : proceedings / / Tom Conte ... [et al.] (eds.)
| High performance embedded architectures and compilers : first international conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005 : proceedings / / Tom Conte ... [et al.] (eds.) |
| Edizione | [1st ed. 2005.] |
| Pubbl/distr/stampa | Berlin, : Springer, 2005 |
| Descrizione fisica | 1 online resource (XIV, 318 p.) |
| Disciplina | 004 |
| Altri autori (Persone) | ConteTom |
| Collana | Lecture notes in computer science |
| Soggetto topico |
Embedded computer systems
High performance computing Compilers (Computer programs) Computer architecture |
| Classificazione | 54.31 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Program -- Keynote 1: Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications -- Keynote 2: The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges -- Software Defined Radio – A High Performance Embedded Challenge -- I Analysis and Evaluation Techniques -- A Practical Method for Quickly Evaluating Program Optimizations -- Efficient Sampling Startup for Sampled Processor Simulation -- Enhancing Network Processor Simulation Speed with Statistical Input Sampling -- II Novel Memory and Interconnect Architectures -- Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems -- Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation -- Streaming Sparse Matrix Compression/Decompression -- XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs -- III Security Architecture -- Memory-Centric Security Architecture -- A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management -- Arc3D: A 3D Obfuscation Architecture -- IV Novel Compiler and Runtime Techniques -- Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations -- Induction Variable Analysis with Delayed Abstractions -- Garbage Collection Hints -- V DomainSpecificArchitectures -- Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors -- Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture -- A Single (Unified) Shader GPU Microarchitecture for Embedded Systems -- A Low-Power DSP-Enhanced 32-Bit EISC Processor. |
| Altri titoli varianti | HiPEAC 2005 |
| Record Nr. | UNINA-9910484308803321 |
| Berlin, : Springer, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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