Constraining designs for synthesis and timing analysis : a practical guide to synopsys design constraints (SDC) / / Sridhar Gangadharan, Sanjay Churiwala |
Autore | Gangadharan Sridhar |
Edizione | [1st ed. 2013.] |
Pubbl/distr/stampa | New York, : Springer, c2013 |
Descrizione fisica | 1 online resource (245 p.) |
Disciplina |
004.1
620 621.381 621.3815 |
Altri autori (Persone) | ChuriwalaSanjay |
Soggetto topico |
Timing circuits
Time measurements |
ISBN | 1-4614-3269-3 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | Introduction -- Synthesis Basics -- Timing Analysis and Constraints -- SDC Extensions through Tcl -- Clocks -- Generated Clocks -- Clock Groups -- Other Clock Characteristics -- Port Delays -- Completing Port Constraints -- False Paths -- Multi Cycle Paths -- Combinatorial Paths -- Modal Analysis -- Managing Your Constraints -- Miscellaneous SDC Commands -- XDC: Xilinx Extensions To SDC. |
Record Nr. | UNINA-9910438056903321 |
Gangadharan Sridhar | ||
New York, : Springer, c2013 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
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Designing with Xilinx® FPGAs : Using Vivado / / edited by Sanjay Churiwala |
Edizione | [1st ed. 2017.] |
Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2017 |
Descrizione fisica | 1 online resource (X, 260 p. 141 illus., 3 illus. in color.) |
Disciplina | 621.3815 |
Soggetto topico |
Electronic circuits
Microprocessors Electronics Microelectronics Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation |
ISBN | 3-319-42438-6 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | State of the Art Programmable Logic -- Vivado Design Tools -- IP Flows -- Gigabit Transceivers -- Memory Controllers -- Processor Options -- Vivado IP Integrator -- SysGen for DSP -- Synthesis -- C Based Design -- Simulation -- Clocking -- Stacked Silicon Interconnect -- Timing Closure -- Power Analysis and Optimization -- System Monitor -- Hardware Debug -- Emulation Using FPGAs -- Partial Reconfiguration & Hierarchical Design. |
Record Nr. | UNINA-9910136015103321 |
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2017 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
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An Introduction to Machine Learning / / by Gopinath Rebala, Ajay Ravi, Sanjay Churiwala |
Autore | Rebala Gopinath |
Edizione | [1st ed. 2019.] |
Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
Descrizione fisica | 1 online resource (275 pages) |
Disciplina | 006.31 |
Soggetto topico |
Electronic circuits
Artificial intelligence Computational intelligence Circuits and Systems Artificial Intelligence Computational Intelligence |
ISBN | 3-030-15729-6 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | Introduction -- Basics before Machine Learning -- Learning Models -- Regression -- Improving Further -- Classification -- Clustering (unsupervised Learning) -- Random Forests -- Testing the Algorithm and the Network -- Neural Network -- Reinforcement Learning -- Deep Learning -- Principal Component Analysis -- Anomaly Detection -- Recommender System -- Feature Search/Convolution -- Natural Language Processing -- Language Translation -- AlphaGo -- Data Quality -- System Improvement -- Software stack -- Hardware Implementations. . |
Record Nr. | UNINA-9910337625903321 |
Rebala Gopinath | ||
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
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