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Embedded SoPC design with NIOS II processor and Verilog examples [[electronic resource] /] / Pong P. Chu
| Embedded SoPC design with NIOS II processor and Verilog examples [[electronic resource] /] / Pong P. Chu |
| Autore | Chu Pong P. <1959-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley, c2012 |
| Descrizione fisica | 1 online resource (783 p.) |
| Disciplina | 006.2/2 |
| Soggetto topico |
Embedded computer systems
Field programmable gate arrays Verilog (Computer hardware description language) |
| ISBN |
1-280-59239-7
9786613622228 1-118-30957-X 1-118-30972-3 1-118-30946-4 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | pt. I. Basic digital circuits development -- pt. II. Basic NIOS II software development -- pt. III. Custom I/O peripheral development -- pt. IV. Hardware accelerator case studies. |
| Record Nr. | UNINA-9910139089603321 |
Chu Pong P. <1959->
|
||
| Hoboken, N.J., : Wiley, c2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Embedded SoPC design with NIOS II processor and Verilog examples / / Pong P. Chu
| Embedded SoPC design with NIOS II processor and Verilog examples / / Pong P. Chu |
| Autore | Chu Pong P. <1959-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley, c2012 |
| Descrizione fisica | 1 online resource (783 p.) |
| Disciplina | 006.2/2 |
| Soggetto topico |
Embedded computer systems
Field programmable gate arrays Verilog (Computer hardware description language) |
| ISBN |
9786613622228
9781280592393 1280592397 9781118309575 111830957X 9781118309728 1118309723 9781118309469 1118309464 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | pt. I. Basic digital circuits development -- pt. II. Basic NIOS II software development -- pt. III. Custom I/O peripheral development -- pt. IV. Hardware accelerator case studies. |
| Altri titoli varianti | Embedded system on a programmable chip design with Nios II processor and Verilog examples |
| Record Nr. | UNINA-9910822030103321 |
|
Chu Pong P. <1959->
|
||
| Hoboken, N.J., : Wiley, c2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Embedded SOPC design with NIOS II processor and VHDL examples [[electronic resource] /] / Pong P. Chu
| Embedded SOPC design with NIOS II processor and VHDL examples [[electronic resource] /] / Pong P. Chu |
| Autore | Chu Pong P. <1959-> |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley, c2011 |
| Descrizione fisica | 1 online resource (738 p.) |
| Disciplina |
621.392
621.395 |
| Soggetto topico |
Systems on a chip
Field programmable gate arrays Computer input-output equipment - Design and construction VHDL (Computer hardware description language) |
| ISBN |
1-283-28288-7
9786613282880 1-118-14653-0 1-118-14652-2 1-118-14650-6 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Embedded SOPC Design with Nios II Processor and VHDL Examples; CONTENTS; Preface; Acknowledgments; 1 Overview of Embedded System; 1.1 Introduction; 1.1.1 Definition of an embedded system; 1.1.2 Example systems; 1.2 System design requirements; 1.3 Embedded SoPC systems; 1.3.1 Basic development flow; 1.4 Book organization; 1.5 Bibliographic notes; PART I BASIC DIGITAL CIRCUITS DEVELOPMENT; 2 Gate-level Combinational Circuit; 2.1 Overview of VHDL; 2.2 General description; 2.2.1 Basic lexical rules; 2.2.2 Library and package; 2.2.3 Entity declaration; 2.2.4 Data type and operators
2.2.5 Architecture body2.2.6 Code of a 2-bit comparator; 2.3 Structural description; 2.4 Testbench; 2.5 Bibliographic notes; 2.6 Suggested experiments; 2.6.1 Code for gate-level greater-than circuit; 2.6.2 Code for gate-level binary decoder; 3 Overview of FPGA and EDA Software; 3.1 FPGA; 3.1.1 Overview of a general FPGA device; 3.1.2 Overview of the Altera Cyclone II devices; 3.2 Overview of the Altera DE1 and DE2 boards; 3.3 Development flow; 3.4 Overview of Quartus II; 3.5 Short tutorial of Quartus II; 3.5.1 Create the design project; 3.5.2 Create a testbench and perform the RTL simulation 3.5.3 Compile the project3.5.4 Perform timing analysis; 3.5.5 Program the FPGA device; 3.6 Short tutorial on the ModelSim HDL simulator; 3.7 Bibliographic notes; 3.8 Suggested experiments; 3.8.1 Gate-level greater-than circuit; 3.8.2 Gate-level binary decoder; 4 RT-level Combinational Circuit; 4.1 RT-level components; 4.1.1 Relational operators; 4.1.2 Arithmetic operators; 4.1.3 Other synthesis-related VHDL constructs; 4.1.4 Summary; 4.2 Routing circuit with concurrent assignment statements; 4.2.1 Conditional signal assignment statement; 4.2.2 Selected signal assignment statement 4.3 Modeling with a process4.3.1 Process; 4.3.2 Sequential signal assignment statement; 4.4 Routing circuit with if and case statements; 4.4.1 If statement; 4.4.2 Case statement; 4.4.3 Comparison to concurrent statements; 4.4.4 Unintended memory; 4.5 Constants and generics; 4.5.1 Constants; 4.5.2 Generics; 4.6 Design examples; 4.6.1 Hexadecimal digit to seven-segment LED decoder; 4.6.2 Sign-magnitude adder; 4.6.3 Barrel shifter; 4.6.4 Simplified floating-point adder; 4.7 Bibliographic notes; 4.8 Suggested experiments; 4.8.1 Multi-function barrel shifter; 4.8.2 Dual-priority encoder 4.8.3 BCD incrementor4.8.4 Floating-point greater-than circuit; 4.8.5 Floating-point and signed integer conversion circuit; 4.8.6 Enhanced floating-point adder; 5 Regular Sequential Circuit; 5.1 Introduction; 5.1.1 D FF and register; 5.1.2 Synchronous system; 5.1.3 Code development; 5.2 HDL code of the basic storage elements; 5.2.1 D FF; 5.2.2 Register; 5.2.3 Register file; 5.2.4 SRAM; 5.3 Simple design examples; 5.3.1 Shift register; 5.3.2 Binary counter and variant; 5.4 Testbench for sequential circuits; 5.5 Timing analysis; 5.5.1 Timing parameters; 5.5.2 Timing considerations in Quartus II 5.6 Case study |
| Record Nr. | UNINA-9910141240503321 |
|
Chu Pong P. <1959->
|
||
| Hoboken, N.J., : Wiley, c2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Embedded SOPC design with NIOS II processor and VHDL examples / / Pong P. Chu
| Embedded SOPC design with NIOS II processor and VHDL examples / / Pong P. Chu |
| Autore | Chu Pong P. <1959-> |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley, c2011 |
| Descrizione fisica | 1 online resource (738 p.) |
| Disciplina |
621.392
621.395 |
| Soggetto topico |
Systems on a chip
Field programmable gate arrays Computer input-output equipment - Design and construction VHDL (Computer hardware description language) |
| ISBN |
1-283-28288-7
9786613282880 1-118-14653-0 1-118-14652-2 1-118-14650-6 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Embedded SOPC Design with Nios II Processor and VHDL Examples; CONTENTS; Preface; Acknowledgments; 1 Overview of Embedded System; 1.1 Introduction; 1.1.1 Definition of an embedded system; 1.1.2 Example systems; 1.2 System design requirements; 1.3 Embedded SoPC systems; 1.3.1 Basic development flow; 1.4 Book organization; 1.5 Bibliographic notes; PART I BASIC DIGITAL CIRCUITS DEVELOPMENT; 2 Gate-level Combinational Circuit; 2.1 Overview of VHDL; 2.2 General description; 2.2.1 Basic lexical rules; 2.2.2 Library and package; 2.2.3 Entity declaration; 2.2.4 Data type and operators
2.2.5 Architecture body2.2.6 Code of a 2-bit comparator; 2.3 Structural description; 2.4 Testbench; 2.5 Bibliographic notes; 2.6 Suggested experiments; 2.6.1 Code for gate-level greater-than circuit; 2.6.2 Code for gate-level binary decoder; 3 Overview of FPGA and EDA Software; 3.1 FPGA; 3.1.1 Overview of a general FPGA device; 3.1.2 Overview of the Altera Cyclone II devices; 3.2 Overview of the Altera DE1 and DE2 boards; 3.3 Development flow; 3.4 Overview of Quartus II; 3.5 Short tutorial of Quartus II; 3.5.1 Create the design project; 3.5.2 Create a testbench and perform the RTL simulation 3.5.3 Compile the project3.5.4 Perform timing analysis; 3.5.5 Program the FPGA device; 3.6 Short tutorial on the ModelSim HDL simulator; 3.7 Bibliographic notes; 3.8 Suggested experiments; 3.8.1 Gate-level greater-than circuit; 3.8.2 Gate-level binary decoder; 4 RT-level Combinational Circuit; 4.1 RT-level components; 4.1.1 Relational operators; 4.1.2 Arithmetic operators; 4.1.3 Other synthesis-related VHDL constructs; 4.1.4 Summary; 4.2 Routing circuit with concurrent assignment statements; 4.2.1 Conditional signal assignment statement; 4.2.2 Selected signal assignment statement 4.3 Modeling with a process4.3.1 Process; 4.3.2 Sequential signal assignment statement; 4.4 Routing circuit with if and case statements; 4.4.1 If statement; 4.4.2 Case statement; 4.4.3 Comparison to concurrent statements; 4.4.4 Unintended memory; 4.5 Constants and generics; 4.5.1 Constants; 4.5.2 Generics; 4.6 Design examples; 4.6.1 Hexadecimal digit to seven-segment LED decoder; 4.6.2 Sign-magnitude adder; 4.6.3 Barrel shifter; 4.6.4 Simplified floating-point adder; 4.7 Bibliographic notes; 4.8 Suggested experiments; 4.8.1 Multi-function barrel shifter; 4.8.2 Dual-priority encoder 4.8.3 BCD incrementor4.8.4 Floating-point greater-than circuit; 4.8.5 Floating-point and signed integer conversion circuit; 4.8.6 Enhanced floating-point adder; 5 Regular Sequential Circuit; 5.1 Introduction; 5.1.1 D FF and register; 5.1.2 Synchronous system; 5.1.3 Code development; 5.2 HDL code of the basic storage elements; 5.2.1 D FF; 5.2.2 Register; 5.2.3 Register file; 5.2.4 SRAM; 5.3 Simple design examples; 5.3.1 Shift register; 5.3.2 Binary counter and variant; 5.4 Testbench for sequential circuits; 5.5 Timing analysis; 5.5.1 Timing parameters; 5.5.2 Timing considerations in Quartus II 5.6 Case study |
| Record Nr. | UNINA-9910808346303321 |
|
Chu Pong P. <1959->
|
||
| Hoboken, N.J., : Wiley, c2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
FPGA prototyping by Verilog examples [[electronic resource] ] : Xilinx Spartan -3 version / / Pong P. Chu
| FPGA prototyping by Verilog examples [[electronic resource] ] : Xilinx Spartan -3 version / / Pong P. Chu |
| Autore | Chu Pong P. <1959-> |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Hoboken, N.J., : J. Wiley & Sons, c2008 |
| Descrizione fisica | 1 online resource (520 p.) |
| Disciplina | 621.39/5 |
| Soggetto topico |
Field programmable gate arrays - Design and construction
Prototypes, Engineering Verilog (Computer hardware description language) |
| ISBN |
1-118-21061-1
1-281-73257-5 9786611732578 0-470-37428-4 0-470-37427-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
FPGA Prototyping by Verilog Examples; CONTENTS; Preface; Acknowledgments; PART I BASIC DIGITAL CIRCUITS; 1 Gate-level combinational circuit; 1.4 Data types; 1.5 Program skeleton; 1.6 Structural description; 1.7 Testbench; 1.8 Bibliographic notes; 1.9 Suggested experiments; 2 Overview of FPGA and EDA software; 3 RT-level combinationaI circuit; 4 Regular Sequential Circuit; 5 FSM; 6 FSMD; 7 Selected Topics of Verilog; PART II I/O MODULES; 8 UART; 9 PS2 Keyboard; 10 PS2 Mouse; 11 External SRAM; 12 Xilinx Spartan 3 Specific Memory; 13 VGA controller I: graphic; 14 VGA controller II: text
PART III PICOBLAZE MICROCONTROLLER XILINX SPECIFIC15 PicoBlaze Overview; 16 PicoBlaze Assembly Code Development; 17 PicoBlaze I/O Interface; 18 PicoBlaze Interrupt Interface; Appendix A: Sample Verilog templates; A.1 Numbers and operators; A.2 General Verilog constructs; A.3 Routing with conditional operator and if and case statements; A.4 Combinational circuit using an always block; A.5 Memory Components; A.6 Regular sequential circuits; A.7 FSM; A.8 FSMD; A.9 S3 board constraint file (s3. ucf); References; Topic Index |
| Record Nr. | UNINA-9910144137503321 |
|
Chu Pong P. <1959->
|
||
| Hoboken, N.J., : J. Wiley & Sons, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
FPGA prototyping by Verilog examples : Xilinx Spartan -3 version / / Pong P. Chu
| FPGA prototyping by Verilog examples : Xilinx Spartan -3 version / / Pong P. Chu |
| Autore | Chu Pong P. <1959-> |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Hoboken, N.J., : J. Wiley & Sons, c2008 |
| Descrizione fisica | 1 online resource (520 p.) |
| Disciplina | 621.39/5 |
| Soggetto topico |
Field programmable gate arrays - Design and construction
Prototypes, Engineering Verilog (Computer hardware description language) |
| ISBN |
1-118-21061-1
1-281-73257-5 9786611732578 0-470-37428-4 0-470-37427-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
FPGA Prototyping by Verilog Examples; CONTENTS; Preface; Acknowledgments; PART I BASIC DIGITAL CIRCUITS; 1 Gate-level combinational circuit; 1.4 Data types; 1.5 Program skeleton; 1.6 Structural description; 1.7 Testbench; 1.8 Bibliographic notes; 1.9 Suggested experiments; 2 Overview of FPGA and EDA software; 3 RT-level combinationaI circuit; 4 Regular Sequential Circuit; 5 FSM; 6 FSMD; 7 Selected Topics of Verilog; PART II I/O MODULES; 8 UART; 9 PS2 Keyboard; 10 PS2 Mouse; 11 External SRAM; 12 Xilinx Spartan 3 Specific Memory; 13 VGA controller I: graphic; 14 VGA controller II: text
PART III PICOBLAZE MICROCONTROLLER XILINX SPECIFIC15 PicoBlaze Overview; 16 PicoBlaze Assembly Code Development; 17 PicoBlaze I/O Interface; 18 PicoBlaze Interrupt Interface; Appendix A: Sample Verilog templates; A.1 Numbers and operators; A.2 General Verilog constructs; A.3 Routing with conditional operator and if and case statements; A.4 Combinational circuit using an always block; A.5 Memory Components; A.6 Regular sequential circuits; A.7 FSM; A.8 FSMD; A.9 S3 board constraint file (s3. ucf); References; Topic Index |
| Record Nr. | UNINA-9910819122103321 |
|
Chu Pong P. <1959->
|
||
| Hoboken, N.J., : J. Wiley & Sons, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
FPGA prototyping by VHDL examples : Xilinx Spartan-3 version / / Pong P. Chu
| FPGA prototyping by VHDL examples : Xilinx Spartan-3 version / / Pong P. Chu |
| Autore | Chu Pong P. <1959-> |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley-Interscience, c2008 |
| Descrizione fisica | 1 online resource (470 p.) |
| Disciplina | 621.39/5 |
| Soggetto topico |
Field programmable gate arrays - Design and construction
Prototypes, Engineering VHDL (Computer hardware description language) |
| ISBN |
1-118-21060-3
1-281-23733-7 9786611237332 0-470-23163-7 0-470-23162-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
FPGA PROTOTYPING BY VHDL EXAMPLES: Xilinx SpartanTM-3 Version; Contents; Preface; Acknowledgments; PART I BASIC DIGITAL CIRCUITS; 1 Gate-level combinational circuit; 2 Overview of FPGA and EDA software; 3 RT-level combinational circuit; 4 Regular Sequential Circuit; 5 FSM; 6 FSMD; PART II I/O MODULES; 7 UART; 8 PS2 Keyboard; 9 PS2 Mouse; 10 External SRAM; 11 Xilinx Spartan-3 Specific Memory; 12 VGA controller I: graphic; 13 VGA controller II: text; PART III PICOBLAZE MICROCONTROLLER XILINX SPECIFIC; 14 PicoBlaze Overview; 15 PicoBlaze Assembly Code Development; 16 PicoBlaze I/O Interface
17 PicoBlaze Interrupt InterfaceAppendix A: Sample VHDL templates; References; Topic Index |
| Altri titoli varianti | Field programmable gate array prototyping by VHSIC hardware description language examples |
| Record Nr. | UNINA-9910145698903321 |
|
Chu Pong P. <1959->
|
||
| Hoboken, N.J., : Wiley-Interscience, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
RTL hardware design using VHDL : coding for efficiency, portability, and scalability / / Pong P. Chu
| RTL hardware design using VHDL : coding for efficiency, portability, and scalability / / Pong P. Chu |
| Autore | Chu Pong P. <1959-> |
| Pubbl/distr/stampa | Hoboken, New Jersey : , : Wiley-Interscience, , c2006 |
| Descrizione fisica | 1 online resource (695 p.) |
| Disciplina |
621.39/2
621.392 |
| Soggetto topico |
Digital electronics - Data processing
VHDL (Computer hardware description language) |
| ISBN |
1-280-44810-5
9786610448104 0-470-32489-9 0-471-78641-1 0-471-78639-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction to digital system design -- Overview of hardware description languages -- Basic language constructs of VHDL -- Concurrent signal assignment statements of VHDL -- Sequential statements of VHDL -- Synthesis of VHDL code -- Combinational circuit design : practice -- Sequential circuit design : principle -- Sequential circuit design : practice -- Finite state machine : principle and practice -- Register transfer methodology : principle -- Register transfer methodology : practice -- Hierarchical design in VHDL -- Parameterized design : principle -- Parameterized design : practice -- Clock and synchronization : principle and practice. |
| Record Nr. | UNINA-9910143580903321 |
|
Chu Pong P. <1959->
|
||
| Hoboken, New Jersey : , : Wiley-Interscience, , c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
RTL hardware design using VHDL : coding for efficiency, portability, and scalability / / Pong P. Chu
| RTL hardware design using VHDL : coding for efficiency, portability, and scalability / / Pong P. Chu |
| Autore | Chu Pong P. <1959-> |
| Edizione | [[First edition].] |
| Pubbl/distr/stampa | Hoboken, New Jersey : , : Wiley-Interscience, , c2006 |
| Descrizione fisica | 1 online resource (695 p.) |
| Disciplina |
621.39/2
621.392 |
| Soggetto topico |
Digital electronics - Data processing
VHDL (Computer hardware description language) |
| ISBN |
1-280-44810-5
9786610448104 0-470-32489-9 0-471-78641-1 0-471-78639-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction to digital system design -- Overview of hardware description languages -- Basic language constructs of VHDL -- Concurrent signal assignment statements of VHDL -- Sequential statements of VHDL -- Synthesis of VHDL code -- Combinational circuit design : practice -- Sequential circuit design : principle -- Sequential circuit design : practice -- Finite state machine : principle and practice -- Register transfer methodology : principle -- Register transfer methodology : practice -- Hierarchical design in VHDL -- Parameterized design : principle -- Parameterized design : practice -- Clock and synchronization : principle and practice. |
| Record Nr. | UNINA-9910829918003321 |
|
Chu Pong P. <1959->
|
||
| Hoboken, New Jersey : , : Wiley-Interscience, , c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
RTL hardware design using VHDL : coding for efficiency, portability, and scalability / / Pong P. Chu
| RTL hardware design using VHDL : coding for efficiency, portability, and scalability / / Pong P. Chu |
| Autore | Chu Pong P. <1959-> |
| Edizione | [[First edition].] |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley-Interscience, c2006 |
| Descrizione fisica | 1 online resource (695 p.) |
| Disciplina | 621.39/2 |
| Soggetto topico |
Digital electronics - Data processing
VHDL (Computer hardware description language) |
| ISBN |
9786610448104
9781280448102 1280448105 9780470324899 0470324899 9780471786412 0471786411 9780471786399 047178639X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction to digital system design -- Overview of hardware description languages -- Basic language constructs of VHDL -- Concurrent signal assignment statements of VHDL -- Sequential statements of VHDL -- Synthesis of VHDL code -- Combinational circuit design : practice -- Sequential circuit design : principle -- Sequential circuit design : practice -- Finite state machine : principle and practice -- Register transfer methodology : principle -- Register transfer methodology : practice -- Hierarchical design in VHDL -- Parameterized design : principle -- Parameterized design : practice -- Clock and synchronization : principle and practice. |
| Record Nr. | UNINA-9910876622103321 |
|
Chu Pong P. <1959->
|
||
| Hoboken, N.J., : Wiley-Interscience, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||