Info
- Utilizzare la checkbox di selezione a fianco di ciascun documento per attivare le funzionalità di stampa, invio email, download nei formati disponibili del (i) record.
Signal integrity and radiated emission of high-speed digital systems [[electronic resource] /] / Spartaco Caniggia, Francescaromana Maradei
| Signal integrity and radiated emission of high-speed digital systems [[electronic resource] /] / Spartaco Caniggia, Francescaromana Maradei |
| Autore | Caniggia Spartaco |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Chichester, U.K., : Wiley, 2008 |
| Descrizione fisica | 1 online resource (554 p.) |
| Disciplina | 621.382/24 |
| Altri autori (Persone) | MaradeiFrancescaromana |
| Soggetto topico |
Electromagnetic interference
Digital electronics Very high speed integrated circuits Crosstalk Signal processing |
| ISBN |
1-282-01071-9
9786612010712 0-470-77287-5 0-470-77288-3 |
| Classificazione | 05.42 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
SIGNAL INTEGRITY ANDRADIATED EMISSIONOF HIGH-SPEED DIGITAL SYSTEMS; Contents; List of Examples; Foreword; Preface; 1 Introduction to Signal Integrity and Radiated Emission in a Digital System; 1.1 Power and Signal Integrity; 1.1.1 Power Distribution Network; 1.1.2 Signal Distribution Network; 1.1.3 Noise Limitations and Design for Characteristic Impedance; 1.2 Radiated Emission; 1.2.1 Definition of Radiated Emission Sources; 1.2.2 Radiated Emission Standards; 1.2.3 Radiated Emission from a Real System; 1.3 Signaling and Logic Devices; 1.3.1 Overshoot, Undershoot and Plateau
1.3.2 Noise Immunity1.3.3 Timing Parameters; 1.3.4 Eye Diagram; 1.4 Modeling Digital Systems; 1.4.1 Mathematical Tools; 1.4.2 Spice-Like Circuit Simulators; 1.4.3 Full-Wave Numerical Tools; 1.4.4 Professional Simulators; References; 2 High-Speed Digital Devices; 2.1 Input/Output Static Characteristic; 2.1.1 Current and Voltage Specifications; 2.1.2 Transistor-Transistor Logic (TTL) Devices; 2.1.3 Complementary Metal Oxide Semiconductor (CMOS) Devices; 2.1.4 Emitter-Coupled Logic (ECL) Devices; 2.1.5 Low-Voltage Differential Signal (LVDS) Devices 2.1.6 Logic Devices Powered and the Logic Level2.2 Dynamic Characteristics: Gate Delay and Rise and Fall Times; 2.3 Driver and Receiver Modeling; 2.3.1 Types of Driver Model; 2.3.2 Driver Switching Currents Path; 2.3.3 Driver Non-Linear Behavioral Model; 2.3.4 Receiver Non-Linear Behavioral Modeling; 2.4 I/O Buffer Information Specification (IBIS) Models; 2.4.1 Structure of an IBIS Model; 2.4.2 IBIS Models and Spice; References; 3 Inductance; 3.1 Loop Inductance; 3.1.1 Inductances of Coupled Loops; 3.1.2 Inductances of Thin Filamentary Circuits; 3.1.3 Equivalent Circuit of Two Coupled Loops 3.1.4 L Matrix of Two Coupled Conductors Having a Reference Return Conductor3.1.5 L Calculation of a Three-Conductor Wire-Type Line; 3.1.6 Frequency-Dependent Internal Inductance; 3.2 Partial Inductance; 3.2.1 Partial Inductances of Coupled Loops; 3.2.2 Flux Area of Partial Inductance of Thin Filamentary Segments; 3.2.3 Loop Inductance Decomposed into Partial Inductances; 3.2.4 Self and Mutual Partial Inductance; 3.2.5 Inductance Between Two Parallel Conductors; 3.2.6 Loop Inductance Matrix Calculation by Partial Inductances; 3.2.7 Partial Inductance Associated with a Finite Ground Plane 3.2.8 Solving Inductance Problems in PCBs3.3 Differential Mode and Common Mode Inductance; 3.3.1 Differential Mode Inductance; 3.3.2 Common Mode Inductance; References; 4 Capacitance; 4.1 Capacitance Between Conductors; 4.1.1 Definition of Capacitance; 4.1.2 Partial Capacitance and Capacitance Matrix of Two Coupled Conductors Having a Reference Return Conductor; 4.1.3 Capacitance Matrix of n Coupled Conductors Having a Reference Return Conductor; 4.2 Differential Mode and Common Mode Capacitance; 4.2.1 Differential Mode Capacitance; 4.2.2 Common Mode Capacitance; References 5 Reflection on Signal Lines |
| Record Nr. | UNINA-9910144378903321 |
Caniggia Spartaco
|
||
| Chichester, U.K., : Wiley, 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Signal integrity and radiated emission of high-speed digital systems / / Spartaco Caniggia, Francescaromana Maradei
| Signal integrity and radiated emission of high-speed digital systems / / Spartaco Caniggia, Francescaromana Maradei |
| Autore | Caniggia Spartaco |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Chichester, U.K., : Wiley, 2008 |
| Descrizione fisica | 1 online resource (554 p.) |
| Disciplina | 621.382/24 |
| Altri autori (Persone) | MaradeiFrancescaromana |
| Soggetto topico |
Electromagnetic interference
Digital electronics Very high speed integrated circuits Crosstalk Signal processing |
| ISBN |
9786612010712
9781282010710 1282010719 9780470772874 0470772875 9780470772881 0470772883 |
| Classificazione | 05.42 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
SIGNAL INTEGRITY ANDRADIATED EMISSIONOF HIGH-SPEED DIGITAL SYSTEMS; Contents; List of Examples; Foreword; Preface; 1 Introduction to Signal Integrity and Radiated Emission in a Digital System; 1.1 Power and Signal Integrity; 1.1.1 Power Distribution Network; 1.1.2 Signal Distribution Network; 1.1.3 Noise Limitations and Design for Characteristic Impedance; 1.2 Radiated Emission; 1.2.1 Definition of Radiated Emission Sources; 1.2.2 Radiated Emission Standards; 1.2.3 Radiated Emission from a Real System; 1.3 Signaling and Logic Devices; 1.3.1 Overshoot, Undershoot and Plateau
1.3.2 Noise Immunity1.3.3 Timing Parameters; 1.3.4 Eye Diagram; 1.4 Modeling Digital Systems; 1.4.1 Mathematical Tools; 1.4.2 Spice-Like Circuit Simulators; 1.4.3 Full-Wave Numerical Tools; 1.4.4 Professional Simulators; References; 2 High-Speed Digital Devices; 2.1 Input/Output Static Characteristic; 2.1.1 Current and Voltage Specifications; 2.1.2 Transistor-Transistor Logic (TTL) Devices; 2.1.3 Complementary Metal Oxide Semiconductor (CMOS) Devices; 2.1.4 Emitter-Coupled Logic (ECL) Devices; 2.1.5 Low-Voltage Differential Signal (LVDS) Devices 2.1.6 Logic Devices Powered and the Logic Level2.2 Dynamic Characteristics: Gate Delay and Rise and Fall Times; 2.3 Driver and Receiver Modeling; 2.3.1 Types of Driver Model; 2.3.2 Driver Switching Currents Path; 2.3.3 Driver Non-Linear Behavioral Model; 2.3.4 Receiver Non-Linear Behavioral Modeling; 2.4 I/O Buffer Information Specification (IBIS) Models; 2.4.1 Structure of an IBIS Model; 2.4.2 IBIS Models and Spice; References; 3 Inductance; 3.1 Loop Inductance; 3.1.1 Inductances of Coupled Loops; 3.1.2 Inductances of Thin Filamentary Circuits; 3.1.3 Equivalent Circuit of Two Coupled Loops 3.1.4 L Matrix of Two Coupled Conductors Having a Reference Return Conductor3.1.5 L Calculation of a Three-Conductor Wire-Type Line; 3.1.6 Frequency-Dependent Internal Inductance; 3.2 Partial Inductance; 3.2.1 Partial Inductances of Coupled Loops; 3.2.2 Flux Area of Partial Inductance of Thin Filamentary Segments; 3.2.3 Loop Inductance Decomposed into Partial Inductances; 3.2.4 Self and Mutual Partial Inductance; 3.2.5 Inductance Between Two Parallel Conductors; 3.2.6 Loop Inductance Matrix Calculation by Partial Inductances; 3.2.7 Partial Inductance Associated with a Finite Ground Plane 3.2.8 Solving Inductance Problems in PCBs3.3 Differential Mode and Common Mode Inductance; 3.3.1 Differential Mode Inductance; 3.3.2 Common Mode Inductance; References; 4 Capacitance; 4.1 Capacitance Between Conductors; 4.1.1 Definition of Capacitance; 4.1.2 Partial Capacitance and Capacitance Matrix of Two Coupled Conductors Having a Reference Return Conductor; 4.1.3 Capacitance Matrix of n Coupled Conductors Having a Reference Return Conductor; 4.2 Differential Mode and Common Mode Capacitance; 4.2.1 Differential Mode Capacitance; 4.2.2 Common Mode Capacitance; References 5 Reflection on Signal Lines |
| Record Nr. | UNINA-9910822567603321 |
|
Caniggia Spartaco
|
||
| Chichester, U.K., : Wiley, 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||