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Architecture of Computing Systems – ARCS 2020 [[electronic resource] ] : 33rd International Conference, Aachen, Germany, May 25–28, 2020, Proceedings / / edited by André Brinkmann, Wolfgang Karl, Stefan Lankes, Sven Tomforde, Thilo Pionteck, Carsten Trinitis
| Architecture of Computing Systems – ARCS 2020 [[electronic resource] ] : 33rd International Conference, Aachen, Germany, May 25–28, 2020, Proceedings / / edited by André Brinkmann, Wolfgang Karl, Stefan Lankes, Sven Tomforde, Thilo Pionteck, Carsten Trinitis |
| Edizione | [1st ed. 2020.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 |
| Descrizione fisica | 1 online resource (XII, 257 p. 112 illus., 62 illus. in color.) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer networks
Computer systems Microprocessors Computer architecture Computer input-output equipment Computer Communication Networks Computer System Implementation Processor Architectures Input/Output and Data Communications |
| ISBN | 3-030-52794-8 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Main Conference -- Approximate Data Dependence Pro ling based on Abstract Interval and Congruent Domains -- Evaluating Dynamic Task Scheduling with Priorities and Adaptive Aging in a Task-based Runtime System -- An Architecture for Solving the Eigenvalue Problem on Embedded FPGAs -- ECC Memory for Fault Tolerant RISC-V Processors -- 3D Optimisation of Software Application Mappings on Heterogeneous MPSoCs -- Towards a Priority-Based Task Distribution Strategy for an Artificial Hormone System -- He..ro DB: A Concept for Parallel Data Processing on Heterogeneous Hardware -- Investigating Transactional Memory for High Performance Embedded Systems -- X-CEL: A Method to Estimate Near-Memory Acceleration Potential in Tile-based MPSoCs -- Engineering an Optimized Instruction Set Architecture for AMIDAR Processors -- Scaling Logic Locking Schemes to Multi-Module Hardware Designs -- Exploration of Power Domain Partitioning with Concurrent Task Mapping and Scheduling for Application-specific Multi-core SoCs -- FORMUS3IC Workshop -- Scalable, Decentralized Battery Management System Based on Self-Organizing Nodes -- Security Improvements by Separating the Cryptographic Protocol from the Network Stack onto a Multi-MCU Architecture -- Equally Distributed Bus-Communication Access Rights for Inter MCU Communication using Multimaster SPI -- Workshop on Computer Architectures in Space (CompSpace) -- On the Evaluation of SEU Effects on AXI Interconnect within AP-SoCs -- Satellite Onboard Data Reduction using a Risc-V core inside an RTG4-based Data Processing Pipeline -- Workshop on Parallel Systems and Algorithms (PASA) -- Accelerating Real-Time Applications with Predictable Work-Stealing. |
| Record Nr. | UNISA-996418307303316 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Architecture of Computing Systems – ARCS 2020 : 33rd International Conference, Aachen, Germany, May 25–28, 2020, Proceedings / / edited by André Brinkmann, Wolfgang Karl, Stefan Lankes, Sven Tomforde, Thilo Pionteck, Carsten Trinitis
| Architecture of Computing Systems – ARCS 2020 : 33rd International Conference, Aachen, Germany, May 25–28, 2020, Proceedings / / edited by André Brinkmann, Wolfgang Karl, Stefan Lankes, Sven Tomforde, Thilo Pionteck, Carsten Trinitis |
| Edizione | [1st ed. 2020.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 |
| Descrizione fisica | 1 online resource (XII, 257 p. 112 illus., 62 illus. in color.) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer networks
Computer systems Microprocessors Computer architecture Computer input-output equipment Computer Communication Networks Computer System Implementation Processor Architectures Input/Output and Data Communications |
| ISBN | 3-030-52794-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Main Conference -- Approximate Data Dependence Pro ling based on Abstract Interval and Congruent Domains -- Evaluating Dynamic Task Scheduling with Priorities and Adaptive Aging in a Task-based Runtime System -- An Architecture for Solving the Eigenvalue Problem on Embedded FPGAs -- ECC Memory for Fault Tolerant RISC-V Processors -- 3D Optimisation of Software Application Mappings on Heterogeneous MPSoCs -- Towards a Priority-Based Task Distribution Strategy for an Artificial Hormone System -- He..ro DB: A Concept for Parallel Data Processing on Heterogeneous Hardware -- Investigating Transactional Memory for High Performance Embedded Systems -- X-CEL: A Method to Estimate Near-Memory Acceleration Potential in Tile-based MPSoCs -- Engineering an Optimized Instruction Set Architecture for AMIDAR Processors -- Scaling Logic Locking Schemes to Multi-Module Hardware Designs -- Exploration of Power Domain Partitioning with Concurrent Task Mapping and Scheduling for Application-specific Multi-core SoCs -- FORMUS3IC Workshop -- Scalable, Decentralized Battery Management System Based on Self-Organizing Nodes -- Security Improvements by Separating the Cryptographic Protocol from the Network Stack onto a Multi-MCU Architecture -- Equally Distributed Bus-Communication Access Rights for Inter MCU Communication using Multimaster SPI -- Workshop on Computer Architectures in Space (CompSpace) -- On the Evaluation of SEU Effects on AXI Interconnect within AP-SoCs -- Satellite Onboard Data Reduction using a Risc-V core inside an RTG4-based Data Processing Pipeline -- Workshop on Parallel Systems and Algorithms (PASA) -- Accelerating Real-Time Applications with Predictable Work-Stealing. |
| Record Nr. | UNINA-9910413447703321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||