Info
- Utilizzare la checkbox di selezione a fianco di ciascun documento per attivare le funzionalità di stampa, invio email, download nei formati disponibili del (i) record.
2005 IEEE international conference on field programmable technology
| 2005 IEEE international conference on field programmable technology |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 2005 |
| Descrizione fisica | 1 online resource (xxii, 344 pages) : illustrations |
| Disciplina | 025.21 |
| Soggetto topico | Field programmable gate arrays |
| ISBN | 1-5090-9949-2 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Platform-based synthesis for field-programmable SOCs," -- Low power and high speed issues in FPGA chips," -- System architectures and design patterns for reconfigurable computing," -- Reconfigurable hardware operating systems," -- A custom instruction approach for hardware and software implementations of finite field arithmetic over F/sub 2163/ using Gaussian normal bases,"M. -- High-radix systolic modular multiplication on reconfigurable hardware," -- Pipelining saturated accumulation," -- A parameterized floating-point exponential function for FPGAs," -- The Erlangen slot machine: increasing flexibility in FPGA-based reconfigurable platforms," -- Task placement for heterogeneous reconfigurable architectures," -- A framework for dynamic resource assignment and scheduling on reconfigurable mixed-mode on-chip multiprocessors," -- High quality uniform random number generation through LUT optimised linear recurrences," -- Solving the minimum dominating set problem with instance-specific hardware on FPGAs," -- Custom hardware architectures for posture analysis," -- Correlation-based fingerprint matching using FPGAs," -- A single-chip FPGA implementation of real-time adaptive background model," -- FPGA-based hardware for physical modelling sound synthesis by finite difference schemes," -- Have GPUs made FPGAs redundant in the field of video processing?," -- S5: the architecture and development flow of a software configurable processor," -- RoMultiC: fast and simple configuration data multicasting scheme for coarse grain reconfigurable devices," -- Pipeline scheduling for array based reconfigurable architectures considering interconnect delays," -- High-speed hardware architectures of the Whirlpool hash function," -- Secure partial reconfiguration of FPGAs," -- An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor," -- Dynamic voltage scaling for commercial FPGAs," -- FPGA defect tolerance: impact of granularity," -- A dynamically reconfigured UMTS multi-channel complex code matched filter," -- Prototyping automatic cloud cover assessment (ACCA) algorithm for remote sensing on-board processing on a reconfigurable computer,"E. -- Reconfigurable acceleration for Monte Carlo based financial simulation," -- Accelerating FPGA routing using architecture-adaptive A* techniques," -- Compiler-directed design space exploration for caching and prefetching data in high-level synthesis," -- Post-silicon debug using programmable logic cores," -- FPGA organization for the fast path-based neural branch predictor," -- FPGA implementation of an excitatory and inhibitory connectionist model for motion perception," -- Spatiotemporal simulation of a single living cell," -- Dynamic loading of peripherals on reconfigurable system-on-chip," -- An FPGA model for developing dynamic circuit computing," -- ADH: an aspect described hardware programming language," -- From TLM to FPGA: rapid prototyping with SystemC and transaction level modeling," -- Rapid reconfiguration of an optically differential reconfigurable gate array with pulse lasers," -- Hardware-accelerated SSH on self-reconfigurable systems," -- A fast and efficient FPGA-based implementation for solving a system of linear interval equations," -- Heuristics for context-caches in 2-level reconfigurable architectures," -- Performance of sorting algorithms on the SRC 6 reconfigurable computer," -- A zero-overhead dynamic optically reconfigurable gate array," -- The Transmogrifier-4: an FPGA-based hardware development system with multi-gigabyte memory capacity and high host and memory bandwidth," -- High performance channel model hardware emulator for 802.11n," -- HW/SW interface synthesis based on Avalon bus specification for Nios-oriented SoC design," -- A reconfigurable architecture for implementing multiple cipher algorithms," -- Low latency elliptic curve cryptography accelerators for NIST curves over binary fields," -- A system-level design methodology for reconfigurable computing applications," -- Optimal FFT architecture selection for OFDM receivers on FPGA," -- An FPGA-based infant monitoring system," -- FPGA-based conformance testing and system prototyping of an MPEG-4 SA-DCT hardware accelerator," -- FPGA core network implementation and optimization: a case study," -- A state-serial Viterbi decoder architecture for digital radio on FPGA," -- A design methodology to generate dynamically self-reconfigurable SoCs for Virtex-II Pro FPGAs," -- Implementation of Gabor-type filters on field programmable gate arrays,"O. -- A scaleable FFT/IFFT kernel for communication systems using codesign approach," -- FPGA based router for cognitive packet networks," -- An overview of high-level synthesis of multiprocessors for logic programming," -- Implementation of EAX mode of operation for FPGA bitstream encryption and authentication," -- Net power directed clustering algorithm for low net-power implementation of FPGAs," -- The design of scalable stochastic biochemical simulator on FPGA," -- Designing an FPGA SoC using a standardized IP block interface,". |
| Record Nr. | UNISA-996206261403316 |
| [Place of publication not identified], : IEEE, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
2005 IEEE international conference on field programmable technology
| 2005 IEEE international conference on field programmable technology |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 2005 |
| Descrizione fisica | 1 online resource (xxii, 344 pages) : illustrations |
| Disciplina | 025.21 |
| Soggetto topico | Field programmable gate arrays |
| ISBN |
9781509099498
1509099492 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Platform-based synthesis for field-programmable SOCs," -- Low power and high speed issues in FPGA chips," -- System architectures and design patterns for reconfigurable computing," -- Reconfigurable hardware operating systems," -- A custom instruction approach for hardware and software implementations of finite field arithmetic over F/sub 2163/ using Gaussian normal bases,"M. -- High-radix systolic modular multiplication on reconfigurable hardware," -- Pipelining saturated accumulation," -- A parameterized floating-point exponential function for FPGAs," -- The Erlangen slot machine: increasing flexibility in FPGA-based reconfigurable platforms," -- Task placement for heterogeneous reconfigurable architectures," -- A framework for dynamic resource assignment and scheduling on reconfigurable mixed-mode on-chip multiprocessors," -- High quality uniform random number generation through LUT optimised linear recurrences," -- Solving the minimum dominating set problem with instance-specific hardware on FPGAs," -- Custom hardware architectures for posture analysis," -- Correlation-based fingerprint matching using FPGAs," -- A single-chip FPGA implementation of real-time adaptive background model," -- FPGA-based hardware for physical modelling sound synthesis by finite difference schemes," -- Have GPUs made FPGAs redundant in the field of video processing?," -- S5: the architecture and development flow of a software configurable processor," -- RoMultiC: fast and simple configuration data multicasting scheme for coarse grain reconfigurable devices," -- Pipeline scheduling for array based reconfigurable architectures considering interconnect delays," -- High-speed hardware architectures of the Whirlpool hash function," -- Secure partial reconfiguration of FPGAs," -- An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor," -- Dynamic voltage scaling for commercial FPGAs," -- FPGA defect tolerance: impact of granularity," -- A dynamically reconfigured UMTS multi-channel complex code matched filter," -- Prototyping automatic cloud cover assessment (ACCA) algorithm for remote sensing on-board processing on a reconfigurable computer,"E. -- Reconfigurable acceleration for Monte Carlo based financial simulation," -- Accelerating FPGA routing using architecture-adaptive A* techniques," -- Compiler-directed design space exploration for caching and prefetching data in high-level synthesis," -- Post-silicon debug using programmable logic cores," -- FPGA organization for the fast path-based neural branch predictor," -- FPGA implementation of an excitatory and inhibitory connectionist model for motion perception," -- Spatiotemporal simulation of a single living cell," -- Dynamic loading of peripherals on reconfigurable system-on-chip," -- An FPGA model for developing dynamic circuit computing," -- ADH: an aspect described hardware programming language," -- From TLM to FPGA: rapid prototyping with SystemC and transaction level modeling," -- Rapid reconfiguration of an optically differential reconfigurable gate array with pulse lasers," -- Hardware-accelerated SSH on self-reconfigurable systems," -- A fast and efficient FPGA-based implementation for solving a system of linear interval equations," -- Heuristics for context-caches in 2-level reconfigurable architectures," -- Performance of sorting algorithms on the SRC 6 reconfigurable computer," -- A zero-overhead dynamic optically reconfigurable gate array," -- The Transmogrifier-4: an FPGA-based hardware development system with multi-gigabyte memory capacity and high host and memory bandwidth," -- High performance channel model hardware emulator for 802.11n," -- HW/SW interface synthesis based on Avalon bus specification for Nios-oriented SoC design," -- A reconfigurable architecture for implementing multiple cipher algorithms," -- Low latency elliptic curve cryptography accelerators for NIST curves over binary fields," -- A system-level design methodology for reconfigurable computing applications," -- Optimal FFT architecture selection for OFDM receivers on FPGA," -- An FPGA-based infant monitoring system," -- FPGA-based conformance testing and system prototyping of an MPEG-4 SA-DCT hardware accelerator," -- FPGA core network implementation and optimization: a case study," -- A state-serial Viterbi decoder architecture for digital radio on FPGA," -- A design methodology to generate dynamically self-reconfigurable SoCs for Virtex-II Pro FPGAs," -- Implementation of Gabor-type filters on field programmable gate arrays,"O. -- A scaleable FFT/IFFT kernel for communication systems using codesign approach," -- FPGA based router for cognitive packet networks," -- An overview of high-level synthesis of multiprocessors for logic programming," -- Implementation of EAX mode of operation for FPGA bitstream encryption and authentication," -- Net power directed clustering algorithm for low net-power implementation of FPGAs," -- The design of scalable stochastic biochemical simulator on FPGA," -- Designing an FPGA SoC using a standardized IP block interface,". |
| Record Nr. | UNINA-9910146789203321 |
| [Place of publication not identified], : IEEE, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Field-Programmable Logic and Applications [[electronic resource] ] : 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 Proceedings / / edited by Gordon Brebner, Roger Woods
| Field-Programmable Logic and Applications [[electronic resource] ] : 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 Proceedings / / edited by Gordon Brebner, Roger Woods |
| Edizione | [1st ed. 2001.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2001 |
| Descrizione fisica | 1 online resource (XV, 665 p.) |
| Disciplina | 621.39/5 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Architecture, Computer
Software engineering Computer communication systems Logic design Microprocessors Computer-aided engineering Computer System Implementation Software Engineering/Programming and Operating Systems Computer Communication Networks Logic Design Processor Architectures Computer-Aided Engineering (CAD, CAE) and Design |
| ISBN | 3-540-44687-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Keynote 1 -- Technology Trends and Adaptive Computing -- Architectural Frameworks -- Prototyping Framework for Reconfigurable Processors -- An Emulator for Exploring RaPiD Configurable Computing Architectures -- Place and Route 1 -- A New Placement Method for Direct Mapping into LUT-Based FPGAs -- fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits -- Architecture -- Macrocell Architectures for Product Term Embedded Memory Arrays -- Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs -- Memory Synthesis for FPGA-Based Reconfigurable Computers -- DSP 1 -- Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic -- Implementation of (Normalised) RLS Lattice on Virtex -- Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing -- Synthesis -- Static Profile-Driven Compilation for FPGAs -- Synthesizing RTL Hardware from Java Byte Codes -- PuMA++: From Behavioral Specification to Multi-FPGA-Prototype -- Encryption -- Secure Configuration of Field Programmable Gate Arrays -- Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm -- JBits™ Implementations of the Advanced Encryption Standard (Rijndael) -- Runtime Recon.guration 1 -- Task-Parallel Programming of Reconfigurable Systems -- Chip-Based Reconfigurable Task Management -- Configuration Caching and Swapping -- Graphics and Vision -- Multiple Stereo Matching Using an Extended Architecture -- Implementation of a NURBS to Bézier Conversor with Constant Latency -- Reconfigurable Frame-Grabber for Real-Time Automated Visual Inspection (RT-AVI) Systems -- Invited Keynote 2 -- Processing Models for the Next Generation Network -- Place and Route 2 -- Tightly Integrated Placement and Routing for FPGAs -- Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays -- Networking -- Reconfigurable Router Modules Using Network Protocol Wrappers -- Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware -- Processor Interaction -- The MOLEN ??-Coded Processor -- Run-Time Optimized Reconfiguration Using Instruction Forecasting -- CRISP: A Template for Reconfigurable Instruction Set Processors -- Applications -- Evaluation of an FPGA Implementation of the Discrete Element Method -- Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers -- A Reconfigurable Embedded Input Device for Kinetically Challenged Persons -- Methodology 1 -- Bubble Partitioning for LUT-Based Sequential Circuits -- Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits -- Placing, Routing, and Editing Virtual FPGAs -- DSP 2 -- Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver -- A Music Synthesizer on FPGA -- Motivation from a Full-Rate Specific Design to a DSP Core Approach for GSM Vocoders -- Loops and Systolic -- Loop Tiling for Reconfigurable Accelerators -- The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems -- A n-Bit Reconfigurable Scalar Quantiser -- Image Processing -- Real Time Morphological Image Contrast Enhancement in Virtex FPGA -- Demonstrating Real-time JPEG Image Compression-Decompression using Standard Component IP Cores on a Programmable Logic based Platform for DSP and Image Processing -- Design and Implementation of an Accelerated Gabor Filter Bank Using Parallel Hardware -- Invited Keynote 3 -- The Evolution of Programmable Logic: Past, Present, and Future Predictions -- Runtime Reconfiguration 2 -- Dynamically Reconfigurable Cores -- Reconfigurable Breakpoints for Co-debug -- Faults -- Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification -- FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits -- Methodology 2 -- A Generic Library for Adaptive Computing Environments -- Generative Development System for FPGA essors with Active Components -- Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines -- System Level Tools for DSP in FPGAs -- Arithmetic -- Parameterized Function Evaluation for FPGAs -- Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures -- A Digit-Serial Structure for Reconfigurable Multipliers -- FPGA Resource Reduction Through Truncated Multiplication -- Short Papers 1 -- Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures -- An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free Grammars -- Hardware-Software Partitioning: A Reconfigurable and Evolutionary Computing Approach -- An Approach to Real-Time Visualization of PIV Method with FPGA -- FPGA-Based Discrete Wavelet Transforms System -- X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor -- Arithmetic Operation Oriented Reconfigurable Chip: RHW -- Short Papers 2 -- Initial Analysis of the Proteus Architecture -- Building Asynchronous Circuits with JBits -- Case Study of Integration of Reconfigurable Logic as a Coprocessor into a SCI-Cluster under RT-Linux -- A Reconfigurable Approach to Packet Filtering -- FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding -- A Data Re-use Based Compiler Optimization for FPGAs -- Dijkstra’s Shortest Path Routing Algorithm in Reconfigurable Hardware -- A System on Chip for Power Line Communications According to European Home Systems Specifications. |
| Record Nr. | UNISA-996465912603316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2001 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Field-Programmable Logic and Applications : 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 Proceedings / / edited by Gordon Brebner, Roger Woods
| Field-Programmable Logic and Applications : 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 Proceedings / / edited by Gordon Brebner, Roger Woods |
| Edizione | [1st ed. 2001.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2001 |
| Descrizione fisica | 1 online resource (XV, 665 p.) |
| Disciplina | 621.39/5 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Computer architecture
Software engineering Computer networks Logic design Microprocessors Computer-aided engineering Computer System Implementation Software Engineering/Programming and Operating Systems Computer Communication Networks Logic Design Processor Architectures Computer-Aided Engineering (CAD, CAE) and Design |
| ISBN | 3-540-44687-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Keynote 1 -- Technology Trends and Adaptive Computing -- Architectural Frameworks -- Prototyping Framework for Reconfigurable Processors -- An Emulator for Exploring RaPiD Configurable Computing Architectures -- Place and Route 1 -- A New Placement Method for Direct Mapping into LUT-Based FPGAs -- fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits -- Architecture -- Macrocell Architectures for Product Term Embedded Memory Arrays -- Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs -- Memory Synthesis for FPGA-Based Reconfigurable Computers -- DSP 1 -- Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic -- Implementation of (Normalised) RLS Lattice on Virtex -- Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing -- Synthesis -- Static Profile-Driven Compilation for FPGAs -- Synthesizing RTL Hardware from Java Byte Codes -- PuMA++: From Behavioral Specification to Multi-FPGA-Prototype -- Encryption -- Secure Configuration of Field Programmable Gate Arrays -- Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm -- JBits™ Implementations of the Advanced Encryption Standard (Rijndael) -- Runtime Recon.guration 1 -- Task-Parallel Programming of Reconfigurable Systems -- Chip-Based Reconfigurable Task Management -- Configuration Caching and Swapping -- Graphics and Vision -- Multiple Stereo Matching Using an Extended Architecture -- Implementation of a NURBS to Bézier Conversor with Constant Latency -- Reconfigurable Frame-Grabber for Real-Time Automated Visual Inspection (RT-AVI) Systems -- Invited Keynote 2 -- Processing Models for the Next Generation Network -- Place and Route 2 -- Tightly Integrated Placement and Routing for FPGAs -- Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays -- Networking -- Reconfigurable Router Modules Using Network Protocol Wrappers -- Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware -- Processor Interaction -- The MOLEN ??-Coded Processor -- Run-Time Optimized Reconfiguration Using Instruction Forecasting -- CRISP: A Template for Reconfigurable Instruction Set Processors -- Applications -- Evaluation of an FPGA Implementation of the Discrete Element Method -- Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers -- A Reconfigurable Embedded Input Device for Kinetically Challenged Persons -- Methodology 1 -- Bubble Partitioning for LUT-Based Sequential Circuits -- Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits -- Placing, Routing, and Editing Virtual FPGAs -- DSP 2 -- Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver -- A Music Synthesizer on FPGA -- Motivation from a Full-Rate Specific Design to a DSP Core Approach for GSM Vocoders -- Loops and Systolic -- Loop Tiling for Reconfigurable Accelerators -- The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems -- A n-Bit Reconfigurable Scalar Quantiser -- Image Processing -- Real Time Morphological Image Contrast Enhancement in Virtex FPGA -- Demonstrating Real-time JPEG Image Compression-Decompression using Standard Component IP Cores on a Programmable Logic based Platform for DSP and Image Processing -- Design and Implementation of an Accelerated Gabor Filter Bank Using Parallel Hardware -- Invited Keynote 3 -- The Evolution of Programmable Logic: Past, Present, and Future Predictions -- Runtime Reconfiguration 2 -- Dynamically Reconfigurable Cores -- Reconfigurable Breakpoints for Co-debug -- Faults -- Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification -- FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits -- Methodology 2 -- A Generic Library for Adaptive Computing Environments -- Generative Development System for FPGA essors with Active Components -- Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines -- System Level Tools for DSP in FPGAs -- Arithmetic -- Parameterized Function Evaluation for FPGAs -- Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures -- A Digit-Serial Structure for Reconfigurable Multipliers -- FPGA Resource Reduction Through Truncated Multiplication -- Short Papers 1 -- Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures -- An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free Grammars -- Hardware-Software Partitioning: A Reconfigurable and Evolutionary Computing Approach -- An Approach to Real-Time Visualization of PIV Method with FPGA -- FPGA-Based Discrete Wavelet Transforms System -- X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor -- Arithmetic Operation Oriented Reconfigurable Chip: RHW -- Short Papers 2 -- Initial Analysis of the Proteus Architecture -- Building Asynchronous Circuits with JBits -- Case Study of Integration of Reconfigurable Logic as a Coprocessor into a SCI-Cluster under RT-Linux -- A Reconfigurable Approach to Packet Filtering -- FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding -- A Data Re-use Based Compiler Optimization for FPGAs -- Dijkstra’s Shortest Path Routing Algorithm in Reconfigurable Hardware -- A System on Chip for Power Line Communications According to European Home Systems Specifications. |
| Record Nr. | UNINA-9910768457503321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2001 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||