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Handbook of 3D integration [[electronic resource] ] : technology and applications of 3D integrated circuits / / edited by Philip Garrou, Christopher Bower and Peter Ramm
| Handbook of 3D integration [[electronic resource] ] : technology and applications of 3D integrated circuits / / edited by Philip Garrou, Christopher Bower and Peter Ramm |
| Pubbl/distr/stampa | Weinheim, : Wiley-VCH, 2008 |
| Descrizione fisica | 1 online resource (801 p.) |
| Disciplina |
621.381
621.3815 |
| Altri autori (Persone) |
GarrouPhilip E
BowerChristopher Andrew RammPeter |
| Soggetto topico |
Integrated circuits
Integrated circuits - Design and construction Semiconductor wafers Three-dimensional imaging |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-283-86967-5
3-527-62306-X 3-527-62305-1 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Handbook of 3D Integration; Contents; Preface; List of Contributors; 1 Introduction to 3D Integration; 1.1 Introduction; 1.2 Historical Evolution of Stacked Wafer Concepts; 1.3 3D Packaging vs 3D Integration; 1.4 Non-TSV 3D Stacking Technologies; 1.4.1 Irvine Sensors; 1.4.2 UTCS (Ultrathin Chip Stacking) IMEC, CNRS, U. Barcelona; 1.4.3 Fujitsu; 1.4.4 Fraunhofer/IZM; 1.4.5 3D Plus/Leti; 1.4.6 Toshiba System Block Module; References; 2 Drivers for 3D Integration; 2.1 Introduction; 2.2 Electrical Performance; 2.2.1 Signal Seed; 2.2.2 Memory Latency; 2.3 Power Consumption and Noise; 2.3.1 Noise
2.4 Form Factor2.4.1 Non-Volatile Memory Technology: Flash; 2.4.2 Volatile Memory Technology: SRAM and DRAM; 2.4.3 CMOS Image Sensors; 2.5 Lower Cost; 2.6 Application Based Drivers; 2.6.1 Microprocessors; 2.6.2 Memory; 2.6.3 Sensors; 2.6.4 Fields Programmable Gate Arrays (FPGAs); References; 3 Overview of 3D Integration Process Technology; 3.1 3D Integration Terminology; 3.1.1 Through Silicon Vias (TSVs); 3.1.2 Wafer Thinning; 3.1.3 Aligned Wafer/IC Bonding; 3.2 Processing Sequences; 3.3 Technologies for 3D Integration; 3.3.1 TSV Formation; 3.3.2 Temporary Bonding to Carrier Wafer 3.3.3 Thinning3.3.4 Alignment/Bonding; References; I Through Silicon Via Fabrication; 4 Deep Reactive Ion Etching of Through Silicon Vias; 4.1 Introduction; 4.1.1 Deep Reactive Ion Etching as Breakthrough Enabling Through-Wafer Interconnects; 4.1.2 State of the Art and Basic Principles in DRIE; 4.1.3 Bosch Process; 4.1.4 Alternatives for Via Hole Creation; 4.2 DRIE Equipment and Characterization; 4.2.1 High-Density Plasma Reactors; 4.2.2 Plasma Chemistry; 4.2.3 Plasma Diagnostics and Surface Analysis; 4.3 DRIE Processing; 4.3.1 Mask Issues; 4.3.2 High Aspect Ratio Features 4.3.3 Sidewall Passivation, Depassivation and Profile Control4.4 Practical Solutions in Via Etching; 4.4.1 Undercut and Scallop Reduction; 4.4.2 Sidewall Roughness Minimization; 4.4.3 Loading Effects; 4.4.4 Notching at Dielectric Interfaces; 4.4.5 Inspection of Via Structures; 4.4.6 In Situ Trench Depth Measurement; 4.5 Concluding Remarks; Appendix A: Glossary of Abbreviations; Appendix B: Examples of DRIE Recipes; References; 5 Laser Ablation; 5.1 Introduction; 5.2 Laser Technology for 3D Packaging; 5.2.1 Advantages; 5.2.2 Disadvantages; 5.3 For Si Substrate; 5.3.1 Difficulties 5.3.2 Results5.4 Results for 3D Chip Stacking; 5.5 Reliabilities; 5.6 The Future; References; 6 SiO(2); 6.1 Introduction; 6.2 Dielectric CVD; 6.2.1 Sub-Atmospheric CVD; 6.2.2 Process Sequence of O(3)-Activated SACVD Deposition; 6.2.3 Conformal SACVD O(3) TEOS Films for 3D Integration; 6.3 Dielectric Film Properties; 6.4 3D-Specifics Regarding SiO(2) Dielectrics; 6.4.1 Wafer Pre-Processing; 6.4.2 Backside Processing Requirements on SiO(2) Film Conformality in TSVs; 6.4.3 SiO(2) Film Deposition on Thinned Silicon Substrates; 6.5 Concluding Remarks; References; 7 Insulation - Organic Dielectrics 7.1 Parylene |
| Record Nr. | UNINA-9910144685303321 |
| Weinheim, : Wiley-VCH, 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Handbook of 3D integration [[electronic resource] ] : technology and applications of 3D integrated circuits / / edited by Philip Garrou, Christopher Bower and Peter Ramm
| Handbook of 3D integration [[electronic resource] ] : technology and applications of 3D integrated circuits / / edited by Philip Garrou, Christopher Bower and Peter Ramm |
| Pubbl/distr/stampa | Weinheim, : Wiley-VCH, 2008 |
| Descrizione fisica | 1 online resource (801 p.) |
| Disciplina |
621.381
621.3815 |
| Altri autori (Persone) |
GarrouPhilip E
BowerChristopher Andrew RammPeter |
| Soggetto topico |
Integrated circuits
Integrated circuits - Design and construction Semiconductor wafers Three-dimensional imaging |
| ISBN |
1-283-86967-5
3-527-62306-X 3-527-62305-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Handbook of 3D Integration; Contents; Preface; List of Contributors; 1 Introduction to 3D Integration; 1.1 Introduction; 1.2 Historical Evolution of Stacked Wafer Concepts; 1.3 3D Packaging vs 3D Integration; 1.4 Non-TSV 3D Stacking Technologies; 1.4.1 Irvine Sensors; 1.4.2 UTCS (Ultrathin Chip Stacking) IMEC, CNRS, U. Barcelona; 1.4.3 Fujitsu; 1.4.4 Fraunhofer/IZM; 1.4.5 3D Plus/Leti; 1.4.6 Toshiba System Block Module; References; 2 Drivers for 3D Integration; 2.1 Introduction; 2.2 Electrical Performance; 2.2.1 Signal Seed; 2.2.2 Memory Latency; 2.3 Power Consumption and Noise; 2.3.1 Noise
2.4 Form Factor2.4.1 Non-Volatile Memory Technology: Flash; 2.4.2 Volatile Memory Technology: SRAM and DRAM; 2.4.3 CMOS Image Sensors; 2.5 Lower Cost; 2.6 Application Based Drivers; 2.6.1 Microprocessors; 2.6.2 Memory; 2.6.3 Sensors; 2.6.4 Fields Programmable Gate Arrays (FPGAs); References; 3 Overview of 3D Integration Process Technology; 3.1 3D Integration Terminology; 3.1.1 Through Silicon Vias (TSVs); 3.1.2 Wafer Thinning; 3.1.3 Aligned Wafer/IC Bonding; 3.2 Processing Sequences; 3.3 Technologies for 3D Integration; 3.3.1 TSV Formation; 3.3.2 Temporary Bonding to Carrier Wafer 3.3.3 Thinning3.3.4 Alignment/Bonding; References; I Through Silicon Via Fabrication; 4 Deep Reactive Ion Etching of Through Silicon Vias; 4.1 Introduction; 4.1.1 Deep Reactive Ion Etching as Breakthrough Enabling Through-Wafer Interconnects; 4.1.2 State of the Art and Basic Principles in DRIE; 4.1.3 Bosch Process; 4.1.4 Alternatives for Via Hole Creation; 4.2 DRIE Equipment and Characterization; 4.2.1 High-Density Plasma Reactors; 4.2.2 Plasma Chemistry; 4.2.3 Plasma Diagnostics and Surface Analysis; 4.3 DRIE Processing; 4.3.1 Mask Issues; 4.3.2 High Aspect Ratio Features 4.3.3 Sidewall Passivation, Depassivation and Profile Control4.4 Practical Solutions in Via Etching; 4.4.1 Undercut and Scallop Reduction; 4.4.2 Sidewall Roughness Minimization; 4.4.3 Loading Effects; 4.4.4 Notching at Dielectric Interfaces; 4.4.5 Inspection of Via Structures; 4.4.6 In Situ Trench Depth Measurement; 4.5 Concluding Remarks; Appendix A: Glossary of Abbreviations; Appendix B: Examples of DRIE Recipes; References; 5 Laser Ablation; 5.1 Introduction; 5.2 Laser Technology for 3D Packaging; 5.2.1 Advantages; 5.2.2 Disadvantages; 5.3 For Si Substrate; 5.3.1 Difficulties 5.3.2 Results5.4 Results for 3D Chip Stacking; 5.5 Reliabilities; 5.6 The Future; References; 6 SiO(2); 6.1 Introduction; 6.2 Dielectric CVD; 6.2.1 Sub-Atmospheric CVD; 6.2.2 Process Sequence of O(3)-Activated SACVD Deposition; 6.2.3 Conformal SACVD O(3) TEOS Films for 3D Integration; 6.3 Dielectric Film Properties; 6.4 3D-Specifics Regarding SiO(2) Dielectrics; 6.4.1 Wafer Pre-Processing; 6.4.2 Backside Processing Requirements on SiO(2) Film Conformality in TSVs; 6.4.3 SiO(2) Film Deposition on Thinned Silicon Substrates; 6.5 Concluding Remarks; References; 7 Insulation - Organic Dielectrics 7.1 Parylene |
| Record Nr. | UNINA-9910829969203321 |
| Weinheim, : Wiley-VCH, 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Handbook of 3D integration : technology and applications of 3D integrated circuits / / edited by Philip Garrou, Christopher Bower and Peter Ramm
| Handbook of 3D integration : technology and applications of 3D integrated circuits / / edited by Philip Garrou, Christopher Bower and Peter Ramm |
| Pubbl/distr/stampa | Weinheim, : Wiley-VCH, 2008 |
| Descrizione fisica | 1 online resource (801 p.) |
| Disciplina |
621.381
621.3815 |
| Altri autori (Persone) |
GarrouPhilip E
BowerChristopher Andrew RammPeter |
| Soggetto topico |
Integrated circuits
Integrated circuits - Design and construction Semiconductor wafers Three-dimensional imaging |
| ISBN |
1-283-86967-5
3-527-62306-X 3-527-62305-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Handbook of 3D Integration; Contents; Preface; List of Contributors; 1 Introduction to 3D Integration; 1.1 Introduction; 1.2 Historical Evolution of Stacked Wafer Concepts; 1.3 3D Packaging vs 3D Integration; 1.4 Non-TSV 3D Stacking Technologies; 1.4.1 Irvine Sensors; 1.4.2 UTCS (Ultrathin Chip Stacking) IMEC, CNRS, U. Barcelona; 1.4.3 Fujitsu; 1.4.4 Fraunhofer/IZM; 1.4.5 3D Plus/Leti; 1.4.6 Toshiba System Block Module; References; 2 Drivers for 3D Integration; 2.1 Introduction; 2.2 Electrical Performance; 2.2.1 Signal Seed; 2.2.2 Memory Latency; 2.3 Power Consumption and Noise; 2.3.1 Noise
2.4 Form Factor2.4.1 Non-Volatile Memory Technology: Flash; 2.4.2 Volatile Memory Technology: SRAM and DRAM; 2.4.3 CMOS Image Sensors; 2.5 Lower Cost; 2.6 Application Based Drivers; 2.6.1 Microprocessors; 2.6.2 Memory; 2.6.3 Sensors; 2.6.4 Fields Programmable Gate Arrays (FPGAs); References; 3 Overview of 3D Integration Process Technology; 3.1 3D Integration Terminology; 3.1.1 Through Silicon Vias (TSVs); 3.1.2 Wafer Thinning; 3.1.3 Aligned Wafer/IC Bonding; 3.2 Processing Sequences; 3.3 Technologies for 3D Integration; 3.3.1 TSV Formation; 3.3.2 Temporary Bonding to Carrier Wafer 3.3.3 Thinning3.3.4 Alignment/Bonding; References; I Through Silicon Via Fabrication; 4 Deep Reactive Ion Etching of Through Silicon Vias; 4.1 Introduction; 4.1.1 Deep Reactive Ion Etching as Breakthrough Enabling Through-Wafer Interconnects; 4.1.2 State of the Art and Basic Principles in DRIE; 4.1.3 Bosch Process; 4.1.4 Alternatives for Via Hole Creation; 4.2 DRIE Equipment and Characterization; 4.2.1 High-Density Plasma Reactors; 4.2.2 Plasma Chemistry; 4.2.3 Plasma Diagnostics and Surface Analysis; 4.3 DRIE Processing; 4.3.1 Mask Issues; 4.3.2 High Aspect Ratio Features 4.3.3 Sidewall Passivation, Depassivation and Profile Control4.4 Practical Solutions in Via Etching; 4.4.1 Undercut and Scallop Reduction; 4.4.2 Sidewall Roughness Minimization; 4.4.3 Loading Effects; 4.4.4 Notching at Dielectric Interfaces; 4.4.5 Inspection of Via Structures; 4.4.6 In Situ Trench Depth Measurement; 4.5 Concluding Remarks; Appendix A: Glossary of Abbreviations; Appendix B: Examples of DRIE Recipes; References; 5 Laser Ablation; 5.1 Introduction; 5.2 Laser Technology for 3D Packaging; 5.2.1 Advantages; 5.2.2 Disadvantages; 5.3 For Si Substrate; 5.3.1 Difficulties 5.3.2 Results5.4 Results for 3D Chip Stacking; 5.5 Reliabilities; 5.6 The Future; References; 6 SiO(2); 6.1 Introduction; 6.2 Dielectric CVD; 6.2.1 Sub-Atmospheric CVD; 6.2.2 Process Sequence of O(3)-Activated SACVD Deposition; 6.2.3 Conformal SACVD O(3) TEOS Films for 3D Integration; 6.3 Dielectric Film Properties; 6.4 3D-Specifics Regarding SiO(2) Dielectrics; 6.4.1 Wafer Pre-Processing; 6.4.2 Backside Processing Requirements on SiO(2) Film Conformality in TSVs; 6.4.3 SiO(2) Film Deposition on Thinned Silicon Substrates; 6.5 Concluding Remarks; References; 7 Insulation - Organic Dielectrics 7.1 Parylene |
| Record Nr. | UNINA-9910841560903321 |
| Weinheim, : Wiley-VCH, 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||