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Biblioteca

MARC Lista (tabellare)
Applied Reconfigurable Computing [[electronic resource] ] : 13th International Symposium, ARC 2017, Delft, The Netherlands, April 3-7, 2017, Proceedings / / edited by Stephan Wong, Antonio Carlos Beck, Koen Bertels, Luigi Carro
Applied Reconfigurable Computing [[electronic resource] ] : 13th International Symposium, ARC 2017, Delft, The Netherlands, April 3-7, 2017, Proceedings / / edited by Stephan Wong, Antonio Carlos Beck, Koen Bertels, Luigi Carro
Edizione [1st ed. 2017.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2017
Descrizione fisica 1 online resource (XX, 332 p. 142 illus.)
Disciplina 004
Collana Theoretical Computer Science and General Issues
Soggetto topico Computers
Software engineering
Artificial intelligence
Image processing—Digital techniques
Computer vision
Computer engineering
Computer networks
Computer Hardware
Software Engineering
Artificial Intelligence
Computer Imaging, Vision, Pattern Recognition and Graphics
Computer Engineering and Networks
ISBN 3-319-56258-4
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNISA-996466189903316
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2017
Materiale a stampa
Lo trovi qui: Univ. di Salerno
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Applied Reconfigurable Computing [[electronic resource] ] : 13th International Symposium, ARC 2017, Delft, The Netherlands, April 3-7, 2017, Proceedings / / edited by Stephan Wong, Antonio Carlos Beck, Koen Bertels, Luigi Carro
Applied Reconfigurable Computing [[electronic resource] ] : 13th International Symposium, ARC 2017, Delft, The Netherlands, April 3-7, 2017, Proceedings / / edited by Stephan Wong, Antonio Carlos Beck, Koen Bertels, Luigi Carro
Edizione [1st ed. 2017.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2017
Descrizione fisica 1 online resource (XX, 332 p. 142 illus.)
Disciplina 004
Collana Theoretical Computer Science and General Issues
Soggetto topico Computers
Software engineering
Artificial intelligence
Image processing—Digital techniques
Computer vision
Computer engineering
Computer networks
Computer Hardware
Software Engineering
Artificial Intelligence
Computer Imaging, Vision, Pattern Recognition and Graphics
Computer Engineering and Networks
ISBN 3-319-56258-4
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNINA-9910484715503321
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2017
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009, Proceedings / / edited by Koen Bertels, Nikitas Dimopoulos, Cristina Silvano, Stephan Wong
Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009, Proceedings / / edited by Koen Bertels, Nikitas Dimopoulos, Cristina Silvano, Stephan Wong
Edizione [1st ed. 2009.]
Pubbl/distr/stampa Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009
Descrizione fisica 1 online resource (354 p.)
Disciplina 004.22
Collana Theoretical Computer Science and General Issues
Soggetto topico Computer systems
Computers
Microprocessors
Computer architecture
Computer networks
Electronic digital computers—Evaluation
Computer System Implementation
Computer Hardware
Processor Architectures
Computer Communication Networks
System Performance and Evaluation
ISBN 1-282-33186-8
9786612331862
3-642-03138-2
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Beachnote -- What Else Is Broken? Can We Fix It? -- Architectures for Multimedia -- Programmable and Scalable Architecture for Graphics Processing Units -- The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors -- CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey -- Programmable Accelerators for Reconfigurable Video Decoder -- Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study -- Multiple Description Scalable Coding for Video Transmission over Unreliable Networks -- Multi/Many Cores Architectures -- Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC -- Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture -- Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management -- A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA -- VLSI Architectures Design -- Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing -- Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata -- Prediction in Dynamic SDRAM Controller Policies -- Inversion/Non-inversion Implementation for an 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI -- Architecture Modeling and Exploration Tools -- Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration -- Modeling Scalable SIMD DSPs in LISA -- NoGAP: A Micro Architecture Construction Framework -- A Comparison of NoTA and GENESYS -- Special Session 1: Instruction-Set Customization -- to Instruction-Set Customization -- Constraint-Driven Identification of Application Specific Instructions in the DURASE System -- A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs) -- Runtime Adaptive Extensible Embedded Processors — A Survey -- Special Session 2: The Future of Reconfigurable Computing and Processor Architectures -- to the Future of Reconfigurable Computing and Processor Architectures -- An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems -- Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study -- Reconfigurable Multicore Server Processors for Low Power Operation -- Reconfigurable Computing in the New Age of Parallelism -- Reconfigurable Multithreading Architectures: A Survey -- Special Session 3: Mastering Cell BE and GPU Execution Platforms -- to Mastering Cell BE and GPU Execution Platforms -- Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors -- Implementing Blocked Sparse Matrix-Vector Multiplication on NVIDIA GPUs -- Experiences with Cell-BE and GPU for Tomography -- Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell -- Exploiting Locality on the Cell/B.E. through Bypassing -- Exploiting the Cell/BE Architecture with the StarPU Unified Runtime System.
Record Nr. UNISA-996465602203316
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009, Proceedings / / edited by Koen Bertels, Nikitas Dimopoulos, Cristina Silvano, Stephan Wong
Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009, Proceedings / / edited by Koen Bertels, Nikitas Dimopoulos, Cristina Silvano, Stephan Wong
Edizione [1st ed. 2009.]
Pubbl/distr/stampa Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009
Descrizione fisica 1 online resource (354 p.)
Disciplina 004.22
Collana Theoretical Computer Science and General Issues
Soggetto topico Computer systems
Computers
Microprocessors
Computer architecture
Computer networks
Electronic digital computers—Evaluation
Computer System Implementation
Computer Hardware
Processor Architectures
Computer Communication Networks
System Performance and Evaluation
ISBN 1-282-33186-8
9786612331862
3-642-03138-2
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Beachnote -- What Else Is Broken? Can We Fix It? -- Architectures for Multimedia -- Programmable and Scalable Architecture for Graphics Processing Units -- The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors -- CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey -- Programmable Accelerators for Reconfigurable Video Decoder -- Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study -- Multiple Description Scalable Coding for Video Transmission over Unreliable Networks -- Multi/Many Cores Architectures -- Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC -- Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture -- Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management -- A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA -- VLSI Architectures Design -- Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing -- Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata -- Prediction in Dynamic SDRAM Controller Policies -- Inversion/Non-inversion Implementation for an 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI -- Architecture Modeling and Exploration Tools -- Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration -- Modeling Scalable SIMD DSPs in LISA -- NoGAP: A Micro Architecture Construction Framework -- A Comparison of NoTA and GENESYS -- Special Session 1: Instruction-Set Customization -- to Instruction-Set Customization -- Constraint-Driven Identification of Application Specific Instructions in the DURASE System -- A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs) -- Runtime Adaptive Extensible Embedded Processors — A Survey -- Special Session 2: The Future of Reconfigurable Computing and Processor Architectures -- to the Future of Reconfigurable Computing and Processor Architectures -- An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems -- Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study -- Reconfigurable Multicore Server Processors for Low Power Operation -- Reconfigurable Computing in the New Age of Parallelism -- Reconfigurable Multithreading Architectures: A Survey -- Special Session 3: Mastering Cell BE and GPU Execution Platforms -- to Mastering Cell BE and GPU Execution Platforms -- Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors -- Implementing Blocked Sparse Matrix-Vector Multiplication on NVIDIA GPUs -- Experiences with Cell-BE and GPU for Tomography -- Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell -- Exploiting Locality on the Cell/B.E. through Bypassing -- Exploiting the Cell/BE Architecture with the StarPU Unified Runtime System.
Record Nr. UNINA-9910484388603321
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Proceedings : 2007 International Conference on Field-Programmable Logic and Applications (FPL) : Amsterdam, The Netherlands, August 27-29, 2007 / / editors, Koen Bertels ... [et al.] ; organized by Delft Technological University ; technical co-sponsor IEEE Circuits and Systems Society
Proceedings : 2007 International Conference on Field-Programmable Logic and Applications (FPL) : Amsterdam, The Netherlands, August 27-29, 2007 / / editors, Koen Bertels ... [et al.] ; organized by Delft Technological University ; technical co-sponsor IEEE Circuits and Systems Society
Pubbl/distr/stampa IEEE
Disciplina 621.39/5
Altri autori (Persone) BertelsKoen
Soggetto topico Field programmable gate arrays
Programmable array logic
ISBN 1-5090-8923-3
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Altri titoli varianti 2007 International Conference on Field Programmable Logic and Applications
Computer and Information Technology
Record Nr. UNISA-996280992903316
IEEE
Materiale a stampa
Lo trovi qui: Univ. di Salerno
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Proceedings : 2007 International Conference on Field-Programmable Logic and Applications (FPL) : Amsterdam, The Netherlands, August 27-29, 2007 / / editors, Koen Bertels ... [et al.] ; organized by Delft Technological University ; technical co-sponsor IEEE Circuits and Systems Society
Proceedings : 2007 International Conference on Field-Programmable Logic and Applications (FPL) : Amsterdam, The Netherlands, August 27-29, 2007 / / editors, Koen Bertels ... [et al.] ; organized by Delft Technological University ; technical co-sponsor IEEE Circuits and Systems Society
Pubbl/distr/stampa IEEE
Disciplina 621.39/5
Altri autori (Persone) BertelsKoen
Soggetto topico Field programmable gate arrays
Programmable array logic
ISBN 1-5090-8923-3
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Altri titoli varianti 2007 International Conference on Field Programmable Logic and Applications
Computer and Information Technology
Record Nr. UNINA-9910143145903321
IEEE
Materiale a stampa
Lo trovi qui: Univ. Federico II
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Proceedings : 2006 International Conference on Field-Programmable Logic and Applications (FPL) : Madrid, Mapain, August 28-30, 2006
Proceedings : 2006 International Conference on Field-Programmable Logic and Applications (FPL) : Madrid, Mapain, August 28-30, 2006
Pubbl/distr/stampa [Place of publication not identified], : IEEE, 2006
Disciplina 621.39/5
Soggetto topico Field programmable gate arrays
Programmable array logic
Electrical & Computer Engineering
Electrical Engineering
Engineering & Applied Sciences
ISBN 1-5090-9314-1
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNISA-996216751403316
[Place of publication not identified], : IEEE, 2006
Materiale a stampa
Lo trovi qui: Univ. di Salerno
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Proceedings : 2006 International Conference on Field-Programmable Logic and Applications (FPL) : Madrid, Mapain, August 28-30, 2006
Proceedings : 2006 International Conference on Field-Programmable Logic and Applications (FPL) : Madrid, Mapain, August 28-30, 2006
Pubbl/distr/stampa [Place of publication not identified], : IEEE, 2006
Disciplina 621.39/5
Soggetto topico Field programmable gate arrays
Programmable array logic
Electrical & Computer Engineering
Electrical Engineering
Engineering & Applied Sciences
ISBN 1-5090-9314-1
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNINA-9910142705203321
[Place of publication not identified], : IEEE, 2006
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Reconfigurable Computing: Architectures and Applications [[electronic resource] ] : Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006 Revised Selected Papers / / edited by Koen Bertels, João M.P. Cardoso, Stamatis Vassiliadis
Reconfigurable Computing: Architectures and Applications [[electronic resource] ] : Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006 Revised Selected Papers / / edited by Koen Bertels, João M.P. Cardoso, Stamatis Vassiliadis
Edizione [1st ed. 2006.]
Pubbl/distr/stampa Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006
Descrizione fisica 1 online resource (XVI, 469 p.)
Disciplina 003.3
Collana Theoretical Computer Science and General Issues
Soggetto topico Computer systems
Computers
Microprocessors
Computer architecture
Computer networks
Electronic digital computers—Evaluation
Computer System Implementation
Computer Hardware
Processor Architectures
Computer Communication Networks
System Performance and Evaluation
ISBN 3-540-36863-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Applications -- Implementation of Realtime and Highspeed Phase Detector on FPGA -- Case Study: Implementation of a Virtual Instrument on a Dynamically Reconfigurable Platform -- Configurable Embedded Core for Controlling Electro-Mechanical Systems -- Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors -- Dynamic Partial Reconfigurable FIR Filter Design -- Event-Driven Simulation Engine for Spiking Neural Networks on a Chip -- Towards an Optimal Implementation of MLP in FPGA -- Power -- Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture -- Quality Driven Dynamic Low Power Reconfiguration of Handhelds -- An Efficient Estimation Method of Dynamic Power Dissipation on VLSI Interconnects -- Image Processing -- Highly Paralellized Architecture for Image Motion Estimation -- Design Exploration of a Video Pre-processor for an FPGA Based SoC -- QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection -- Applications of Small-Scale Reconfigurability to Graphics Processors -- An Embedded Multi-camera System for Simultaneous Localization and Mapping -- Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor -- Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-Chip -- Handel-C Design Enhancement for FPGA-Based DV Decoder -- Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES’ Platform -- A New VLSI Architecture of Lifting-Based DWT -- Architecture Based on FPGA’s for Real-Time Image Processing -- Real Time Image Processing on a Portable Aid Device for Low Vision Patients -- General Purpose Real-Time Image Segmentation System -- Organization and Architecture -- Implementation of LPM Address Generators on FPGAs -- Self Reconfiguring EPIC Soft Core Processors -- Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs -- Area/Performance Improvement of NoC Architectures -- Implementation of Inner Product Architecture for Increased Flexibility in Bitwidths of Input Array -- A Flexible Multi-port Caching Scheme for Reconfigurable Platforms -- Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support -- A Reconfigurable Data Cache for Adaptive Processors -- The Emergence of Non-von Neumann Processors -- Scheduling Reconfiguration Activities of Run-Time Reconfigurable RTOS Using an Aperiodic Task Server -- A New Approach to Assess Defragmentation Strategies in Dynamically Reconfigurable FPGAs -- A 1,632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI -- PISC: Polymorphic Instruction Set Computers -- Networks and Communication -- Generic Network Interfaces for Plug and Play NoC Based Architecture -- Providing QoS Guarantees in a NoC by Virtual Channel Reservation -- Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA -- A Reconfigurable Architecture for MIMO Square Root Decoder -- Security -- Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking -- Updates on the Security of FPGAs Against Power Analysis Attacks -- Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems -- FPGA Implementation of a GF(2 m ) Tate Pairing Architecture -- Iterative Modular Division over GF(2 m ): Novel Algorithm and Implementations on FPGA -- Mobile Fingerprint Identification Using a Hardware Accelerated Biometric Service Provider -- UNITE: Uniform Hardware-Based Network Intrusion deTection Engine -- Tools -- Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs -- Automatic Compilation Framework for Bloom Filter Based Intrusion Detection -- A Basic Data Routing Model for a Coarse-Grain Reconfigurable Hardware -- Hardware and a Tool Chain for ADRES -- Integrating Custom Instruction Specifications into C Development Processes -- A Compiler-Oriented Architecture Description for Reconfigurable Systems -- Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software Compatibility -- High-Level Synthesis Using SPARK and Systolic Array -- Super Semi-systolic Array-Based Application-Specific PLD Architecture.
Record Nr. UNISA-996465597903316
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
Reconfigurable Computing: Architectures and Applications [[electronic resource] ] : Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006 Revised Selected Papers / / edited by Koen Bertels, João M.P. Cardoso, Stamatis Vassiliadis
Reconfigurable Computing: Architectures and Applications [[electronic resource] ] : Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006 Revised Selected Papers / / edited by Koen Bertels, João M.P. Cardoso, Stamatis Vassiliadis
Edizione [1st ed. 2006.]
Pubbl/distr/stampa Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006
Descrizione fisica 1 online resource (XVI, 469 p.)
Disciplina 003.3
Collana Theoretical Computer Science and General Issues
Soggetto topico Computer systems
Computers
Microprocessors
Computer architecture
Computer networks
Electronic digital computers—Evaluation
Computer System Implementation
Computer Hardware
Processor Architectures
Computer Communication Networks
System Performance and Evaluation
ISBN 3-540-36863-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Applications -- Implementation of Realtime and Highspeed Phase Detector on FPGA -- Case Study: Implementation of a Virtual Instrument on a Dynamically Reconfigurable Platform -- Configurable Embedded Core for Controlling Electro-Mechanical Systems -- Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors -- Dynamic Partial Reconfigurable FIR Filter Design -- Event-Driven Simulation Engine for Spiking Neural Networks on a Chip -- Towards an Optimal Implementation of MLP in FPGA -- Power -- Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture -- Quality Driven Dynamic Low Power Reconfiguration of Handhelds -- An Efficient Estimation Method of Dynamic Power Dissipation on VLSI Interconnects -- Image Processing -- Highly Paralellized Architecture for Image Motion Estimation -- Design Exploration of a Video Pre-processor for an FPGA Based SoC -- QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection -- Applications of Small-Scale Reconfigurability to Graphics Processors -- An Embedded Multi-camera System for Simultaneous Localization and Mapping -- Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor -- Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-Chip -- Handel-C Design Enhancement for FPGA-Based DV Decoder -- Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES’ Platform -- A New VLSI Architecture of Lifting-Based DWT -- Architecture Based on FPGA’s for Real-Time Image Processing -- Real Time Image Processing on a Portable Aid Device for Low Vision Patients -- General Purpose Real-Time Image Segmentation System -- Organization and Architecture -- Implementation of LPM Address Generators on FPGAs -- Self Reconfiguring EPIC Soft Core Processors -- Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs -- Area/Performance Improvement of NoC Architectures -- Implementation of Inner Product Architecture for Increased Flexibility in Bitwidths of Input Array -- A Flexible Multi-port Caching Scheme for Reconfigurable Platforms -- Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support -- A Reconfigurable Data Cache for Adaptive Processors -- The Emergence of Non-von Neumann Processors -- Scheduling Reconfiguration Activities of Run-Time Reconfigurable RTOS Using an Aperiodic Task Server -- A New Approach to Assess Defragmentation Strategies in Dynamically Reconfigurable FPGAs -- A 1,632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI -- PISC: Polymorphic Instruction Set Computers -- Networks and Communication -- Generic Network Interfaces for Plug and Play NoC Based Architecture -- Providing QoS Guarantees in a NoC by Virtual Channel Reservation -- Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA -- A Reconfigurable Architecture for MIMO Square Root Decoder -- Security -- Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking -- Updates on the Security of FPGAs Against Power Analysis Attacks -- Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems -- FPGA Implementation of a GF(2 m ) Tate Pairing Architecture -- Iterative Modular Division over GF(2 m ): Novel Algorithm and Implementations on FPGA -- Mobile Fingerprint Identification Using a Hardware Accelerated Biometric Service Provider -- UNITE: Uniform Hardware-Based Network Intrusion deTection Engine -- Tools -- Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs -- Automatic Compilation Framework for Bloom Filter Based Intrusion Detection -- A Basic Data Routing Model for a Coarse-Grain Reconfigurable Hardware -- Hardware and a Tool Chain for ADRES -- Integrating Custom Instruction Specifications into C Development Processes -- A Compiler-Oriented Architecture Description for Reconfigurable Systems -- Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software Compatibility -- High-Level Synthesis Using SPARK and Systolic Array -- Super Semi-systolic Array-Based Application-Specific PLD Architecture.
Record Nr. UNINA-9910484564303321
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui