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Architecture of Computing Systems [[electronic resource] ] : 34th International Conference, ARCS 2021, Virtual Event, June 7–8, 2021, Proceedings / / edited by Christian Hochberger, Lars Bauer, Thilo Pionteck
| Architecture of Computing Systems [[electronic resource] ] : 34th International Conference, ARCS 2021, Virtual Event, June 7–8, 2021, Proceedings / / edited by Christian Hochberger, Lars Bauer, Thilo Pionteck |
| Edizione | [1st ed. 2021.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2021 |
| Descrizione fisica | 1 online resource (239 pages) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer networks
Computer systems Computer input-output equipment Software engineering Computer Communication Networks Computer System Implementation Input/Output and Data Communications Software Engineering |
| ISBN | 3-030-81682-6 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Memory Organization -- Locality: The 3rd Wall and The Need for Innovation in Parallel Architectures -- Static extraction of memory access profiles for multi-core interference analysis of real-time tasks -- Transparent Resilience for Approximate DRAM -- Heterogeneous Computing -- Automatic Mapping of Parallel Pattern-based Algorithms on Heterogeneous Architectures -- Assessing and Improving the Suitability of Model-Based Design for GPU-Accelerated Railway Control Systems -- DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model -- Instruction Set Transformations -- Performance Gain of a Data Flow Oriented ISA as Replacement for Java Bytecode -- Towards Transparent Dynamic Binary Translation from RISC-V to a CGRA -- Organic Computing -- An Organic Computing System for Automated Testing -- Evaluating a Priority-Based Task Distribution Strategy for an Artificial Hormone System -- Low Power Design -- Streamlining the OpenMP Programming Model on Ultra-Low-Power Multi-Core MCUs -- Energy Efficient Power-Management for Out-of-Order Processors using Cyclic Power-Gating -- VEFRE Workshop -- BCH 2-Bit and 3-Bit Error Correction with Fast Multi-Bit Error Detection -- Evaluating Soft Error Mitigation Trade-offs During Early Design Stages. |
| Record Nr. | UNISA-996464513403316 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2021 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Architecture of Computing Systems : 34th International Conference, ARCS 2021, Virtual Event, June 7–8, 2021, Proceedings / / edited by Christian Hochberger, Lars Bauer, Thilo Pionteck
| Architecture of Computing Systems : 34th International Conference, ARCS 2021, Virtual Event, June 7–8, 2021, Proceedings / / edited by Christian Hochberger, Lars Bauer, Thilo Pionteck |
| Edizione | [1st ed. 2021.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2021 |
| Descrizione fisica | 1 online resource (239 pages) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer networks
Computer systems Computer input-output equipment Software engineering Computer Communication Networks Computer System Implementation Input/Output and Data Communications Software Engineering Arquitectura d'ordinadors Sistemes informàtics |
| Soggetto genere / forma |
Congressos
Llibres electrònics |
| ISBN | 3-030-81682-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Memory Organization -- Locality: The 3rd Wall and The Need for Innovation in Parallel Architectures -- Static extraction of memory access profiles for multi-core interference analysis of real-time tasks -- Transparent Resilience for Approximate DRAM -- Heterogeneous Computing -- Automatic Mapping of Parallel Pattern-based Algorithms on Heterogeneous Architectures -- Assessing and Improving the Suitability of Model-Based Design for GPU-Accelerated Railway Control Systems -- DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model -- Instruction Set Transformations -- Performance Gain of a Data Flow Oriented ISA as Replacement for Java Bytecode -- Towards Transparent Dynamic Binary Translation from RISC-V to a CGRA -- Organic Computing -- An Organic Computing System for Automated Testing -- Evaluating a Priority-Based Task Distribution Strategy for an Artificial Hormone System -- Low Power Design -- Streamlining the OpenMP Programming Model on Ultra-Low-Power Multi-Core MCUs -- Energy Efficient Power-Management for Out-of-Order Processors using Cyclic Power-Gating -- VEFRE Workshop -- BCH 2-Bit and 3-Bit Error Correction with Fast Multi-Bit Error Detection -- Evaluating Soft Error Mitigation Trade-offs During Early Design Stages. |
| Record Nr. | UNINA-9910492144003321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2021 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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