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Logic synthesis for VLSI-based combined finite state machines : synthesis targeting ASICs, CPLDs and FPGAs / / edited by Alexander Barkalov [and four others]
| Logic synthesis for VLSI-based combined finite state machines : synthesis targeting ASICs, CPLDs and FPGAs / / edited by Alexander Barkalov [and four others] |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , [2023] |
| Descrizione fisica | 1 online resource (305 pages) |
| Disciplina | 629.8 |
| Collana | Lecture Notes in Electrical Engineering |
| Soggetto topico |
Integrated circuits - Very large scale integration
Automatic control Sequential machine theory |
| ISBN | 3-031-16027-4 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Preface -- Contents -- Abbreviations -- 1 Control Algorithms and Finite State Machines -- 1.1 Methods of Implementation of Control Algorithms -- 1.2 Basic Models of Finite State Machines -- 1.3 Synthesis of Mealy FSM -- 1.4 Synthesis of Moore FSM -- 1.5 Synthesis of Microprogram Control Units -- 1.6 Background of Combined FSMs -- References -- 2 VLSI-based Logic Synthesis -- 2.1 Evaluation of Logic Elements -- 2.2 Logic Synthesis with ASICs -- 2.3 Logic Synthesis with CPLDs -- 2.4 Logic Synthesis with FPGAs -- References -- 3 ASIC-based Synthesis of CFSMs -- 3.1 Trivial Matrix Implementation -- 3.2 Structural Decomposition for Matrix CFSMs -- 3.3 PES-based Matrix Circuits of Moore FSMs -- 3.4 Analysis of CFSM-based Matrix Circuits -- References -- 4 Optimization of ASIC-based CFSMs -- 4.1 CFSMs with Optimal State Assignment -- 4.2 CFSMs with Transformation of State Codes -- 4.3 CFSMs with Partial Code Transformation -- 4.4 CFSMs with Primary Encoding of Classes of PES -- References -- 5 Homogenous CPLD-Based Synthesis of CFSMs -- 5.1 Preliminary Information -- 5.2 Synthesis of P CFSM -- 5.3 Synthesis of CFSMs with Optimal State Assignment -- 5.4 Synthesis of CFSMs with Transformation of State Codes -- 5.5 Synthesis of CFSMs with Primary Encoding of Classes -- References -- 6 Heterogeneous CPLD-based Synthesis of CFSMs -- 6.1 Preliminary Information -- 6.2 Synthesis of CFSMs with Trivial State Assignment -- 6.3 Synthesis of CFSMs with Optimal State Assignment -- 6.4 Synthesis of CFSMs with Primary Encoding of Classes -- 6.5 Synthesis of CFSMs with Transformation of Object Codes -- References -- 7 CPLD-Based Synthesis with Transformation of State Codes -- 7.1 Synthesis with Complete State Transformation -- 7.2 Partial State Transformation: Homogenous CPLDs -- 7.3 Partial State Transformation: Heterogenous CPLDs.
7.4 Combining Different Methods of Object Transformation -- References -- 8 FPGA-Based Synthesis of CFSMs -- 8.1 Preliminary Information -- 8.2 Primary Encoding of Classes of PES for FPGA-Based GFSMs -- 8.3 FPGA-Based Synthesis with Transformation of Class Codes -- 8.4 Twofold State Assignment in CFSMs -- References -- Appendix Conclusion -- Index. |
| Record Nr. | UNISA-996499854203316 |
| Cham, Switzerland : , : Springer, , [2023] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Logic synthesis for VLSI-based combined finite state machines : synthesis targeting ASICs, CPLDs and FPGAs / / edited by Alexander Barkalov [and four others]
| Logic synthesis for VLSI-based combined finite state machines : synthesis targeting ASICs, CPLDs and FPGAs / / edited by Alexander Barkalov [and four others] |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , [2023] |
| Descrizione fisica | 1 online resource (305 pages) |
| Disciplina | 629.8 |
| Collana | Lecture Notes in Electrical Engineering |
| Soggetto topico |
Integrated circuits - Very large scale integration
Automatic control Sequential machine theory |
| ISBN | 3-031-16027-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Preface -- Contents -- Abbreviations -- 1 Control Algorithms and Finite State Machines -- 1.1 Methods of Implementation of Control Algorithms -- 1.2 Basic Models of Finite State Machines -- 1.3 Synthesis of Mealy FSM -- 1.4 Synthesis of Moore FSM -- 1.5 Synthesis of Microprogram Control Units -- 1.6 Background of Combined FSMs -- References -- 2 VLSI-based Logic Synthesis -- 2.1 Evaluation of Logic Elements -- 2.2 Logic Synthesis with ASICs -- 2.3 Logic Synthesis with CPLDs -- 2.4 Logic Synthesis with FPGAs -- References -- 3 ASIC-based Synthesis of CFSMs -- 3.1 Trivial Matrix Implementation -- 3.2 Structural Decomposition for Matrix CFSMs -- 3.3 PES-based Matrix Circuits of Moore FSMs -- 3.4 Analysis of CFSM-based Matrix Circuits -- References -- 4 Optimization of ASIC-based CFSMs -- 4.1 CFSMs with Optimal State Assignment -- 4.2 CFSMs with Transformation of State Codes -- 4.3 CFSMs with Partial Code Transformation -- 4.4 CFSMs with Primary Encoding of Classes of PES -- References -- 5 Homogenous CPLD-Based Synthesis of CFSMs -- 5.1 Preliminary Information -- 5.2 Synthesis of P CFSM -- 5.3 Synthesis of CFSMs with Optimal State Assignment -- 5.4 Synthesis of CFSMs with Transformation of State Codes -- 5.5 Synthesis of CFSMs with Primary Encoding of Classes -- References -- 6 Heterogeneous CPLD-based Synthesis of CFSMs -- 6.1 Preliminary Information -- 6.2 Synthesis of CFSMs with Trivial State Assignment -- 6.3 Synthesis of CFSMs with Optimal State Assignment -- 6.4 Synthesis of CFSMs with Primary Encoding of Classes -- 6.5 Synthesis of CFSMs with Transformation of Object Codes -- References -- 7 CPLD-Based Synthesis with Transformation of State Codes -- 7.1 Synthesis with Complete State Transformation -- 7.2 Partial State Transformation: Homogenous CPLDs -- 7.3 Partial State Transformation: Heterogenous CPLDs.
7.4 Combining Different Methods of Object Transformation -- References -- 8 FPGA-Based Synthesis of CFSMs -- 8.1 Preliminary Information -- 8.2 Primary Encoding of Classes of PES for FPGA-Based GFSMs -- 8.3 FPGA-Based Synthesis with Transformation of Class Codes -- 8.4 Twofold State Assignment in CFSMs -- References -- Appendix Conclusion -- Index. |
| Record Nr. | UNINA-9910632470003321 |
| Cham, Switzerland : , : Springer, , [2023] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Methods of signal processing for adaptive antenna arrays / / Larysa Titarenko and Alexander Barkalov
| Methods of signal processing for adaptive antenna arrays / / Larysa Titarenko and Alexander Barkalov |
| Autore | Titarenko Larysa |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | Berlin ; ; Heidleberg, : Springer-Verlag, 2012, c2013 |
| Descrizione fisica | 1 online resource (233 p.) |
| Disciplina |
621.382/4
621.3822 |
| Altri autori (Persone) | BarkalovAlexander |
| Collana | Signals and communication technology |
| Soggetto topico |
Signal processing
Adaptive antennas |
| ISBN |
9786613944177
9781283631723 1283631725 9783642321320 3642321321 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Title; Acknowledgements; Abbreviations; Introduction; General Characteristic of Methods for STSP; Analysis of Methods of Nonadaptive Spatial Signal Processing; Analysis of Peculiarities of Adaptive Spatial Signal Processing; Analysis of Non-structural Methods of Adaptive STSP; Analysis of Classical Structural Methods of Adaptive STSP; References; Background of Classical Theory of ASSP; Analysis of Typical Description of Signal-Noise Situation; Introduction into System of Criteria of Optimality; Analysis of Algorithms of Adaptive Space-Time Signal Processing; References
Features of ASSP under Different Levels of A-Priori UncertaintyAnalysis of Peculiarities of ASSP with Different Levels of A-Priori Uncertainty; Nature of a Priori Uncertainty about Properties of Signal and Noise; Methods of SSP under Generalized Parametric Uncertainty about the Noise Properties; Methods of SP under a Priory Parametric Uncertainty about Properties of Useful Signal; References; Algorithms of ASSP with Not Exactly Known Parameters; Main Approaches for Development of Algorithms of ASSP with Not Exactly Known Parameters Probabilistic Approach for Synthesis of Robust Algorithms of ASSPDeterministic Approach: Robust Algorithms of ASSP for Modified Optimization Tasks; Restrictions for Value of Arbitrary Directivity Characteristic of Antenna; Additional Linear Restrictions; Restrictions of Standard Deviation for Directivity Characteristic of AA from the Given Value; Correlative Restrictions; Restrictions for the Shape of Amplitude-Phase Distribution of Currents in Channels of AA; Restriction for Value of Modulus of Output Signal of AA; Restrictions for Value of Norm ofWeight Coefficients Peculiarities of Robustnization for Algorithms of ASSPApproximation of Control Vector by Section of Taylor Series; Projection Approach; Robustnization of ASSP Algorithms Using Nonlinear Transformations of Input Signals; Restrictions of Existed Methods of ASPS with Not Exactly Known Parameters; References; Background of ASSP with Not Exactly Known Parameters; Elements of Axiomatic and Some Analogies; Generalized Linear Systems of Rayleigh and Centrosymmetric Matrices; Algorithms of ASF Basing on Operators' Construction in Banach Space; Methods of Construction of Operators Minimax Approach for Operator's Construction and Principle of ComparisonAdaptive Approach for Construction of Operators; Optimization Tasks with Squared Restrictions of the Unstrict Inequalities Type; Construction of Optimization Tasks with Mixed Restrictions; Construction of Optimization Tasks with Generalized Mixed Restrictions; Conclusion; References; Synthesis of ASF Algorithms for Not Exactly Known Parameters; Synthesis of Minimax Algorithms; Synthesis of Adaptive Algorithms; Synthesis of Algorithms for Adaptation of Structures of Operators to Current SIE Analysis of Quality for ASF Algorithms for Signals with Not Exactly Known Parameters |
| Record Nr. | UNINA-9910437903203321 |
Titarenko Larysa
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| Berlin ; ; Heidleberg, : Springer-Verlag, 2012, c2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Synthesis and Optimization of FPGA-Based Systems / / by Valery Sklyarov, Iouliia Skliarova, Alexander Barkalov, Larysa Titarenko
| Synthesis and Optimization of FPGA-Based Systems / / by Valery Sklyarov, Iouliia Skliarova, Alexander Barkalov, Larysa Titarenko |
| Autore | Sklyarov Valery |
| Edizione | [1st ed. 2014.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2014 |
| Descrizione fisica | 1 online resource (443 p.) |
| Disciplina | 621.395 |
| Collana | Lecture Notes in Electrical Engineering |
| Soggetto topico |
Electronic circuits
Electronics Microelectronics Circuits and Systems Electronics and Microelectronics, Instrumentation |
| ISBN | 3-319-04708-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
""Synthesis and Optimization of FPGA-Based Systems ""; ""Preface""; ""Contents""; ""Abbreviations""; ""Conventions""; ""Part I Design of Digital Circuits and Systems on the Basis of FPGA""; ""1 FPGA Architectures, Reconfigurable Fabric, Embedded Blocks and Design Tools""; ""Abstract ""; ""1.1 Introduction to FPGA""; ""1.2 The Basis of FPGA Devices""; ""1.2.1 Configurable Logic Blocks of Xilinx FPGAs""; ""1.2.2 Logic Elements of Altera FPGAs""; ""1.3 Embedded Blocks ""; ""1.3.1 Embedded Memories""; ""1.3.2 Embedded DSP Slices""; ""1.4 Clock Distributions and Resets ""; ""1.5 Design Tools""
""1.6 Implementation and Prototyping """"1.7 Interaction with FPGA-Based Circuits and Systems""; ""References""; ""2 Synthesizable VHDL for FPGA-Based Devices""; ""Abstract ""; ""2.1 Introduction to VHDL""; ""2.2 Data Types, Objects and Operators""; ""2.3 Combinational and Sequential Processes""; ""2.3.1 Combinational Processes""; ""2.3.2 Sequential Processes""; ""2.4 Functions, Procedures, and Blocks""; ""2.5 Generics and Generates""; ""2.6 Libraries, Packages, and Files""; ""2.7 Behavioral Simulation""; ""2.8 Prototyping""; ""References""; ""3 Design Techniques""; ""Abstract "" ""3.1 Combinational Circuits""""3.1.1 Encoders""; ""3.1.2 Decoders""; ""3.1.3 Multiplexers""; ""3.1.4 Comparators""; ""3.1.5 Arithmetical Circuits""; ""3.1.6 Barrel Shifters""; ""3.2 Sequential Circuits""; ""3.2.1 Registers""; ""3.2.2 Shift Registers""; ""3.2.3 Counters""; ""3.2.4 Arithmetical Circuits with Accumulators""; ""3.3 Finite State Machines""; ""3.4 Optimization of FPGA-Based Circuits and Systems""; ""3.4.1 Highly Parallel Network-Based Solutions""; ""3.4.2 Hardware Accelerators""; ""3.4.3 Parallel Modular Algorithms Running in Hierarchical FSMs"" ""3.5 Design Examples for Parallel Sort""""3.6 Design Examples for Parallel Search""; ""3.7 Design Examples for Parallel Counters""; ""3.8 Design Examples for Counting Networks""; ""3.9 Design Examples for LUT-Based Hamming Weight CountersComparators""; ""3.10 Design Examples for Operations Over Vectors""; ""References""; ""4 Embedded Blocks and System-Level Design""; ""Abstract ""; ""4.1 Using IP Cores""; ""4.2 Design with Embedded DSP Slices""; ""4.3 Interaction with FPGA""; ""4.3.1 Digilent Parallel Port Interface""; ""4.3.1.1 Digilent EPP Communication Module"" ""4.3.1.2 Application Software""""4.3.2 UART Interface""; ""4.3.2.1 UART Communication Module""; ""4.3.2.2 Application Software""; ""4.4 SoftwareHardware Co-design and Co-simulation""; ""4.4.1 Software-Hardware Co-design with Digilent Parallel Port Interface""; ""4.4.2 Software-Hardware Co-design with UART Interface""; ""4.5 Programmable Systems-on-Chip""; ""References""; ""5 Design Technique Based on Hierarchical and Parallel Specifications""; ""Abstract ""; ""5.1 Modular Hierarchical Specifications""; ""5.2 Hierarchical Finite State Machines"" ""5.2.1 HDL Template for HFSM with Explicit Modules"" |
| Record Nr. | UNINA-9910299485803321 |
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Sklyarov Valery
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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