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Foundations of Embedded Systems / / by Alexander Barkalov, Larysa Titarenko, Małgorzata Mazurkiewicz
Foundations of Embedded Systems / / by Alexander Barkalov, Larysa Titarenko, Małgorzata Mazurkiewicz
Autore Barkalov Alexander
Edizione [1st ed. 2019.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019
Descrizione fisica 1 online resource (XIII, 167 p. 142 illus., 16 illus. in color.)
Disciplina 621.3815
Collana Studies in Systems, Decision and Control
Soggetto topico Electronic circuits
Computational intelligence
Electronics
Microelectronics
Control engineering
Circuits and Systems
Computational Intelligence
Electronics and Microelectronics, Instrumentation
Control and Systems Theory
ISBN 3-030-11961-0
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction into embedded systems -- Design of embedded systems -- Implementation of computational algorithms in embedded systems -- Field programmable gate arrays -- Implementing Control Algorithms with FPGAs -- Programmable Logic Controllers -- Conclusion.
Record Nr. UNINA-9910337630403321
Barkalov Alexander  
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Logic synthesis for finite state machines based on linear chains of states : foundations, recent developments and challenges / / by Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski
Logic synthesis for finite state machines based on linear chains of states : foundations, recent developments and challenges / / by Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski
Autore Barkalov Alexander
Edizione [1st ed. 2018.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018
Descrizione fisica 1 online resource (VIII, 225 p. 145 illus.)
Disciplina 511.3
Collana Studies in Systems, Decision and Control
Soggetto topico Computational intelligence
Electronic circuits
Computational Intelligence
Circuits and Systems
ISBN 3-319-59837-6
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction -- Finite state machines and field-programmable gate arrays -- Linear chains in FSMs -- Hardware reduction for Moore UFSMs -- Hardware reduction for Mealy UFSMs -- Hardware reduction for Moore NFSMs -- Hardware reduction for Moore XFSMs.
Record Nr. UNINA-9910299908703321
Barkalov Alexander  
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Logic synthesis for FPGA-based control units : structural decomposition in logic design / / Alexander Barkalov [et al.]
Logic synthesis for FPGA-based control units : structural decomposition in logic design / / Alexander Barkalov [et al.]
Autore Barkalov Alexander
Edizione [1st edition 2020.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020
Descrizione fisica 1 online resource (257 p.)
Disciplina 621.395
Collana Lecture Notes in Electrical Engineering
Soggetto topico Control engineering
Electronic circuits
Logic circuits - Design
ISBN 3-030-38295-8
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto FSM-Based Models of Control Units -- Structural decomposition in FSM synthesis -- Twofold State Assignment for Mealy FSMs -- Twofold state assignment for Moore FSMs -- Combining twofold state assignment with transformation of object codes -- Combining twofold state assignment with replacement of logical conditions -- Mixed encoding of microoperations -- Synthesis of Mealy FSMs with counters.
Record Nr. UNINA-9910484916703321
Barkalov Alexander  
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Logic Synthesis for FPGA-Based Finite State Machines / / by Alexander Barkalov, Larysa Titarenko, Malgorzata Kolopienczyk, Kamil Mielcarek, Grzegorz Bazydlo
Logic Synthesis for FPGA-Based Finite State Machines / / by Alexander Barkalov, Larysa Titarenko, Malgorzata Kolopienczyk, Kamil Mielcarek, Grzegorz Bazydlo
Autore Barkalov Alexander
Edizione [1st ed. 2016.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016
Descrizione fisica 1 online resource (287 p.)
Disciplina 621.395
Collana Studies in Systems, Decision and Control
Soggetto topico Control engineering
Electronic circuits
Mathematical models
Control and Systems Theory
Circuits and Systems
Mathematical Modeling and Industrial Mathematics
ISBN 3-319-24202-4
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Preface; Contents; Abbreviations; 1 Background of Finite State Machines and Programmable Logic; 1.1 Basic Models of FSMs; 1.2 Logic Synthesis for Microprogram Automata; 1.3 Logic Synthesis for Microprogram Control Units; 1.4 Logic Synthesis for Compositional MCUs; 1.5 Hardware Reduction for FPLD-Based FSMs; References; 2 Field Programmable Gate Arrays in FSM Design; 2.1 General Characteristic of FPGAs; 2.2 Trivial Implementing FPGA-Based FSMs; 2.3 Methods of State Assignment; 2.4 Hardware Reduction for FPGA-Based FSMs; References; 3 Object Codes Transformation for Mealy FSMs
3.1 Principle of OCT for Mealy FSMs3.2 Synthesis of FPGA-Based Mealy FSMs with Transformation of States; 3.3 Synthesis of FPGA-Based Mealy FSMs with Transformation of CMOs; 3.4 Replacement of Logical Conditions in Mealy FSMs with OCT; 3.5 Analysis of Proposed Methods; References; 4 Object Codes Transformation for Moore FSMs ; 4.1 Principle of OCT for Moore FSMs; 4.2 Synthesis of FPGA-Based Moore FSMs with Transformations of States; 4.3 Synthesis of FPGA-Based Moore FSMs with Transformation of CMOs; 4.4 Replacement of Logical Conditions in Moore FSMs with OCT; References
5 Distribution of Class Codes in Moore FSMs5.1 The Case of CPLD-Based FSMs; 5.2 Two Sources of Class Codes in FPGA-Based Moore FSMs; 5.3 Three Sources of Class Codes in FPGA-Based Moore FSMs; 5.4 Replacement of Logical Conditions and Distribution of Class Codes; 5.5 Increasing the Number of Class Variables; References; 6 Hardware Reduction in Multidirectional Moore FSMs; 6.1 Hardware Reduction in Two-Directional Moore FSMs; 6.2 Hardware Reduction in 3-Directional Moore FSMs; 6.3 Replacement of Logical Conditions for K-Directional Moore FSMs; References; 7 Design of EMB-Based Mealy FSMs
7.1 Trivial Implementing Mealy FSMs7.2 Encoding of Objects in Mealy FSMs; 7.3 Replacement of Logical Conditions for Mealy FSMs; 7.4 Hardware Reduction for BRLC; References; 8 Design of EMB-Based Moore FSMs; 8.1 Trivial Implementing Moore FSMs; 8.2 Structural Decomposition for Moore FSMs; 8.3 Optimization of BIMF Based on Pseudoequivalent States; 8.4 Optimizing LUTer in Replacement of Logical Conditions; References; Conclusion; Index
Record Nr. UNINA-9910254209903321
Barkalov Alexander  
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui