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Embedded Systems Design with FPGAs [[electronic resource] /] / edited by Peter Athanas, Dionisios Pnevmatikatos, Nicolas Sklavos
| Embedded Systems Design with FPGAs [[electronic resource] /] / edited by Peter Athanas, Dionisios Pnevmatikatos, Nicolas Sklavos |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | New York, NY : , : Springer New York : , : Imprint : Springer, , 2013 |
| Descrizione fisica | 1 online resource (281 p.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Electronic circuits
Electronics Microelectronics Microprocessors Circuits and Systems Electronics and Microelectronics, Instrumentation Processor Architectures |
| Soggetto non controllato |
Engineering
Computer science Systems engineering Circuits and Systems Electronics and Microelectronics, Instrumentation |
| ISBN |
1-283-93351-9
1-4614-1362-1 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Preface -- Widening the Memory Bottleneck by Automatically-Compiled Application-Specific Speculation Mechanisms -- Decimal Division using the Newton-Raphson Method and Radix-1000 Arithmetic -- Lifetime Reliability Sensing In Modern FPGAs -- Model-Based Performance Evaluation of Dynamic Partial Reconfigurable FPGAs -- Switch design for soft interconnection networks -- Embedded Systems Start-up under Timing Constraints on Modern FPGAs -- Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC - SVC Video Codecs -- CAPH: A Language for Implementing Stream-Processing Applications on FPGAs -- Compact Clefia Implementation on FPGAs -- A Systematic Method to Evaluate and Compare the Performance of Physical Unclonable Functions. |
| Record Nr. | UNINA-9910437911303321 |
| New York, NY : , : Springer New York : , : Imprint : Springer, , 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
IEEE Symposium on FPGAs for Custom Computing Machines : proceedings, April 19-21, 1995, Napa Valley, California
| IEEE Symposium on FPGAs for Custom Computing Machines : proceedings, April 19-21, 1995, Napa Valley, California |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society Press, 1995 |
| Disciplina | 004.16 |
| Soggetto topico |
Electronic digital computers
Engineering & Applied Sciences Computer Science |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996210274303316 |
| [Place of publication not identified], : IEEE Computer Society Press, 1995 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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ReConFig '17 : 2017 International Conference on Reconfigurable Computing and FPGAs : Cancun, Mexico, December 4-6, 2017 / / editors, Peter Athanas, René Cumplido, Claudia Feregrino, Ron Sass
| ReConFig '17 : 2017 International Conference on Reconfigurable Computing and FPGAs : Cancun, Mexico, December 4-6, 2017 / / editors, Peter Athanas, René Cumplido, Claudia Feregrino, Ron Sass |
| Pubbl/distr/stampa | New York : , : IEEE, , 2018 |
| Descrizione fisica | 1 online resource (183 pages) |
| Soggetto topico |
Adaptive computing systems
Field programmable gate arrays |
| ISBN | 1-5386-3797-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996280444303316 |
| New York : , : IEEE, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
ReConFig '17 : 2017 International Conference on Reconfigurable Computing and FPGAs : Cancun, Mexico, December 4-6, 2017 / / editors, Peter Athanas, René Cumplido, Claudia Feregrino, Ron Sass
| ReConFig '17 : 2017 International Conference on Reconfigurable Computing and FPGAs : Cancun, Mexico, December 4-6, 2017 / / editors, Peter Athanas, René Cumplido, Claudia Feregrino, Ron Sass |
| Pubbl/distr/stampa | New York : , : IEEE, , 2018 |
| Descrizione fisica | 1 online resource (183 pages) |
| Soggetto topico |
Adaptive computing systems
Field programmable gate arrays |
| ISBN | 1-5386-3797-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910258254103321 |
| New York : , : IEEE, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Reconfigurable Computing: Architectures, Tools and Applications [[electronic resource] ] : 8th International Symposium, ARC 2012, Hongkong, China, March 19-23, 2012, Proceedings / / edited by Oliver Choy, Ray Cheung, Peter Athanas, Kentaro Sano
| Reconfigurable Computing: Architectures, Tools and Applications [[electronic resource] ] : 8th International Symposium, ARC 2012, Hongkong, China, March 19-23, 2012, Proceedings / / edited by Oliver Choy, Ray Cheung, Peter Athanas, Kentaro Sano |
| Edizione | [1st ed. 2012.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2012 |
| Descrizione fisica | 1 online resource (XIV, 386 p. 24 illus.) |
| Disciplina | 004.6 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer networks
Algorithms Software engineering Computer science Computer programming Computer simulation Computer Communication Networks Software Engineering Theory of Computation Programming Techniques Computer Modelling |
| ISBN | 3-642-28365-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996465940503316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Reconfigurable Computing: Architectures, Tools and Applications [[electronic resource] ] : 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009, Proceedings / / edited by Jürgen Becker, Roger Woods, Peter Athanas, Fearghal Morgan
| Reconfigurable Computing: Architectures, Tools and Applications [[electronic resource] ] : 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009, Proceedings / / edited by Jürgen Becker, Roger Woods, Peter Athanas, Fearghal Morgan |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 |
| Descrizione fisica | 1 online resource (XV, 388 p.) |
| Disciplina | 004 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computers
Microprocessors Computer architecture Computer networks Electronic digital computers—Evaluation Computer systems Computer vision Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation Computer System Implementation Computer Vision |
| ISBN | 3-642-00641-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynotes -- FPGA Design Productivity – A Discussion of the State of the Art and a Research Agenda -- Resiliency in Elemental Computing -- The Colour of Embedded Computation -- Applications 1 -- A HyperTransport 3 Physical Layer Interface for FPGAs -- Parametric Design for Reconfigurable Software-Defined Radio -- Applications 2 -- Hardware/Software FPGA Architecture for Robotics Applications -- Reconfigurable Operator Based Multimedia Embedded Processor -- FPGA Security and Bitstream Analysis -- A Protocol for Secure Remote Updates of FPGA Configurations -- FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing -- Fault Tolerant Systems -- An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications -- Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs -- Architectures -- A Novel Local Interconnect Architecture for Variable Grain Logic Cell -- Dynamically Adapted Low Power ASIPs -- Fast Optical Reconfiguration of a Nine-Context DORGA -- Place and Route Techniques -- Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep -- On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks -- A New Datapath Merging Method for Reconfigurable System -- Cryptography -- Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform -- Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm -- Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs -- Resource Allocation and Scheduling -- Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures -- Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems -- Applications 3 -- Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator -- FPGA-Based Anomalous Trajectory Detection Using SOFM -- Posters -- SORU: A Reconfigurable Vector Unit for Adaptable Embedded Systems -- A Parallel Branching Program Machine for Emulation of Sequential Circuits -- Memory Sharing Approach for TMR Softcore Processor -- The Need for Reconfigurable Routers in Networks-on-Chip -- Transparent Dynamic Reconfiguration as a Service of a System-Level Middleware -- Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder -- Tile-Based Fault Tolerant Approach Using Partial Reconfiguration -- Regular Expression Pattern Matching Supporting Constrained Repetitions -- Accelerating Calculations on the RASC Platform: A Case Study of the Exponential Function -- AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications -- CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers -- Object Tracking and Motion Capturing in Hardware-Accelerated Multi-camera System -- Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture -- A Hardware Accelerated Simulation Environment for Spiking Neural Networks -- Survey of Advanced CABAC Accelerator Architectures for Future Multimedia -- Real Time Simulation in Floating Point Precision Using FPGA Computing -- A Hardware Analysis of Twisted Edwards Curves for an Elliptic Curve Cryptosystem -- A Seamless Virtualization Approach for Transparent Dynamical Function Mapping Targeting Heterogeneous and Reconfigurable Systems -- Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator -- ACCFS – Operating System Integration of Computational Accelerators Using a VFS Approach -- A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms. |
| Record Nr. | UNISA-996465883203316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Reconfigurable Computing: Architectures, Tools and Applications : 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009, Proceedings / / edited by Jürgen Becker, Roger Woods, Peter Athanas, Fearghal Morgan
| Reconfigurable Computing: Architectures, Tools and Applications : 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009, Proceedings / / edited by Jürgen Becker, Roger Woods, Peter Athanas, Fearghal Morgan |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 |
| Descrizione fisica | 1 online resource (XV, 388 p.) |
| Disciplina | 004 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computers
Microprocessors Computer architecture Computer networks Electronic digital computers—Evaluation Computer systems Computer vision Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation Computer System Implementation Computer Vision |
| ISBN | 3-642-00641-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynotes -- FPGA Design Productivity – A Discussion of the State of the Art and a Research Agenda -- Resiliency in Elemental Computing -- The Colour of Embedded Computation -- Applications 1 -- A HyperTransport 3 Physical Layer Interface for FPGAs -- Parametric Design for Reconfigurable Software-Defined Radio -- Applications 2 -- Hardware/Software FPGA Architecture for Robotics Applications -- Reconfigurable Operator Based Multimedia Embedded Processor -- FPGA Security and Bitstream Analysis -- A Protocol for Secure Remote Updates of FPGA Configurations -- FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing -- Fault Tolerant Systems -- An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications -- Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs -- Architectures -- A Novel Local Interconnect Architecture for Variable Grain Logic Cell -- Dynamically Adapted Low Power ASIPs -- Fast Optical Reconfiguration of a Nine-Context DORGA -- Place and Route Techniques -- Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep -- On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks -- A New Datapath Merging Method for Reconfigurable System -- Cryptography -- Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform -- Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm -- Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs -- Resource Allocation and Scheduling -- Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures -- Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems -- Applications 3 -- Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator -- FPGA-Based Anomalous Trajectory Detection Using SOFM -- Posters -- SORU: A Reconfigurable Vector Unit for Adaptable Embedded Systems -- A Parallel Branching Program Machine for Emulation of Sequential Circuits -- Memory Sharing Approach for TMR Softcore Processor -- The Need for Reconfigurable Routers in Networks-on-Chip -- Transparent Dynamic Reconfiguration as a Service of a System-Level Middleware -- Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder -- Tile-Based Fault Tolerant Approach Using Partial Reconfiguration -- Regular Expression Pattern Matching Supporting Constrained Repetitions -- Accelerating Calculations on the RASC Platform: A Case Study of the Exponential Function -- AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications -- CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers -- Object Tracking and Motion Capturing in Hardware-Accelerated Multi-camera System -- Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture -- A Hardware Accelerated Simulation Environment for Spiking Neural Networks -- Survey of Advanced CABAC Accelerator Architectures for Future Multimedia -- Real Time Simulation in Floating Point Precision Using FPGA Computing -- A Hardware Analysis of Twisted Edwards Curves for an Elliptic Curve Cryptosystem -- A Seamless Virtualization Approach for Transparent Dynamical Function Mapping Targeting Heterogeneous and Reconfigurable Systems -- Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator -- ACCFS – Operating System Integration of Computational Accelerators Using a VFS Approach -- A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms. |
| Record Nr. | UNINA-9910484388003321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||