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The designer's guide to VHDL / / Peter J. Ashenden
| The designer's guide to VHDL / / Peter J. Ashenden |
| Autore | Ashenden Peter J |
| Edizione | [3rd ed.] |
| Pubbl/distr/stampa | Amsterdam : , : Morgan Kaufmann Publishers, , [2008] |
| Descrizione fisica | 1 online resource (933 pages) |
| Disciplina | 621.39/2 |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
VHDL (Computer hardware description language)
Electronic digital computers - Computer simulation |
| ISBN |
1-282-28512-2
9786612285127 0-08-056885-8 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; The Designer's Guide to VHDL; Copyright Page; Contents; Preface; Chapter 1. Fundamental Concepts; 1.1 Modeling Digital Systems; 1.2 Domains and Levels of Modeling; 1.3 Modeling Languages; 1.4 VHDL Modeling Concepts; 1.5 Learning a New Language: Lexical Elements and Syntax; Exercises; Chapter 2. Scalar Data Types and Operations; 2.1 Constants and Variables; 2.2 Scalar Types; 2.3 Type Classification; 2.4 Attributes of Scalar Types; 2.5 Expressions and Predefined Operations; Exercises; Chapter 3. Sequential Statements; 3.1 If Statements; 3.2 Case Statements; 3.3 Null Statements
3.4 Loop Statements3.5 Assertion and Report Statements; Exercises; Chapter 4. Composite Data Types and Operations; 4.1 Arrays; 4.2 Unconstrained Array Types; 4.3 Array Operations and Referencing; 4.4 Records; Exercises; Chapter 5. Basic Modeling Constructs; 5.1 Entity Declarations and Architecture Bodies; 5.2 Behavioral Descriptions; 5.3 Structural Descriptions; 5.4 Design Processing; Exercises; Chapter 6. Subprograms; 6.1 Procedures; 6.2 Procedure Parameters; 6.3 Concurrent Procedure Call Statements; 6.4 Functions; 6.5 Overloading; 6.6 Visibility of Declarations; Exercises Chapter 7. Packages and Use Clauses7.1 Package Declarations; 7.2 Package Bodies; 7.3 Use Clauses; Exercises; Chapter 8. Resolved Signals; 8.1 Basic Resolved Signals; 8.2 Resolved Signals, Ports, and Parameters; Exercises; Chapter 9. Predefined and Standard Packages; 9.1 The Predefined Packages standard and env; 9.2 IEEE Standard Packages; Exercises; Chapter 10 Case Study: A Pipelined Multiplier Accumulator; 10.1 Algorithm Outline; 10.2 A Behavioral Model; 10.3 A Register-Transfer-Level Model; Exercises; Chapter 11. Aliases; 11.1 Aliases for Data Objects; 11.2 Aliases for Non-Data Items ExercisesChapter 12. Generics; 12.1 Generic Constants; 12.2 Generic Types; 12.3 Generic Lists in Packages; 12.4 Generic Lists in Subprograms; 12.5 Generic Subprograms; 12.6 Generic Packages; Exercises; Chapter 13. Components and Configurations; 13.1 Components; 13.2 Configuring Component Instances; 13.3 Configuration Specifications; Exercises; Chapter 14. Generate Statements; 14.1 Generating Iterative Structures; 14.2 Conditionally Generating Structures; 14.3 Configuration of Generate Statements; Exercises; Chapter 15. Access Types; 15.1 Access Types; 15.2 Linked Data Structures 15.3 An Ordered-Dictionary ADT Using Access TypesExercises; Chapter 16. Files and Input/Output; 16.1 Files; 16.2 The Package Textio; Exercises; Chapter 17. Case Study: A Package for Memories; 17.1 The Memories Package; 17.2 Using the Memories Package; Exercises; Chapter 18. Test Bench and Verification Features; 18.1 External Names; 18.2 Force and Release Assignments; 18.3 Embedded PSL in VHDL; Exercises; Chapter 19. Shared Variables and Protected Types; 19.1 Shared Variables and Mutual Exclusion; 19.2 Uninstantiated Methods in Protected Types; Exercises; Chapter 20. Attributes and Groups 20.1 Predefined Attributes |
| Record Nr. | UNINA-9910453430103321 |
Ashenden Peter J
|
||
| Amsterdam : , : Morgan Kaufmann Publishers, , [2008] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
The designer's guide to VHDL / / Peter J. Ashenden
| The designer's guide to VHDL / / Peter J. Ashenden |
| Autore | Ashenden Peter J |
| Edizione | [3rd ed.] |
| Pubbl/distr/stampa | Amsterdam : , : Morgan Kaufmann Publishers, , [2008] |
| Descrizione fisica | 1 online resource (933 pages) |
| Disciplina | 621.39/2 |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
VHDL (Computer hardware description language)
Electronic digital computers - Computer simulation |
| ISBN |
1-282-28512-2
9786612285127 0-08-056885-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; The Designer's Guide to VHDL; Copyright Page; Contents; Preface; Chapter 1. Fundamental Concepts; 1.1 Modeling Digital Systems; 1.2 Domains and Levels of Modeling; 1.3 Modeling Languages; 1.4 VHDL Modeling Concepts; 1.5 Learning a New Language: Lexical Elements and Syntax; Exercises; Chapter 2. Scalar Data Types and Operations; 2.1 Constants and Variables; 2.2 Scalar Types; 2.3 Type Classification; 2.4 Attributes of Scalar Types; 2.5 Expressions and Predefined Operations; Exercises; Chapter 3. Sequential Statements; 3.1 If Statements; 3.2 Case Statements; 3.3 Null Statements
3.4 Loop Statements3.5 Assertion and Report Statements; Exercises; Chapter 4. Composite Data Types and Operations; 4.1 Arrays; 4.2 Unconstrained Array Types; 4.3 Array Operations and Referencing; 4.4 Records; Exercises; Chapter 5. Basic Modeling Constructs; 5.1 Entity Declarations and Architecture Bodies; 5.2 Behavioral Descriptions; 5.3 Structural Descriptions; 5.4 Design Processing; Exercises; Chapter 6. Subprograms; 6.1 Procedures; 6.2 Procedure Parameters; 6.3 Concurrent Procedure Call Statements; 6.4 Functions; 6.5 Overloading; 6.6 Visibility of Declarations; Exercises Chapter 7. Packages and Use Clauses7.1 Package Declarations; 7.2 Package Bodies; 7.3 Use Clauses; Exercises; Chapter 8. Resolved Signals; 8.1 Basic Resolved Signals; 8.2 Resolved Signals, Ports, and Parameters; Exercises; Chapter 9. Predefined and Standard Packages; 9.1 The Predefined Packages standard and env; 9.2 IEEE Standard Packages; Exercises; Chapter 10 Case Study: A Pipelined Multiplier Accumulator; 10.1 Algorithm Outline; 10.2 A Behavioral Model; 10.3 A Register-Transfer-Level Model; Exercises; Chapter 11. Aliases; 11.1 Aliases for Data Objects; 11.2 Aliases for Non-Data Items ExercisesChapter 12. Generics; 12.1 Generic Constants; 12.2 Generic Types; 12.3 Generic Lists in Packages; 12.4 Generic Lists in Subprograms; 12.5 Generic Subprograms; 12.6 Generic Packages; Exercises; Chapter 13. Components and Configurations; 13.1 Components; 13.2 Configuring Component Instances; 13.3 Configuration Specifications; Exercises; Chapter 14. Generate Statements; 14.1 Generating Iterative Structures; 14.2 Conditionally Generating Structures; 14.3 Configuration of Generate Statements; Exercises; Chapter 15. Access Types; 15.1 Access Types; 15.2 Linked Data Structures 15.3 An Ordered-Dictionary ADT Using Access TypesExercises; Chapter 16. Files and Input/Output; 16.1 Files; 16.2 The Package Textio; Exercises; Chapter 17. Case Study: A Package for Memories; 17.1 The Memories Package; 17.2 Using the Memories Package; Exercises; Chapter 18. Test Bench and Verification Features; 18.1 External Names; 18.2 Force and Release Assignments; 18.3 Embedded PSL in VHDL; Exercises; Chapter 19. Shared Variables and Protected Types; 19.1 Shared Variables and Mutual Exclusion; 19.2 Uninstantiated Methods in Protected Types; Exercises; Chapter 20. Attributes and Groups 20.1 Predefined Attributes |
| Record Nr. | UNINA-9910782360203321 |
|
Ashenden Peter J
|
||
| Amsterdam : , : Morgan Kaufmann Publishers, , [2008] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
The designer's guide to VHDL / / Peter J. Ashenden
| The designer's guide to VHDL / / Peter J. Ashenden |
| Autore | Ashenden Peter J |
| Edizione | [3rd ed.] |
| Pubbl/distr/stampa | Amsterdam : , : Morgan Kaufmann Publishers, , [2008] |
| Descrizione fisica | 1 online resource (933 pages) |
| Disciplina | 621.39/2 |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
VHDL (Computer hardware description language)
Electronic digital computers - Computer simulation |
| ISBN |
1-282-28512-2
9786612285127 0-08-056885-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; The Designer's Guide to VHDL; Copyright Page; Contents; Preface; Chapter 1. Fundamental Concepts; 1.1 Modeling Digital Systems; 1.2 Domains and Levels of Modeling; 1.3 Modeling Languages; 1.4 VHDL Modeling Concepts; 1.5 Learning a New Language: Lexical Elements and Syntax; Exercises; Chapter 2. Scalar Data Types and Operations; 2.1 Constants and Variables; 2.2 Scalar Types; 2.3 Type Classification; 2.4 Attributes of Scalar Types; 2.5 Expressions and Predefined Operations; Exercises; Chapter 3. Sequential Statements; 3.1 If Statements; 3.2 Case Statements; 3.3 Null Statements
3.4 Loop Statements3.5 Assertion and Report Statements; Exercises; Chapter 4. Composite Data Types and Operations; 4.1 Arrays; 4.2 Unconstrained Array Types; 4.3 Array Operations and Referencing; 4.4 Records; Exercises; Chapter 5. Basic Modeling Constructs; 5.1 Entity Declarations and Architecture Bodies; 5.2 Behavioral Descriptions; 5.3 Structural Descriptions; 5.4 Design Processing; Exercises; Chapter 6. Subprograms; 6.1 Procedures; 6.2 Procedure Parameters; 6.3 Concurrent Procedure Call Statements; 6.4 Functions; 6.5 Overloading; 6.6 Visibility of Declarations; Exercises Chapter 7. Packages and Use Clauses7.1 Package Declarations; 7.2 Package Bodies; 7.3 Use Clauses; Exercises; Chapter 8. Resolved Signals; 8.1 Basic Resolved Signals; 8.2 Resolved Signals, Ports, and Parameters; Exercises; Chapter 9. Predefined and Standard Packages; 9.1 The Predefined Packages standard and env; 9.2 IEEE Standard Packages; Exercises; Chapter 10 Case Study: A Pipelined Multiplier Accumulator; 10.1 Algorithm Outline; 10.2 A Behavioral Model; 10.3 A Register-Transfer-Level Model; Exercises; Chapter 11. Aliases; 11.1 Aliases for Data Objects; 11.2 Aliases for Non-Data Items ExercisesChapter 12. Generics; 12.1 Generic Constants; 12.2 Generic Types; 12.3 Generic Lists in Packages; 12.4 Generic Lists in Subprograms; 12.5 Generic Subprograms; 12.6 Generic Packages; Exercises; Chapter 13. Components and Configurations; 13.1 Components; 13.2 Configuring Component Instances; 13.3 Configuration Specifications; Exercises; Chapter 14. Generate Statements; 14.1 Generating Iterative Structures; 14.2 Conditionally Generating Structures; 14.3 Configuration of Generate Statements; Exercises; Chapter 15. Access Types; 15.1 Access Types; 15.2 Linked Data Structures 15.3 An Ordered-Dictionary ADT Using Access TypesExercises; Chapter 16. Files and Input/Output; 16.1 Files; 16.2 The Package Textio; Exercises; Chapter 17. Case Study: A Package for Memories; 17.1 The Memories Package; 17.2 Using the Memories Package; Exercises; Chapter 18. Test Bench and Verification Features; 18.1 External Names; 18.2 Force and Release Assignments; 18.3 Embedded PSL in VHDL; Exercises; Chapter 19. Shared Variables and Protected Types; 19.1 Shared Variables and Mutual Exclusion; 19.2 Uninstantiated Methods in Protected Types; Exercises; Chapter 20. Attributes and Groups 20.1 Predefined Attributes |
| Record Nr. | UNINA-9910819469703321 |
|
Ashenden Peter J
|
||
| Amsterdam : , : Morgan Kaufmann Publishers, , [2008] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Digital design [[electronic resource] ] : an embedded systems approach using Verilog / / Peter J. Ashenden
| Digital design [[electronic resource] ] : an embedded systems approach using Verilog / / Peter J. Ashenden |
| Autore | Ashenden Peter J |
| Pubbl/distr/stampa | Burlington, : Morgan Kaufmann |
| Descrizione fisica | 1 online resource (579 p.) |
| Disciplina | 621.39/16 |
| Soggetto topico |
Embedded computer systems
Verilog (Computer hardware description language) System design |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-283-39612-2
9786613396129 0-08-055311-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Front Cover |
| Record Nr. | UNINA-9910456637203321 |
|
Ashenden Peter J
|
||
| Burlington, : Morgan Kaufmann | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Digital design [[electronic resource] ] : an embedded systems approach using VHDL / / Peter J. Ashenden
| Digital design [[electronic resource] ] : an embedded systems approach using VHDL / / Peter J. Ashenden |
| Autore | Ashenden Peter J |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier/Morgan Kaufmann Publishers, c2008 |
| Descrizione fisica | 1 online resource (595 p.) |
| Disciplina | 621.39/16 |
| Soggetto topico |
Embedded computer systems
VHDL (Computer hardware description language) System design |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-283-39613-0
9786613396136 0-08-055312-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Front Cover |
| Record Nr. | UNINA-9910457871203321 |
|
Ashenden Peter J
|
||
| Amsterdam ; ; Boston, : Elsevier/Morgan Kaufmann Publishers, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Digital design [[electronic resource] ] : an embedded systems approach using Verilog / / Peter J. Ashenden
| Digital design [[electronic resource] ] : an embedded systems approach using Verilog / / Peter J. Ashenden |
| Autore | Ashenden Peter J |
| Pubbl/distr/stampa | Burlington, : Morgan Kaufmann |
| Descrizione fisica | 1 online resource (579 p.) |
| Disciplina | 621.39/16 |
| Soggetto topico |
Embedded computer systems
Verilog (Computer hardware description language) System design |
| ISBN |
1-283-39612-2
9786613396129 0-08-055311-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Front Cover |
| Record Nr. | UNINA-9910780787103321 |
|
Ashenden Peter J
|
||
| Burlington, : Morgan Kaufmann | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Digital design [[electronic resource] ] : an embedded systems approach using VHDL / / Peter J. Ashenden
| Digital design [[electronic resource] ] : an embedded systems approach using VHDL / / Peter J. Ashenden |
| Autore | Ashenden Peter J |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier/Morgan Kaufmann Publishers, c2008 |
| Descrizione fisica | 1 online resource (595 p.) |
| Disciplina | 621.39/16 |
| Soggetto topico |
Embedded computer systems
VHDL (Computer hardware description language) System design |
| ISBN |
1-283-39613-0
9786613396136 0-08-055312-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Front Cover |
| Record Nr. | UNINA-9910778938603321 |
|
Ashenden Peter J
|
||
| Amsterdam ; ; Boston, : Elsevier/Morgan Kaufmann Publishers, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Digital design [[electronic resource] ] : an embedded systems approach using VHDL / / Peter J. Ashenden
| Digital design [[electronic resource] ] : an embedded systems approach using VHDL / / Peter J. Ashenden |
| Autore | Ashenden Peter J |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier/Morgan Kaufmann Publishers, c2008 |
| Descrizione fisica | 1 online resource (595 p.) |
| Disciplina | 621.39/16 |
| Soggetto topico |
Embedded computer systems
VHDL (Computer hardware description language) System design |
| ISBN |
1-283-39613-0
9786613396136 0-08-055312-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Front Cover |
| Record Nr. | UNINA-9910807197803321 |
|
Ashenden Peter J
|
||
| Amsterdam ; ; Boston, : Elsevier/Morgan Kaufmann Publishers, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Digital design [[electronic resource] ] : an embedded systems approach using Verilog / / Peter J. Ashenden
| Digital design [[electronic resource] ] : an embedded systems approach using Verilog / / Peter J. Ashenden |
| Autore | Ashenden Peter J |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Burlington, : Morgan Kaufmann |
| Descrizione fisica | 1 online resource (579 p.) |
| Disciplina | 621.39/16 |
| Soggetto topico |
Embedded computer systems
Verilog (Computer hardware description language) System design |
| ISBN |
1-283-39612-2
9786613396129 0-08-055311-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Front Cover |
| Record Nr. | UNINA-9910827843003321 |
|
Ashenden Peter J
|
||
| Burlington, : Morgan Kaufmann | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
VHDL-2008 [[electronic resource] ] : just the new stuff / / Peter J. Ashenden, Jim Lewis
| VHDL-2008 [[electronic resource] ] : just the new stuff / / Peter J. Ashenden, Jim Lewis |
| Autore | Ashenden Peter J |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier/Morgan Kaufmann, c2008 |
| Descrizione fisica | 1 online resource (255 p.) |
| Disciplina | 621.39/2 |
| Altri autori (Persone) | LewisJim <1962-> |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico | VHDL (Computer hardware description language) |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-281-17213-8
9786611172138 0-08-055757-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; VHDL-2008: Just the New Stuff; Copyright Page; Contents; Preface; Chapter 1. Enhanced Generics; 1.1 Generic Types; 1.2 Generic Lists in Packages; 1.3 Local Packages; 1.4 Generic Lists in Subprograms; 1.5 Generic Subprograms; 1.6 Generic Packages; 1.7 Use Case: Generic Memories; Chapter 2. Other Major Features; 2.1 External Names; 2.2 Force and Release; 2.3 Context Declarations; 2.4 Integrated PSL; 2.5 IP Encryption; 2.6 VHDL Procedural Interface (VHPI); Chapter 3. Type System Changes; 3.1 Unconstrained Element Types; 3.2 Resolved Elements; Chapter 4. New and Changed Operations
4.1 Array/Scalar Logical Operations 4.2 Array/Scalar Addition Operators; 4.3 Logical Reduction Operators; 4.4 Condition Operator; 4.5 Matching Relational Operators; 4.6 Maximum and Minimum; 4.7 Mod and Rem for Physical Types; 4.8 Shift Operations; 4.9 Strength Reduction and 'X' Detection; Chapter 5. New and Changed Statements; 5.1 Conditional and Selected Assignments; 5.2 Matching Case Statements; 5.3 If and Case Generate; Chapter 6. Modeling Enhancements; 6.1 Signal Expressions in Port Maps; 6.2 All Signals in Sensitivity List; 6.3 Reading Out-Mode Ports and Parameters 6.4 Slices in Aggregates 6.5 Bit-String Literals; Chapter 7. Improved I/O; 7.1 The To_string Functions; 7.2 The Justify Function; 7.3 Newline Formatting; 7.4 Read and Write Operations; 7.5 The Tee Procedure; 7.6 The Flush Procedure; Chapter 8. Standard Packages; 8.1 The Std_logic_1164 Package; 8.2 The Numeric_bit and Numeric_std Packages; 8.3 The Numeric Unsigned Packages; 8.4 The Fixed-Point Math Packages; 8.5 The Floating-Point Math Packages; 8.6 The Standard Package; 8.7 The Env Package; 8.8 Operator Overloading Summary; 8.9 Conversion Function Summary 8.10 Strength Reduction Function Summary Chapter 9. Miscellaneous Changes; 9.1 Referencing Generics in Generic Lists; 9.2 Function Return Subtype; 9.3 Qualified Expression Subtype; 9.4 Type Conversions; 9.5 Case Expression Subtype; 9.6 Subtypes for Port and Parameter Actuals; 9.7 Static Composite Expressions; 9.8 Static Ranges; 9.9 Use Clauses, Types, and Operations; 9.10 Hiding of Implicit Operations; 9.11 Multidimensional Array Alias; 9.12 Others in Aggregates; 9.13 Attribute Specifications in Package Bodies; 9.14 Attribute Specification for Overloaded Subprograms 9.15 Integer Expressions in Range Bounds 9.16 Action on Assertion Violations; 9.17 'Path_Name and 'Instance_Name; 9.18 Non-Nesting of Architecture Region; 9.19 Purity of Now; 9.20 Delimited Comments; 9.21 Tool Directives; 9.22 New Reserved Words; 9.23 Replacement Characters; Chapter 10. What's Next; 10.1 Object-Oriented Class Types; 10.2 Randomization; 10.3 Functional Coverage; 10.4 Alternatives; 10.5 Getting Involved; Index |
| Record Nr. | UNINA-9910450682303321 |
|
Ashenden Peter J
|
||
| Amsterdam ; ; Boston, : Elsevier/Morgan Kaufmann, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
