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Designer's guide to the Cypress PSoC [[electronic resource] /] / by Robert Ashby
| Designer's guide to the Cypress PSoC [[electronic resource] /] / by Robert Ashby |
| Autore | Ashby Robert |
| Pubbl/distr/stampa | Boston, : Elsevier, 2005 |
| Descrizione fisica | 1 online resource (273 p.) |
| Disciplina | 004.6 |
| Collana | Embedded Technology |
| Soggetto topico |
Systems on a chip - Design and construction
Embedded computer systems |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-281-00985-7
9786611009854 1-4237-4245-1 0-08-047714-3 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front cover; Designer's Guideto the Cypress PSoCTM; Contents; Foreword; Acknowledgments; What's New with PSoC?; What's on the CD-ROM?; Introduction to Microcontroller Basics; What is a Microcontroller?; What About Peripherals?; What's in the CPU?; What Can a Microcontroller Do?; How Does a Microcontroller Work?; A Little Bit About Numbers; Basic Logic; Instructions and Data Handling; Addressing Methods; A Little Bit About Paging; More Information; CHAPTER 1: Why Use the Cypress PSoC?; Notable Qualities of the PSoC Family; My Experience with the PSoC Family; Getting Over Those Speed Bumps
A True System on a ChipA Work in Progress; CHAPTER 2: Structure of the PSoC; M8C Core; Oscillator; RAM Organization; Supervisory ROM; Interrupt Controller; General-Purpose I/O; Analog I/O; Digital and Analog Programmable Blocks; CHAPTER 3: PSoC Designer; Device Editor; Application Editor; Debugger; CHAPTER 4: Limitations of the PSoC; Analog Limitations; Digital Limitations; Interconnects on the Newer Parts; CHAPTER 5: Improvements of the PSoC; Analog Improvements; Improved Interconnects; LUTs in Key Locations; CHAPTER 6: PSoC Modules; Analog-to-Digital Converters (ADCs); Amplifiers Analog CommCounters; DACs; Digital Comm; Filters; Generic; Miscellaneous Digital; MUXs; PWMs; Random Sequence; Temperature; Timers; CHAPTER 7 :Interconnects; 25xxx/26xxx Interconnection System; 22xxx/24xxx/27xxx/29xxx Interconnection System; Analog Interconnects; CHAPTER 8: PSoC Memory Management; Areas; Where Does My RAM Go?; CHAPTER 9: Multiple Configurations; LoadConfigInit; LoadConfig_ProjectName; UnloadConfig_multipleconfig; ReloadConfig_multipleconfig; LoadConfig_Config1; UnloadConfig_Config1; LoadConfig_Config2; UnloadConfig_Config2; UnloadConfig_Total; NO_SHADOW CHAPTER 10: Project PruningOptions Within PSoC Designer; Sublimation; Configuration Initialization Type; Design Practices; Other Common Practices; CHAPTER 11: Design Tips; Working with Data Sheets; Shortcut Keys and Navigation Within PSoC Designer; One Project for Multiple Parts; Versions; PSoC Designer Versions; Saving Space; Boot.asm File; Temporary Removal of Routines; Control Systems; Bit Manipulation; CHAPTER 12: PSoC Express; Design; Simulation; Build; Program; Other Transfer Functions; Making a Stimulus File; What is Really Being Done in the Background?; The Valuator and Interface The Future of PSoC ExpressAPPENDIX A: Global Resources; CPU Clock; APPENDIXA; 32K_Select; PLL_Mode; Sleep_Timer; VC1 (24V1=24MHz/N); VC2 (24V2=24V1/N); Analog Power; Ref Mux; Op-Amp Bias; A_Buff_Power; Switch Mode Pump; Trip Voltage[LVD (SMP)]; Supply Voltage; Watchdog Enable; APPENDIX B: Project Walkthrough; Setting Up the Project; User Module Selection View; Interconnect View; Application Editor; Project File Sections; Some Important Files; Variable Declaration; Constant Declarations; Timer Interrupt; Main.asm; Building the Project; Goals of This Exercise; APPENDIX C: Limited Analog System About the Author |
| Altri titoli varianti | Designer's guide to the Cypress programmable system on a chip |
| Record Nr. | UNINA-9910457074203321 |
Ashby Robert
|
||
| Boston, : Elsevier, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Designer's guide to the Cypress PSoC [[electronic resource] /] / by Robert Ashby
| Designer's guide to the Cypress PSoC [[electronic resource] /] / by Robert Ashby |
| Autore | Ashby Robert |
| Pubbl/distr/stampa | Boston, : Elsevier, 2005 |
| Descrizione fisica | 1 online resource (273 p.) |
| Disciplina | 004.6 |
| Collana | Embedded Technology |
| Soggetto topico |
Systems on a chip - Design and construction
Embedded computer systems |
| ISBN |
1-281-00985-7
9786611009854 1-4237-4245-1 0-08-047714-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front cover; Designer's Guideto the Cypress PSoCTM; Contents; Foreword; Acknowledgments; What's New with PSoC?; What's on the CD-ROM?; Introduction to Microcontroller Basics; What is a Microcontroller?; What About Peripherals?; What's in the CPU?; What Can a Microcontroller Do?; How Does a Microcontroller Work?; A Little Bit About Numbers; Basic Logic; Instructions and Data Handling; Addressing Methods; A Little Bit About Paging; More Information; CHAPTER 1: Why Use the Cypress PSoC?; Notable Qualities of the PSoC Family; My Experience with the PSoC Family; Getting Over Those Speed Bumps
A True System on a ChipA Work in Progress; CHAPTER 2: Structure of the PSoC; M8C Core; Oscillator; RAM Organization; Supervisory ROM; Interrupt Controller; General-Purpose I/O; Analog I/O; Digital and Analog Programmable Blocks; CHAPTER 3: PSoC Designer; Device Editor; Application Editor; Debugger; CHAPTER 4: Limitations of the PSoC; Analog Limitations; Digital Limitations; Interconnects on the Newer Parts; CHAPTER 5: Improvements of the PSoC; Analog Improvements; Improved Interconnects; LUTs in Key Locations; CHAPTER 6: PSoC Modules; Analog-to-Digital Converters (ADCs); Amplifiers Analog CommCounters; DACs; Digital Comm; Filters; Generic; Miscellaneous Digital; MUXs; PWMs; Random Sequence; Temperature; Timers; CHAPTER 7 :Interconnects; 25xxx/26xxx Interconnection System; 22xxx/24xxx/27xxx/29xxx Interconnection System; Analog Interconnects; CHAPTER 8: PSoC Memory Management; Areas; Where Does My RAM Go?; CHAPTER 9: Multiple Configurations; LoadConfigInit; LoadConfig_ProjectName; UnloadConfig_multipleconfig; ReloadConfig_multipleconfig; LoadConfig_Config1; UnloadConfig_Config1; LoadConfig_Config2; UnloadConfig_Config2; UnloadConfig_Total; NO_SHADOW CHAPTER 10: Project PruningOptions Within PSoC Designer; Sublimation; Configuration Initialization Type; Design Practices; Other Common Practices; CHAPTER 11: Design Tips; Working with Data Sheets; Shortcut Keys and Navigation Within PSoC Designer; One Project for Multiple Parts; Versions; PSoC Designer Versions; Saving Space; Boot.asm File; Temporary Removal of Routines; Control Systems; Bit Manipulation; CHAPTER 12: PSoC Express; Design; Simulation; Build; Program; Other Transfer Functions; Making a Stimulus File; What is Really Being Done in the Background?; The Valuator and Interface The Future of PSoC ExpressAPPENDIX A: Global Resources; CPU Clock; APPENDIXA; 32K_Select; PLL_Mode; Sleep_Timer; VC1 (24V1=24MHz/N); VC2 (24V2=24V1/N); Analog Power; Ref Mux; Op-Amp Bias; A_Buff_Power; Switch Mode Pump; Trip Voltage[LVD (SMP)]; Supply Voltage; Watchdog Enable; APPENDIX B: Project Walkthrough; Setting Up the Project; User Module Selection View; Interconnect View; Application Editor; Project File Sections; Some Important Files; Variable Declaration; Constant Declarations; Timer Interrupt; Main.asm; Building the Project; Goals of This Exercise; APPENDIX C: Limited Analog System About the Author |
| Altri titoli varianti | Designer's guide to the Cypress programmable system on a chip |
| Record Nr. | UNINA-9910784361303321 |
|
Ashby Robert
|
||
| Boston, : Elsevier, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Designer's guide to the Cypress PSoC / / by Robert Ashby
| Designer's guide to the Cypress PSoC / / by Robert Ashby |
| Autore | Ashby Robert |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Boston, : Elsevier, 2005 |
| Descrizione fisica | 1 online resource (273 p.) |
| Disciplina |
004.6
004.16 |
| Collana | Embedded Technology |
| Soggetto topico |
Systems on a chip - Design and construction
Embedded computer systems |
| ISBN |
1-281-00985-7
9786611009854 1-4237-4245-1 0-08-047714-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front cover; Designer's Guideto the Cypress PSoCTM; Contents; Foreword; Acknowledgments; What's New with PSoC?; What's on the CD-ROM?; Introduction to Microcontroller Basics; What is a Microcontroller?; What About Peripherals?; What's in the CPU?; What Can a Microcontroller Do?; How Does a Microcontroller Work?; A Little Bit About Numbers; Basic Logic; Instructions and Data Handling; Addressing Methods; A Little Bit About Paging; More Information; CHAPTER 1: Why Use the Cypress PSoC?; Notable Qualities of the PSoC Family; My Experience with the PSoC Family; Getting Over Those Speed Bumps
A True System on a ChipA Work in Progress; CHAPTER 2: Structure of the PSoC; M8C Core; Oscillator; RAM Organization; Supervisory ROM; Interrupt Controller; General-Purpose I/O; Analog I/O; Digital and Analog Programmable Blocks; CHAPTER 3: PSoC Designer; Device Editor; Application Editor; Debugger; CHAPTER 4: Limitations of the PSoC; Analog Limitations; Digital Limitations; Interconnects on the Newer Parts; CHAPTER 5: Improvements of the PSoC; Analog Improvements; Improved Interconnects; LUTs in Key Locations; CHAPTER 6: PSoC Modules; Analog-to-Digital Converters (ADCs); Amplifiers Analog CommCounters; DACs; Digital Comm; Filters; Generic; Miscellaneous Digital; MUXs; PWMs; Random Sequence; Temperature; Timers; CHAPTER 7 :Interconnects; 25xxx/26xxx Interconnection System; 22xxx/24xxx/27xxx/29xxx Interconnection System; Analog Interconnects; CHAPTER 8: PSoC Memory Management; Areas; Where Does My RAM Go?; CHAPTER 9: Multiple Configurations; LoadConfigInit; LoadConfig_ProjectName; UnloadConfig_multipleconfig; ReloadConfig_multipleconfig; LoadConfig_Config1; UnloadConfig_Config1; LoadConfig_Config2; UnloadConfig_Config2; UnloadConfig_Total; NO_SHADOW CHAPTER 10: Project PruningOptions Within PSoC Designer; Sublimation; Configuration Initialization Type; Design Practices; Other Common Practices; CHAPTER 11: Design Tips; Working with Data Sheets; Shortcut Keys and Navigation Within PSoC Designer; One Project for Multiple Parts; Versions; PSoC Designer Versions; Saving Space; Boot.asm File; Temporary Removal of Routines; Control Systems; Bit Manipulation; CHAPTER 12: PSoC Express; Design; Simulation; Build; Program; Other Transfer Functions; Making a Stimulus File; What is Really Being Done in the Background?; The Valuator and Interface The Future of PSoC ExpressAPPENDIX A: Global Resources; CPU Clock; APPENDIXA; 32K_Select; PLL_Mode; Sleep_Timer; VC1 (24V1=24MHz/N); VC2 (24V2=24V1/N); Analog Power; Ref Mux; Op-Amp Bias; A_Buff_Power; Switch Mode Pump; Trip Voltage[LVD (SMP)]; Supply Voltage; Watchdog Enable; APPENDIX B: Project Walkthrough; Setting Up the Project; User Module Selection View; Interconnect View; Application Editor; Project File Sections; Some Important Files; Variable Declaration; Constant Declarations; Timer Interrupt; Main.asm; Building the Project; Goals of This Exercise; APPENDIX C: Limited Analog System About the Author |
| Altri titoli varianti | Designer's guide to the Cypress programmable system on a chip |
| Record Nr. | UNINA-9910815972503321 |
|
Ashby Robert
|
||
| Boston, : Elsevier, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||