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Fundamentals of Computer Organization and Architecture [[electronic resource]]
Fundamentals of Computer Organization and Architecture [[electronic resource]]
Autore Abd-El-Barr Mostafa
Pubbl/distr/stampa Hoboken, : Wiley, 2005
Descrizione fisica 1 online resource (289 p.)
Disciplina 004.2/2
004.22
004/.35
Altri autori (Persone) El-RewiniHesham
Collana Wiley Series on Parallel and Distributed Computing
Soggetto topico Computer architecture
Parallel processing (Electronic computers)
Engineering & Applied Sciences
Computer Science
Soggetto genere / forma Electronic books.
ISBN 1-280-25238-3
9786610252381
0-470-32195-4
0-471-47833-4
0-471-47832-6
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto FUNDAMENTALS OF COMPUTER ORGANIZATION AND ARCHITECTURE; CONTENTS; Preface; 1. Introduction to Computer Systems; 1.1. Historical Background; 1.2. Architectural Development and Styles; 1.3. Technological Development; 1.4. Performance Measures; 1.5. Summary; Exercises; References and Further Reading; 2. Instruction Set Architecture and Design; 2.1. Memory Locations and Operations; 2.2. Addressing Modes; 2.3. Instruction Types; 2.4. Programming Examples; 2.5. Summary; Exercises; References and Further Reading; 3. Assembly Language Programming; 3.1. A Simple Machine
3.2. Instructions Mnemonics and Syntax3.3. Assembler Directives and Commands; 3.4. Assembly and Execution of Programs; 3.5. Example: The X86 Family; 3.6. Summary; Exercises; References and Further Reading; 4. Computer Arithmetic; 4.1. Number Systems; 4.2. Integer Arithmetic; 4.3 Floating-Point Arithmetic; 4.4 Summary; Exercises; References and Further Reading; 5. Processing Unit Design; 5.1. CPU Basics; 5.2. Register Set; 5.3. Datapath; 5.4. CPU Instruction Cycle; 5.5. Control Unit; 5.6. Summary; Exercises; References; 6. Memory System Design I; 6.1. Basic Concepts; 6.2. Cache Memory
6.3. SummaryExercises; References and Further Reading; 7. Memory System Design II; 7.1. Main Memory; 7.2. Virtual Memory; 7.3. Read-Only Memory; 7.4. Summary; Exercises; References and Further Reading; 8. Input-Output Design and Organization; 8.1. Basic Concepts; 8.2. Programmed I/O; 8.3. Interrupt-Driven I/O; 8.4. Direct Memory Access (DMA); 8.5. Buses; 8.6. Input-Output Interfaces; 8.7. Summary; Exercises; References and Further Reading; 9 Pipelining Design Techniques; 9.1. General Concepts; 9.2. Instruction Pipeline; 9.3. Example Pipeline Processors; 9.4. Instruction-Level Parallelism
9.5. Arithmetic Pipeline9.6. Summary; Exercises; References and Further Reading; 10 Reduced Instruction Set Computers (RISCs); 10.1. RISC/CISC Evolution Cycle; 10.2. RISCs Design Principles; 10.3. Overlapped Register Windows; 10.4. RISCs Versus CISCs; 10.5. Pioneer (University) RISC Machines; 10.6. Example of Advanced RISC Machines; 10.7. Summary; Exercises; References and Further Reading; 11 Introduction to Multiprocessors; 11.1. Introduction; 11.2. Classification of Computer Architectures; 11.3. SIMD Schemes; 11.4. MIMD Schemes; 11.5. Interconnection Networks
11.6. Analysis and Performance Metrics11.7. Summary; Exercises; References and Further Reading; Index
Record Nr. UNINA-9910146056003321
Abd-El-Barr Mostafa  
Hoboken, : Wiley, 2005
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Fundamentals of Computer Organization and Architecture [[electronic resource]]
Fundamentals of Computer Organization and Architecture [[electronic resource]]
Autore Abd-El-Barr Mostafa
Edizione [1st ed.]
Pubbl/distr/stampa Hoboken, : Wiley, 2005
Descrizione fisica 1 online resource (289 p.)
Disciplina 004.2/2
004.22
004/.35
Altri autori (Persone) El-RewiniHesham
Collana Wiley Series on Parallel and Distributed Computing
Soggetto topico Computer architecture
Parallel processing (Electronic computers)
Engineering & Applied Sciences
Computer Science
ISBN 1-280-25238-3
9786610252381
0-470-32195-4
0-471-47833-4
0-471-47832-6
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto FUNDAMENTALS OF COMPUTER ORGANIZATION AND ARCHITECTURE; CONTENTS; Preface; 1. Introduction to Computer Systems; 1.1. Historical Background; 1.2. Architectural Development and Styles; 1.3. Technological Development; 1.4. Performance Measures; 1.5. Summary; Exercises; References and Further Reading; 2. Instruction Set Architecture and Design; 2.1. Memory Locations and Operations; 2.2. Addressing Modes; 2.3. Instruction Types; 2.4. Programming Examples; 2.5. Summary; Exercises; References and Further Reading; 3. Assembly Language Programming; 3.1. A Simple Machine
3.2. Instructions Mnemonics and Syntax3.3. Assembler Directives and Commands; 3.4. Assembly and Execution of Programs; 3.5. Example: The X86 Family; 3.6. Summary; Exercises; References and Further Reading; 4. Computer Arithmetic; 4.1. Number Systems; 4.2. Integer Arithmetic; 4.3 Floating-Point Arithmetic; 4.4 Summary; Exercises; References and Further Reading; 5. Processing Unit Design; 5.1. CPU Basics; 5.2. Register Set; 5.3. Datapath; 5.4. CPU Instruction Cycle; 5.5. Control Unit; 5.6. Summary; Exercises; References; 6. Memory System Design I; 6.1. Basic Concepts; 6.2. Cache Memory
6.3. SummaryExercises; References and Further Reading; 7. Memory System Design II; 7.1. Main Memory; 7.2. Virtual Memory; 7.3. Read-Only Memory; 7.4. Summary; Exercises; References and Further Reading; 8. Input-Output Design and Organization; 8.1. Basic Concepts; 8.2. Programmed I/O; 8.3. Interrupt-Driven I/O; 8.4. Direct Memory Access (DMA); 8.5. Buses; 8.6. Input-Output Interfaces; 8.7. Summary; Exercises; References and Further Reading; 9 Pipelining Design Techniques; 9.1. General Concepts; 9.2. Instruction Pipeline; 9.3. Example Pipeline Processors; 9.4. Instruction-Level Parallelism
9.5. Arithmetic Pipeline9.6. Summary; Exercises; References and Further Reading; 10 Reduced Instruction Set Computers (RISCs); 10.1. RISC/CISC Evolution Cycle; 10.2. RISCs Design Principles; 10.3. Overlapped Register Windows; 10.4. RISCs Versus CISCs; 10.5. Pioneer (University) RISC Machines; 10.6. Example of Advanced RISC Machines; 10.7. Summary; Exercises; References and Further Reading; 11 Introduction to Multiprocessors; 11.1. Introduction; 11.2. Classification of Computer Architectures; 11.3. SIMD Schemes; 11.4. MIMD Schemes; 11.5. Interconnection Networks
11.6. Analysis and Performance Metrics11.7. Summary; Exercises; References and Further Reading; Index
Record Nr. UNINA-9910819129403321
Abd-El-Barr Mostafa  
Hoboken, : Wiley, 2005
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui