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IEEE STD 1800-2009 : IEEE standard for SystemVerilog--unified hardware design, specification, and verification language / / Institute of Electrical and Electronics Engineers
| IEEE STD 1800-2009 : IEEE standard for SystemVerilog--unified hardware design, specification, and verification language / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | New York, New York : , : IEEE, , 2009 |
| Descrizione fisica | 1 online resource (1285 pages) |
| Disciplina | 621.392 |
| Collana | IEEE Std |
| Soggetto topico | Verilog (Computer hardware description language) |
| ISBN | 0-7381-6130-6 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | IEEE STD 1800-2009 |
| Record Nr. | UNISA-996280690003316 |
| New York, New York : , : IEEE, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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IEEE Std 1800-2012 (Revision of IEEE Std 1800-2009) : IEEE standard for SystemVerilog--unified hardware design, specification, and verification language / / Institute of Electrical and Electronics Engineers
| IEEE Std 1800-2012 (Revision of IEEE Std 1800-2009) : IEEE standard for SystemVerilog--unified hardware design, specification, and verification language / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : IEEE, , 2013 |
| Descrizione fisica | 1 online resource (xxxviii, 1275 pages) |
| Disciplina | 621.392 |
| Collana | IEEE Std |
| Soggetto topico | Verilog (Computer hardware description language) |
| ISBN | 0-7381-8110-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | IEEE Std 1800-2012 |
| Record Nr. | UNINA-9910135519103321 |
| Piscataway, New Jersey : , : IEEE, , 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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IEEE Std 1800-2012 (Revision of IEEE Std 1800-2009) : IEEE standard for SystemVerilog--unified hardware design, specification, and verification language / / Institute of Electrical and Electronics Engineers
| IEEE Std 1800-2012 (Revision of IEEE Std 1800-2009) : IEEE standard for SystemVerilog--unified hardware design, specification, and verification language / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : IEEE, , 2013 |
| Descrizione fisica | 1 online resource (xxxviii, 1275 pages) |
| Disciplina | 621.392 |
| Collana | IEEE Std |
| Soggetto topico | Verilog (Computer hardware description language) |
| ISBN | 0-7381-8110-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | IEEE Std 1800-2012 |
| Record Nr. | UNISA-996280690103316 |
| Piscataway, New Jersey : , : IEEE, , 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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A practical guide to Verilog-A : mastering the modeling language for analog devices, circuits, and systems / / Slobodan Mijalković
| A practical guide to Verilog-A : mastering the modeling language for analog devices, circuits, and systems / / Slobodan Mijalković |
| Autore | Mijalković Slobodan |
| Pubbl/distr/stampa | Berkeley, California : , : Apress L. P., , [2022] |
| Descrizione fisica | 1 online resource (340 pages) |
| Disciplina | 050 |
| Soggetto topico |
Analog electronic systems
Verilog (Computer hardware description language) |
| ISBN | 1-4842-6351-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Table of Contents -- About the Author -- About the Technical Reviewer -- Acknowledgments -- Introduction -- Chapter 1: Lexical Basis -- Character Set and Tokens -- Comments -- Identifiers -- Simple Identifiers -- Escaped Identifiers -- Hierarchical Names -- Reserved Words -- System Names -- Compiler Directives -- Numerical Literals -- Integer Literals -- Real Literals -- String Literals -- Operators -- Punctuators -- Chapter 2: Basic Types and Expressions -- Basic Types -- Integer Types -- Real Types -- String Types -- Expressions -- Primary Expressions -- Call Expressions -- Subscript Expressions -- Arithmetic Expressions -- Relational Expressions -- Logical Expressions -- Bitwise Expressions -- Conditional Expressions -- Concatenated Expressions -- Expression Evaluation Order -- Operator Precedence -- Parenthesized Expressions -- Short-Circuit Evaluation -- Expression Containers -- Assignment Patterns -- Ranges -- Chapter 3: Net-Discipline Types -- Defining Signal Natures -- Base Natures -- Derived Natures -- Predefined Natures -- Defining Net-Discipline Types -- Nature Binding Statements -- Domain Binding Statements -- Nature Override Statements -- Deriving Natures from Disciplines -- Discipline Compatibility -- Predefined Disciplines -- Net Declarations -- Scalar Nets -- Vector Nets -- Ground Nets -- Net Initialization -- Accessing Net Attributes -- Chapter 4: Modules and Ports -- Defining Module Connectivity -- Declaring Port Directions -- Declaring Port Types -- Connecting Modules by Instantiation -- Explicit Port Mapping -- Positional Port Mapping -- Top-Level Instantiation and root -- Implicit Nets -- Instantiation of SPICE Primitives -- Chapter 5: Parameters -- Parameter Declarations -- Simple Parameters -- Array Parameters -- Permissible Value Ranges -- Parameter Aliases -- Local Parameters -- Overriding Parameters.
Instance Parameter Override -- Parameter Override by Name -- Parameter Override by Order -- Hierarchical Parameter Override -- Hierarchical System Parameters -- Chapter 6: Paramsets -- Introducing Paramsets -- Defining Paramsets -- Paramset Parameters -- Parameter Override Statements -- Other Paramset Statements -- Paramset Instantiation -- Chapter 7: Procedural Programming -- Variables -- Simple Variables -- Array Variables -- Procedural Blocks -- Analog Blocks -- Block Procedural Statements -- Assignment Statements -- Scalar Assignments -- Array Assignments -- Conditional Statements -- if Statement -- case Statement -- Looping Statements -- while Statement -- for Statement -- repeat Statement -- Chapter 8: Branches -- Declaring Branches -- Scalar Branches -- Vector Branches -- Port Branches -- Branch Signals -- Signal Directions -- Signal Access Functions -- Unnamed Branches -- Contributing Branch Signals -- Direct Contribution Statements -- Indirect Contribution Statements -- Probe Branches -- Value Retention -- Switch Branches -- Chapter 9: Derivative and Integral Operators -- Time Derivative Operator -- Case Study: DC Motor -- Time Integrator Operator -- Case Study: Chemical Reaction System -- Circular Integrator Operator -- Case Study: Voltage-Controlled Oscillator -- Indirect Contribution Equations -- Case Study: Accelerometer -- Probe Derivative Operator -- Chapter 10: Built-In Math Functions -- Deterministic Functions -- Logarithmic and Power Functions -- Trigonometric Functions -- Hyperbolic Functions -- Limiting and Rounding Functions -- Probabilistic Functions -- Random Number Generation Function -- Statistical Distribution Functions -- Chapter 11: User-Defined Functions -- Defining Functions -- Formal Arguments -- A Return Variable -- A Procedural Statement -- Calling Functions -- Function References -- Using Functions in Expressions. Function Called As Statements -- Chapter 12: Lookup Tables -- Table Data Structure -- Jagged Array Grids -- Preparing Table Data -- Lookup Table Function -- Input Variables and Data Source -- Control String -- Chapter 13: Small-Signal Functions -- AC Analysis -- AC Stimulus Function -- Noise Analysis -- White Noise Function -- Flicker Noise Function -- Look-Up Table Noise Functions -- Correlated Noise Sources -- Chapter 14: Filters -- Time-Domain Filters -- Absolute Delay Filter -- Transition Filter -- Slew Filter -- Frequency-Domain Filters -- Laplace Transform Filters -- Zero-Pole Filter -- Zero-Denominator Filter -- Numerator-Pole Filter -- Numerator-Denominator Filter -- The Z-Transform Filters -- Zero-Pole Filter -- Zero-Denominator Filter -- Numerator-Pole Filter -- Numerator-Denominator Filter -- Chapter 15: Events -- Event Control Statements -- Global Event Functions -- Monitored Event Functions -- Cross Function -- Last Crossing Function -- Above Function -- Timer Function -- Chapter 16: Runtime Support -- Elaboration Queries -- Port Connections -- Parameter Overrides -- Simulation Queries -- Analysis Type -- Kernel Parameters -- Dynamic Probing -- Solver Support -- Announcing Discontinuity -- Bounding Time Step -- Limiting Iteration Steps -- Simulation Control -- Announcing Severity -- Terminating Simulation -- Chapter 17: Input and Output -- File Management -- Opening Files -- File Positioning -- Error Status -- Detecting End-of-File -- Flushing Output -- Closing Files -- Reading Data -- Reading a Line from a File -- Reading Formatted Data -- Displaying and Writing Data -- Text Output -- File Output -- Writing Data to a String -- Escape Sequences -- Chapter 18: Generative Programming -- Generate Blocks -- Generate Statements -- Generate Regions -- Conditional Generation -- Looping Generation -- Hierarchy Scope and Names. Order of Elaboration -- Chapter 19: Attributes -- Introducing Attributes -- Attribute Assignments -- Attribute Instances -- Standard Attributes -- Simulation Reports -- Output Variables -- Port Discipline Override -- Chapter 20: Compiler Directives -- File Inclusion -- Macro Definition -- Object-like Macros -- Function-like Macros -- Undefining Macros -- Predefined Macros -- Conditional Compilation -- Default Transition Directive -- Appendix -- Reserved Words in Verilog-A -- Keywords -- Other Reserved Words -- SPICE Compatibility -- Index. |
| Record Nr. | UNINA-9910595028803321 |
Mijalković Slobodan
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| Berkeley, California : , : Apress L. P., , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Proceedings of the ... International Verilog HDL Conference / / sponsored by Open Verilog International in cooperation with IEEE Computer Society
| Proceedings of the ... International Verilog HDL Conference / / sponsored by Open Verilog International in cooperation with IEEE Computer Society |
| Pubbl/distr/stampa | Los Alamitos, Calif., : IEEE Computer Society Press |
| Descrizione fisica | 1 online resource |
| Disciplina | 621.39/2 |
| Soggetto topico |
Verilog (Computer hardware description language)
VHDL (Computer hardware description language) |
| Soggetto genere / forma | Conference papers and proceedings. |
| Formato | Materiale a stampa |
| Livello bibliografico | Periodico |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
IEEE International Verilog HDL Conference
IVC Proceedings |
| Record Nr. | UNISA-996279335903316 |
| Los Alamitos, Calif., : IEEE Computer Society Press | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Proceedings of the ... International Verilog HDL Conference / / sponsored by Open Verilog International in cooperation with IEEE Computer Society
| Proceedings of the ... International Verilog HDL Conference / / sponsored by Open Verilog International in cooperation with IEEE Computer Society |
| Pubbl/distr/stampa | Los Alamitos, Calif., : IEEE Computer Society Press |
| Descrizione fisica | 1 online resource |
| Disciplina | 621.39/2 |
| Soggetto topico |
Verilog (Computer hardware description language)
VHDL (Computer hardware description language) |
| Soggetto genere / forma | Conference papers and proceedings. |
| Formato | Materiale a stampa |
| Livello bibliografico | Periodico |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
IEEE International Verilog HDL Conference
IVC Proceedings |
| Record Nr. | UNINA-9910626174503321 |
| Los Alamitos, Calif., : IEEE Computer Society Press | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Proceedings, 1996 IEEE International Verilog HDL Conference : February 26-28, 1996, Santa Clara, California / / IEEE Computer Society, Open Verilog International
| Proceedings, 1996 IEEE International Verilog HDL Conference : February 26-28, 1996, Santa Clara, California / / IEEE Computer Society, Open Verilog International |
| Pubbl/distr/stampa | Los Alamitos, CA : , : IEEE, , 1996 |
| Descrizione fisica | 1 online resource (x, 113 pages) : illustrations |
| Disciplina | 621.3902855133 |
| Soggetto topico | Verilog (Computer hardware description language) |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996200278203316 |
| Los Alamitos, CA : , : IEEE, , 1996 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Standard for systemverilog : unified hardware design, specification, and verification language
| Standard for systemverilog : unified hardware design, specification, and verification language |
| Pubbl/distr/stampa | New York : , : IEEE, , 2007 |
| Descrizione fisica | 1 online resource (257 pages) |
| Disciplina | 621.392 |
| Soggetto topico |
Verilog (Computer hardware description language)
Computer hardware description languages - Standards |
| ISBN | 0-7381-5726-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910135406203321 |
| New York : , : IEEE, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Standard for systemverilog : unified hardware design, specification, and verification language
| Standard for systemverilog : unified hardware design, specification, and verification language |
| Pubbl/distr/stampa | New York : , : IEEE, , 2007 |
| Descrizione fisica | 1 online resource (257 pages) |
| Disciplina | 621.392 |
| Soggetto topico |
Verilog (Computer hardware description language)
Computer hardware description languages - Standards |
| ISBN | 0-7381-5726-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996279343403316 |
| New York : , : IEEE, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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System Verilog assertions and functional coverage : guide to language, methodology and applications / / Ashok B. Mehta
| System Verilog assertions and functional coverage : guide to language, methodology and applications / / Ashok B. Mehta |
| Autore | Mehta Ashok B |
| Pubbl/distr/stampa | New York, : Springer, c2014 |
| Descrizione fisica | 1 online resource (xxxiii, 356 pages) : illustrations (some color) |
| Disciplina |
004.1
620 621.381 621.3815 |
| Collana | Gale eBooks |
| Soggetto topico |
Computer hardware description languages
Verilog (Computer hardware description language) |
| ISBN | 1-4614-7324-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- System Verilog Assertions -- Immediate Assertions -- Concurrent Assertions – Basics (sequence, property, assert).- Sampled Value Functions $rose, $fell -- Operators -- System Functions and Tasks -- Multiple clocks -- Local Variables -- Recursive property -- Detecting and using endpoint of a sequence -- ‘expect’ -- ‘assume’ and formal (static functional) verification -- Other important topics -- Asynchronous Assertions !!! -- IEEE-1800–2009 Features -- SystemVerilog Assertions LABs -- System Verilog Assertions – LAB Answers -- Functional Coverage -- Performance Implications of coverage methodology -- Coverage Options (Reference material). |
| Record Nr. | UNINA-9910299760103321 |
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Mehta Ashok B
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| New York, : Springer, c2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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