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FPGA prototyping by Verilog examples : Xilinx Spartan -3 version / / Pong P. Chu
| FPGA prototyping by Verilog examples : Xilinx Spartan -3 version / / Pong P. Chu |
| Autore | Chu Pong P. <1959-> |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Hoboken, N.J., : J. Wiley & Sons, c2008 |
| Descrizione fisica | 1 online resource (520 p.) |
| Disciplina | 621.39/5 |
| Soggetto topico |
Field programmable gate arrays - Design and construction
Prototypes, Engineering Verilog (Computer hardware description language) |
| ISBN |
1-118-21061-1
1-281-73257-5 9786611732578 0-470-37428-4 0-470-37427-6 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
FPGA Prototyping by Verilog Examples; CONTENTS; Preface; Acknowledgments; PART I BASIC DIGITAL CIRCUITS; 1 Gate-level combinational circuit; 1.4 Data types; 1.5 Program skeleton; 1.6 Structural description; 1.7 Testbench; 1.8 Bibliographic notes; 1.9 Suggested experiments; 2 Overview of FPGA and EDA software; 3 RT-level combinationaI circuit; 4 Regular Sequential Circuit; 5 FSM; 6 FSMD; 7 Selected Topics of Verilog; PART II I/O MODULES; 8 UART; 9 PS2 Keyboard; 10 PS2 Mouse; 11 External SRAM; 12 Xilinx Spartan 3 Specific Memory; 13 VGA controller I: graphic; 14 VGA controller II: text
PART III PICOBLAZE MICROCONTROLLER XILINX SPECIFIC15 PicoBlaze Overview; 16 PicoBlaze Assembly Code Development; 17 PicoBlaze I/O Interface; 18 PicoBlaze Interrupt Interface; Appendix A: Sample Verilog templates; A.1 Numbers and operators; A.2 General Verilog constructs; A.3 Routing with conditional operator and if and case statements; A.4 Combinational circuit using an always block; A.5 Memory Components; A.6 Regular sequential circuits; A.7 FSM; A.8 FSMD; A.9 S3 board constraint file (s3. ucf); References; Topic Index |
| Record Nr. | UNINA-9910819122103321 |
Chu Pong P. <1959->
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| Hoboken, N.J., : J. Wiley & Sons, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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FSM-based digital design using Verilog HDL [[electronic resource] /] / Peter Minns, Ian Elliott
| FSM-based digital design using Verilog HDL [[electronic resource] /] / Peter Minns, Ian Elliott |
| Autore | Minns Peter D |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Chichester, England ; ; Hoboken, NJ, : J. Wiley & Sons, c2008 |
| Descrizione fisica | 1 online resource (409 p.) |
| Disciplina | 004/.33 |
| Altri autori (Persone) | ElliottIan D |
| Soggetto topico |
Verilog (Computer hardware description language)
Digital electronics Sequential machine theory |
| ISBN |
1-282-34988-0
9786612349881 0-470-98762-6 0-470-98761-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
FSM-based Digital Design using Verilog HDL; Contents; Preface; Acknowledgements; 1 Introduction to Finite-State Machines and State Diagrams for the Design of Electronic Circuits and Systems; 1.1 INTRODUCTION; 1.2 LEARNING MATERIAL; 1.3 SUMMARY; 2 Using State Diagrams to Control External Hardware Subsystems; 2.1 INTRODUCTION; 2.2 LEARNING MATERIAL; 2.3 SUMMARY; 3 Synthesizing Hardware from a State Diagram; 3.1 INTRODUCTION TO FINITE-STATE MACHINE SYNTHESIS; 3.2 LEARNING MATERIAL; 3.3 SUMMARY; 4 Synchronous Finite-State Machine Designs; 4.1 TRADITIONAL STATE DIAGRAM SYNTHESIS METHOD
4.2 DEALING WITH UNUSED STATES4.3 DEVELOPMENT OF A HIGH/LOW ALARM INDICATOR SYSTEM; 4.3.1 Testing the Finite-State Machine using a Test-Bench Module; 4.4 SIMPLE WAVEFORM GENERATOR; 4.4.1 Sampling Frequency and Samples per Waveform; 4.5 THE DICE GAME; 4.5.1 Development of the Equations for the Dice Game; 4.6 BINARY DATA SERIAL TRANSMITTER; 4.6.1 The RE Counter Block in the Shift Register of Figure 4.15; 4.7 DEVELOPMENT OF A SERIAL ASYNCHRONOUS RECEIVER; 4.7.1 Finite-State Machine Equations; 4.8 ADDING PARITY DETECTION TO THE SERIAL RECEIVER SYSTEM; 4.8.1 To Incorporate the Parity 4.8.2 D-Type Equations for Figure 4.264.9 AN ASYNCHRONOUS SERIAL TRANSMITTER SYSTEM; 4.9.1 Equations for the Asynchronous Serial Transmitter; 4.10 CLOCKED WATCHDOG TIMER; 4.10.1 D Flip-Flop Equations; 4.10.2 Output Equation; 4.11 SUMMARY; 5 The One Hot Technique in Finite-State Machine Design; 5.1 THE ONE HOT TECHNIQUE; 5.2 A DATA ACQUISITION SYSTEM; 5.3 A SHARED MEMORY SYSTEM; 5.4 FAST WAVEFORM SYNTHESIZER; 5.4.1 Specification; 5.4.2 A Possible Solution; 5.4.3 Equations for the d Inputs to D Flip-Flops; 5.4.4 Output Equations 5.5 CONTROLLING THE FINITE-STATE MACHINE FROM A MICROPROCESSOR/MICROCONTROLLER5.6 A MEMORY-CHIP TESTER; 5.7 COMPARING ONE HOT WITH THE MORE CONVENTIONAL DESIGN METHOD OF CHAPTER 4; 5.8 A DYNAMIC MEMORY ACCESS CONTROLLER; 5.8.1 Flip-Flop Equations; 5.8.2 Output Equations; 5.9 HOW TO CONTROL THE DYNAMIC MEMORY ACCESS FROM A MICROPROCESSOR; 5.10 DETECTING SEQUENTIAL BINARY SEQUENCES USING A FINITE-STATE MACHINE; 5.11 SUMMARY; 6 Introduction to Verilog HDL; 6.1 A BRIEF BACKGROUND TO HARDWARE DESCRIPTION LANGUAGES; 6.2 HARDWARE MODELLING WITH VERILOG HDL: THE MODULE 6.3 MODULES WITHIN MODULES: CREATING HIERARCHY6.4 VERILOG HDL SIMULATION: A COMPLETE EXAMPLE; REFERENCES; 7 Elements of Verilog HDL; 7.1 BUILT-IN PRIMITIVES AND TYPES; 7.1.1 Verilog Types; 7.1.2 Verilog Logic and Numeric Values; 7.1.3 Specifying Values; 7.1.4 Verilog HDL Primitive Gates; 7.2 OPERATORS AND EXPRESSIONS; 7.3 EXAMPLE ILLUSTRATING THE USE OF VERILOG HDL OPERATORS: HAMMING CODE ENCODER; 7.3.1 Simulating the Hamming Encoder; REFERENCES; 8 Describing Combinational and Sequential Logic using Verilog HDL; 8.1 THE DATA-FLOW STYLE OF DESCRIPTION: REVIEW OF THE CONTINUOUS ASSIGNMENT 8.2 THE BEHAVIOURAL STYLE OF DESCRIPTION: THE SEQUENTIAL BLOCK |
| Record Nr. | UNINA-9910144431803321 |
|
Minns Peter D
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| Chichester, England ; ; Hoboken, NJ, : J. Wiley & Sons, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
FSM-based digital design using Verilog HDL [[electronic resource] /] / Peter Minns, Ian Elliott
| FSM-based digital design using Verilog HDL [[electronic resource] /] / Peter Minns, Ian Elliott |
| Autore | Minns Peter D |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Chichester, England ; ; Hoboken, NJ, : J. Wiley & Sons, c2008 |
| Descrizione fisica | 1 online resource (409 p.) |
| Disciplina | 004/.33 |
| Altri autori (Persone) | ElliottIan D |
| Soggetto topico |
Verilog (Computer hardware description language)
Digital electronics Sequential machine theory |
| ISBN |
1-282-34988-0
9786612349881 0-470-98762-6 0-470-98761-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
FSM-based Digital Design using Verilog HDL; Contents; Preface; Acknowledgements; 1 Introduction to Finite-State Machines and State Diagrams for the Design of Electronic Circuits and Systems; 1.1 INTRODUCTION; 1.2 LEARNING MATERIAL; 1.3 SUMMARY; 2 Using State Diagrams to Control External Hardware Subsystems; 2.1 INTRODUCTION; 2.2 LEARNING MATERIAL; 2.3 SUMMARY; 3 Synthesizing Hardware from a State Diagram; 3.1 INTRODUCTION TO FINITE-STATE MACHINE SYNTHESIS; 3.2 LEARNING MATERIAL; 3.3 SUMMARY; 4 Synchronous Finite-State Machine Designs; 4.1 TRADITIONAL STATE DIAGRAM SYNTHESIS METHOD
4.2 DEALING WITH UNUSED STATES4.3 DEVELOPMENT OF A HIGH/LOW ALARM INDICATOR SYSTEM; 4.3.1 Testing the Finite-State Machine using a Test-Bench Module; 4.4 SIMPLE WAVEFORM GENERATOR; 4.4.1 Sampling Frequency and Samples per Waveform; 4.5 THE DICE GAME; 4.5.1 Development of the Equations for the Dice Game; 4.6 BINARY DATA SERIAL TRANSMITTER; 4.6.1 The RE Counter Block in the Shift Register of Figure 4.15; 4.7 DEVELOPMENT OF A SERIAL ASYNCHRONOUS RECEIVER; 4.7.1 Finite-State Machine Equations; 4.8 ADDING PARITY DETECTION TO THE SERIAL RECEIVER SYSTEM; 4.8.1 To Incorporate the Parity 4.8.2 D-Type Equations for Figure 4.264.9 AN ASYNCHRONOUS SERIAL TRANSMITTER SYSTEM; 4.9.1 Equations for the Asynchronous Serial Transmitter; 4.10 CLOCKED WATCHDOG TIMER; 4.10.1 D Flip-Flop Equations; 4.10.2 Output Equation; 4.11 SUMMARY; 5 The One Hot Technique in Finite-State Machine Design; 5.1 THE ONE HOT TECHNIQUE; 5.2 A DATA ACQUISITION SYSTEM; 5.3 A SHARED MEMORY SYSTEM; 5.4 FAST WAVEFORM SYNTHESIZER; 5.4.1 Specification; 5.4.2 A Possible Solution; 5.4.3 Equations for the d Inputs to D Flip-Flops; 5.4.4 Output Equations 5.5 CONTROLLING THE FINITE-STATE MACHINE FROM A MICROPROCESSOR/MICROCONTROLLER5.6 A MEMORY-CHIP TESTER; 5.7 COMPARING ONE HOT WITH THE MORE CONVENTIONAL DESIGN METHOD OF CHAPTER 4; 5.8 A DYNAMIC MEMORY ACCESS CONTROLLER; 5.8.1 Flip-Flop Equations; 5.8.2 Output Equations; 5.9 HOW TO CONTROL THE DYNAMIC MEMORY ACCESS FROM A MICROPROCESSOR; 5.10 DETECTING SEQUENTIAL BINARY SEQUENCES USING A FINITE-STATE MACHINE; 5.11 SUMMARY; 6 Introduction to Verilog HDL; 6.1 A BRIEF BACKGROUND TO HARDWARE DESCRIPTION LANGUAGES; 6.2 HARDWARE MODELLING WITH VERILOG HDL: THE MODULE 6.3 MODULES WITHIN MODULES: CREATING HIERARCHY6.4 VERILOG HDL SIMULATION: A COMPLETE EXAMPLE; REFERENCES; 7 Elements of Verilog HDL; 7.1 BUILT-IN PRIMITIVES AND TYPES; 7.1.1 Verilog Types; 7.1.2 Verilog Logic and Numeric Values; 7.1.3 Specifying Values; 7.1.4 Verilog HDL Primitive Gates; 7.2 OPERATORS AND EXPRESSIONS; 7.3 EXAMPLE ILLUSTRATING THE USE OF VERILOG HDL OPERATORS: HAMMING CODE ENCODER; 7.3.1 Simulating the Hamming Encoder; REFERENCES; 8 Describing Combinational and Sequential Logic using Verilog HDL; 8.1 THE DATA-FLOW STYLE OF DESCRIPTION: REVIEW OF THE CONTINUOUS ASSIGNMENT 8.2 THE BEHAVIOURAL STYLE OF DESCRIPTION: THE SEQUENTIAL BLOCK |
| Record Nr. | UNINA-9910818859403321 |
|
Minns Peter D
|
||
| Chichester, England ; ; Hoboken, NJ, : J. Wiley & Sons, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
IEC 62530 Edition 2.0 2011-05 IEEE Std 1800 : SystemVerilog : unified hardware design, specification, and verification language / / Institute of Electrical and Electronics Engineers
| IEC 62530 Edition 2.0 2011-05 IEEE Std 1800 : SystemVerilog : unified hardware design, specification, and verification language / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : IEEE, , 2011 |
| Descrizione fisica | 1 online resource (1294 pages) |
| Disciplina | 621.392 |
| Soggetto topico |
Verilog (Computer hardware description language)
Computer hardware description languages |
| ISBN | 0-7381-6607-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | IEC 62530 Edition 2.0 2011-05 IEEE Std 1800: SystemVerilog Unified Hardware Design, Specification, and Verification Language |
| Record Nr. | UNINA-9910135406503321 |
| Piscataway, New Jersey : , : IEEE, , 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
IEC 62530 Edition 2.0 2011-05 IEEE Std 1800 : SystemVerilog : unified hardware design, specification, and verification language / / Institute of Electrical and Electronics Engineers
| IEC 62530 Edition 2.0 2011-05 IEEE Std 1800 : SystemVerilog : unified hardware design, specification, and verification language / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : IEEE, , 2011 |
| Descrizione fisica | 1 online resource (1294 pages) |
| Disciplina | 621.392 |
| Soggetto topico |
Verilog (Computer hardware description language)
Computer hardware description languages |
| ISBN | 0-7381-6607-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | IEC 62530 Edition 2.0 2011-05 IEEE Std 1800: SystemVerilog Unified Hardware Design, Specification, and Verification Language |
| Record Nr. | UNISA-996279343203316 |
| Piscataway, New Jersey : , : IEEE, , 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
IEEE Std 1364-2001 : IEEE Standard Verilog Hardware Description Language / / Institute of Electrical and Electronics Engineers
| IEEE Std 1364-2001 : IEEE Standard Verilog Hardware Description Language / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | New York, N.Y. : , : IEEE, , 2001 |
| Descrizione fisica | 1 online resource (xi, 778 pages) : illustrations |
| Disciplina | 621.392 |
| Soggetto topico |
Verilog (Computer hardware description language)
Computer hardware description languages |
| ISBN | 0-7381-2827-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | IEEE Std 1364-2001 |
| Record Nr. | UNINA-9910147233303321 |
| New York, N.Y. : , : IEEE, , 2001 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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IEEE Std 1364-2001 : IEEE Standard Verilog Hardware Description Language / / Institute of Electrical and Electronics Engineers
| IEEE Std 1364-2001 : IEEE Standard Verilog Hardware Description Language / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | New York, N.Y. : , : IEEE, , 2001 |
| Descrizione fisica | 1 online resource (xi, 778 pages) : illustrations |
| Disciplina | 621.392 |
| Soggetto topico |
Verilog (Computer hardware description language)
Computer hardware description languages |
| ISBN | 0-7381-2827-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | IEEE Std 1364-2001 |
| Record Nr. | UNISA-996280729103316 |
| New York, N.Y. : , : IEEE, , 2001 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
IEEE Std 1364.1-2002 : IEEE Standard for Verilog Register Transfer Level Synthesis / / Institute of Electrical and Electronics Engineers (IEEE)
| IEEE Std 1364.1-2002 : IEEE Standard for Verilog Register Transfer Level Synthesis / / Institute of Electrical and Electronics Engineers (IEEE) |
| Pubbl/distr/stampa | New York : , : Institute of Electrical and Electronics Engineers (IEEE), , 2002 |
| Descrizione fisica | 1 online resource (vii, 100 pages) |
| Disciplina | 621.392 |
| Soggetto topico |
Verilog (Computer hardware description language)
Verilog (Computer hardware description language) - Standards |
| ISBN | 0-7381-3502-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | IEEE Std 1364.1-2002 |
| Record Nr. | UNISA-996280555203316 |
| New York : , : Institute of Electrical and Electronics Engineers (IEEE), , 2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
IEEE Std 1364.1-2002 : IEEE Standard for Verilog Register Transfer Level Synthesis / / Institute of Electrical and Electronics Engineers (IEEE)
| IEEE Std 1364.1-2002 : IEEE Standard for Verilog Register Transfer Level Synthesis / / Institute of Electrical and Electronics Engineers (IEEE) |
| Pubbl/distr/stampa | New York : , : Institute of Electrical and Electronics Engineers (IEEE), , 2002 |
| Descrizione fisica | 1 online resource (vii, 100 pages) |
| Disciplina | 621.392 |
| Soggetto topico |
Verilog (Computer hardware description language)
Verilog (Computer hardware description language) - Standards |
| ISBN | 0-7381-3502-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | IEEE Std 1364.1-2002 |
| Record Nr. | UNINA-9910147226803321 |
| New York : , : Institute of Electrical and Electronics Engineers (IEEE), , 2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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IEEE STD 1800-2009 : IEEE standard for SystemVerilog--unified hardware design, specification, and verification language / / Institute of Electrical and Electronics Engineers
| IEEE STD 1800-2009 : IEEE standard for SystemVerilog--unified hardware design, specification, and verification language / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | New York, New York : , : IEEE, , 2009 |
| Descrizione fisica | 1 online resource (1285 pages) |
| Disciplina | 621.392 |
| Collana | IEEE Std |
| Soggetto topico | Verilog (Computer hardware description language) |
| ISBN | 0-7381-6130-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | IEEE STD 1800-2009 |
| Record Nr. | UNINA-9910135519403321 |
| New York, New York : , : IEEE, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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