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System-on-chip test architectures [[electronic resource] ] : nanometer design for testability / / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba
| System-on-chip test architectures [[electronic resource] ] : nanometer design for testability / / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 |
| Descrizione fisica | 1 online resource (893 p.) |
| Disciplina | 621.39/5 |
| Altri autori (Persone) |
WangLaung-Terng
StroudCharles E ToubaNur A |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Systems on a chip - Testing
Integrated circuits - Very large scale integration - Testing Integrated circuits - Very large scale integration - Design |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-281-10004-8
9786611100049 0-08-055680-9 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; System-on-Chip Test Architectures; Copyright Page; Table of Contents; Preface; In the Classroom; Acknowledgments; Contributors; About the Editors; Chapter 1 Introduction; 1.1 Importance of System-on-Chip Testing; 1.1.1 Yield and Reject Rate; 1.1.2 Reliability and System Availability; 1.2 Basics of SOC Testing; 1.2.1 Boundary Scan (IEEE 1149.1 Standard); 1.2.2 Boundary Scan Extension (IEEE 1149.6 Standard); 1.2.3 Boundary-Scan Accessible Embedded Instruments (IEEE P1687); 1.2.4 Core-Based Testing (IEEE 1500 Standard); 1.2.5 Analog Boundary Scan (IEEE 1149.4 Standard)
1.3 Basics of Memory Testing1.4 SOC Design Examples; 1.4.1 BioMEMS Sensor; 1.4.2 Network-on-Chip Processor; 1.5 About This Book; 1.5.1 DFT Architectures; 1.5.2 New Fault Models and Advanced Techniques; 1.5.3 Yield and Reliability Enhancement; 1.5.4 Nanotechnology Testing Aspects; 1.6 Exercises; Acknowledgments; References; Chapter 2 Digital Test Architectures; 2.1 Introduction; 2.2 Scan Design; 2.2.1 Scan Architectures; 2.2.1.1 Muxed-D Scan Design; 2.2.1.2 Clocked-Scan Design; 2.2.1.3 LSSD Scan Design; 2.2.1.4 Enhanced-Scan Design; 2.2.2 Low-Power Scan Architectures 2.2.2.1 Reduced-Voltage Low-Power Scan Design2.2.2.2 Reduced-Frequency Low-Power Scan Design; 2.2.2.3 Multi-Phase or Multi-Duty Low-Power Scan Design; 2.2.2.4 Bandwidth-Matching Low-Power Scan Design; 2.2.2.5 Hybrid Low-Power Scan Design; 2.2.3 At-Speed Scan Architectures; 2.3 Logic Built-In Self-Test; 2.3.1 Logic BIST Architectures; 2.3.1.1 Self-Testing Using MISR and Parallel SRSG (STUMPS); 2.3.1.2 Concurrent Built-In Logic Block Observer (CBILBO); 2.3.2 Coverage-Driven Logic BIST Architectures; 2.3.2.1 Weighted Pattern Generation; 2.3.2.2 Test Point Insertion; 2.3.2.3 Mixed-Mode BIST 2.3.2.4 Hybrid BIST2.3.3 Low-Power Logic BIST Architectures; 2.3.3.1 Low-Transition BIST Design; 2.3.3.2 Test-Vector-Inhibiting BIST Design; 2.3.3.3 Modified LFSR Low-Power BIST Design; 2.3.4 At-Speed Logic BIST Architectures; 2.3.4.1 Single-Capture; 2.3.4.2 Skewed-Load; 2.3.4.3 Double-Capture; 2.3.5 Industry Practices; 2.4 Test Compression; 2.4.1 Circuits for Test Stimulus Compression; 2.4.1.1 Linear-Decompression-Based Schemes; 2.4.1.2 Broadcast-Scan-Based Schemes; 2.4.1.3 Comparison; 2.4.2 Circuits for Test Response Compaction; 2.4.2.1 Space Compaction; 2.4.2.2 Time Compaction 2.4.2.3 Mixed Time and Space Compaction2.4.3 Low-Power Test Compression Architectures; 2.4.4 Industry Practices; 2.5 Random-Access Scan Design; 2.5.1 Random-Access Scan Architectures; 2.5.1.1 Progressive Random-Access Scan Design; 2.5.1.2 Shift-Addressable Random-Access Scan Design; 2.5.2 Test Compression RAS Architectures; 2.5.3 At-Speed RAS Architectures; 2.6 Concluding Remarks; 2.7 Exercises; Acknowledgments; References; Chapter 3 Fault-Tolerant Design; 3.1 Introduction; 3.2 Fundamentals of Fault Tolerance; 3.2.1 Reliability; 3.2.2 Mean Time to Failure (MTTF); 3.2.3 Maintainability 3.2.4 Availability |
| Record Nr. | UNINA-9910451492103321 |
| Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
System-on-chip test architectures [[electronic resource] ] : nanometer design for testability / / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba
| System-on-chip test architectures [[electronic resource] ] : nanometer design for testability / / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 |
| Descrizione fisica | 1 online resource (893 p.) |
| Disciplina | 621.39/5 |
| Altri autori (Persone) |
WangLaung-Terng
StroudCharles E ToubaNur A |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Systems on a chip - Testing
Integrated circuits - Very large scale integration - Testing Integrated circuits - Very large scale integration - Design |
| ISBN |
1-281-10004-8
9786611100049 0-08-055680-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; System-on-Chip Test Architectures; Copyright Page; Table of Contents; Preface; In the Classroom; Acknowledgments; Contributors; About the Editors; Chapter 1 Introduction; 1.1 Importance of System-on-Chip Testing; 1.1.1 Yield and Reject Rate; 1.1.2 Reliability and System Availability; 1.2 Basics of SOC Testing; 1.2.1 Boundary Scan (IEEE 1149.1 Standard); 1.2.2 Boundary Scan Extension (IEEE 1149.6 Standard); 1.2.3 Boundary-Scan Accessible Embedded Instruments (IEEE P1687); 1.2.4 Core-Based Testing (IEEE 1500 Standard); 1.2.5 Analog Boundary Scan (IEEE 1149.4 Standard)
1.3 Basics of Memory Testing1.4 SOC Design Examples; 1.4.1 BioMEMS Sensor; 1.4.2 Network-on-Chip Processor; 1.5 About This Book; 1.5.1 DFT Architectures; 1.5.2 New Fault Models and Advanced Techniques; 1.5.3 Yield and Reliability Enhancement; 1.5.4 Nanotechnology Testing Aspects; 1.6 Exercises; Acknowledgments; References; Chapter 2 Digital Test Architectures; 2.1 Introduction; 2.2 Scan Design; 2.2.1 Scan Architectures; 2.2.1.1 Muxed-D Scan Design; 2.2.1.2 Clocked-Scan Design; 2.2.1.3 LSSD Scan Design; 2.2.1.4 Enhanced-Scan Design; 2.2.2 Low-Power Scan Architectures 2.2.2.1 Reduced-Voltage Low-Power Scan Design2.2.2.2 Reduced-Frequency Low-Power Scan Design; 2.2.2.3 Multi-Phase or Multi-Duty Low-Power Scan Design; 2.2.2.4 Bandwidth-Matching Low-Power Scan Design; 2.2.2.5 Hybrid Low-Power Scan Design; 2.2.3 At-Speed Scan Architectures; 2.3 Logic Built-In Self-Test; 2.3.1 Logic BIST Architectures; 2.3.1.1 Self-Testing Using MISR and Parallel SRSG (STUMPS); 2.3.1.2 Concurrent Built-In Logic Block Observer (CBILBO); 2.3.2 Coverage-Driven Logic BIST Architectures; 2.3.2.1 Weighted Pattern Generation; 2.3.2.2 Test Point Insertion; 2.3.2.3 Mixed-Mode BIST 2.3.2.4 Hybrid BIST2.3.3 Low-Power Logic BIST Architectures; 2.3.3.1 Low-Transition BIST Design; 2.3.3.2 Test-Vector-Inhibiting BIST Design; 2.3.3.3 Modified LFSR Low-Power BIST Design; 2.3.4 At-Speed Logic BIST Architectures; 2.3.4.1 Single-Capture; 2.3.4.2 Skewed-Load; 2.3.4.3 Double-Capture; 2.3.5 Industry Practices; 2.4 Test Compression; 2.4.1 Circuits for Test Stimulus Compression; 2.4.1.1 Linear-Decompression-Based Schemes; 2.4.1.2 Broadcast-Scan-Based Schemes; 2.4.1.3 Comparison; 2.4.2 Circuits for Test Response Compaction; 2.4.2.1 Space Compaction; 2.4.2.2 Time Compaction 2.4.2.3 Mixed Time and Space Compaction2.4.3 Low-Power Test Compression Architectures; 2.4.4 Industry Practices; 2.5 Random-Access Scan Design; 2.5.1 Random-Access Scan Architectures; 2.5.1.1 Progressive Random-Access Scan Design; 2.5.1.2 Shift-Addressable Random-Access Scan Design; 2.5.2 Test Compression RAS Architectures; 2.5.3 At-Speed RAS Architectures; 2.6 Concluding Remarks; 2.7 Exercises; Acknowledgments; References; Chapter 3 Fault-Tolerant Design; 3.1 Introduction; 3.2 Fundamentals of Fault Tolerance; 3.2.1 Reliability; 3.2.2 Mean Time to Failure (MTTF); 3.2.3 Maintainability 3.2.4 Availability |
| Record Nr. | UNINA-9910785095503321 |
| Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
System-on-chip test architectures : nanometer design for testability / / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba
| System-on-chip test architectures : nanometer design for testability / / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 |
| Descrizione fisica | 1 online resource (893 p.) |
| Disciplina |
621.39/5
621.395 |
| Altri autori (Persone) |
WangLaung-Terng
StroudCharles E ToubaNur A |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Systems on a chip - Testing
Integrated circuits - Very large scale integration - Testing Integrated circuits - Very large scale integration - Design |
| ISBN |
1-281-10004-8
9786611100049 0-08-055680-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; System-on-Chip Test Architectures; Copyright Page; Table of Contents; Preface; In the Classroom; Acknowledgments; Contributors; About the Editors; Chapter 1 Introduction; 1.1 Importance of System-on-Chip Testing; 1.1.1 Yield and Reject Rate; 1.1.2 Reliability and System Availability; 1.2 Basics of SOC Testing; 1.2.1 Boundary Scan (IEEE 1149.1 Standard); 1.2.2 Boundary Scan Extension (IEEE 1149.6 Standard); 1.2.3 Boundary-Scan Accessible Embedded Instruments (IEEE P1687); 1.2.4 Core-Based Testing (IEEE 1500 Standard); 1.2.5 Analog Boundary Scan (IEEE 1149.4 Standard)
1.3 Basics of Memory Testing1.4 SOC Design Examples; 1.4.1 BioMEMS Sensor; 1.4.2 Network-on-Chip Processor; 1.5 About This Book; 1.5.1 DFT Architectures; 1.5.2 New Fault Models and Advanced Techniques; 1.5.3 Yield and Reliability Enhancement; 1.5.4 Nanotechnology Testing Aspects; 1.6 Exercises; Acknowledgments; References; Chapter 2 Digital Test Architectures; 2.1 Introduction; 2.2 Scan Design; 2.2.1 Scan Architectures; 2.2.1.1 Muxed-D Scan Design; 2.2.1.2 Clocked-Scan Design; 2.2.1.3 LSSD Scan Design; 2.2.1.4 Enhanced-Scan Design; 2.2.2 Low-Power Scan Architectures 2.2.2.1 Reduced-Voltage Low-Power Scan Design2.2.2.2 Reduced-Frequency Low-Power Scan Design; 2.2.2.3 Multi-Phase or Multi-Duty Low-Power Scan Design; 2.2.2.4 Bandwidth-Matching Low-Power Scan Design; 2.2.2.5 Hybrid Low-Power Scan Design; 2.2.3 At-Speed Scan Architectures; 2.3 Logic Built-In Self-Test; 2.3.1 Logic BIST Architectures; 2.3.1.1 Self-Testing Using MISR and Parallel SRSG (STUMPS); 2.3.1.2 Concurrent Built-In Logic Block Observer (CBILBO); 2.3.2 Coverage-Driven Logic BIST Architectures; 2.3.2.1 Weighted Pattern Generation; 2.3.2.2 Test Point Insertion; 2.3.2.3 Mixed-Mode BIST 2.3.2.4 Hybrid BIST2.3.3 Low-Power Logic BIST Architectures; 2.3.3.1 Low-Transition BIST Design; 2.3.3.2 Test-Vector-Inhibiting BIST Design; 2.3.3.3 Modified LFSR Low-Power BIST Design; 2.3.4 At-Speed Logic BIST Architectures; 2.3.4.1 Single-Capture; 2.3.4.2 Skewed-Load; 2.3.4.3 Double-Capture; 2.3.5 Industry Practices; 2.4 Test Compression; 2.4.1 Circuits for Test Stimulus Compression; 2.4.1.1 Linear-Decompression-Based Schemes; 2.4.1.2 Broadcast-Scan-Based Schemes; 2.4.1.3 Comparison; 2.4.2 Circuits for Test Response Compaction; 2.4.2.1 Space Compaction; 2.4.2.2 Time Compaction 2.4.2.3 Mixed Time and Space Compaction2.4.3 Low-Power Test Compression Architectures; 2.4.4 Industry Practices; 2.5 Random-Access Scan Design; 2.5.1 Random-Access Scan Architectures; 2.5.1.1 Progressive Random-Access Scan Design; 2.5.1.2 Shift-Addressable Random-Access Scan Design; 2.5.2 Test Compression RAS Architectures; 2.5.3 At-Speed RAS Architectures; 2.6 Concluding Remarks; 2.7 Exercises; Acknowledgments; References; Chapter 3 Fault-Tolerant Design; 3.1 Introduction; 3.2 Fundamentals of Fault Tolerance; 3.2.1 Reliability; 3.2.2 Mean Time to Failure (MTTF); 3.2.3 Maintainability 3.2.4 Availability |
| Record Nr. | UNINA-9910820907503321 |
| Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Verification techniques for system-level design [[electronic resource] /] / Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad
| Verification techniques for system-level design [[electronic resource] /] / Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad |
| Autore | Fujita Masahiro <1956-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 |
| Descrizione fisica | 1 online resource (251 p.) |
| Disciplina | 621.3815 |
| Altri autori (Persone) |
GhoshIndradeep <1970->
PrasadMukul |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Systems on a chip - Testing
Integrated circuits - Verification Formal methods (Computer science) |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-281-04964-6
9786611049645 0-08-055313-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Verification Techniques For System-Level Design; Copyright Page; Contents; Acknowledgments; Chapter 1 Introduction; Chapter 2 Higher-Level Design Methodology and Associated Verification Problems; 2.1 Introduction; 2.2 Issues in High-Level Design; 2.3 C/C++-Based Design and Specification Languages; 2.3.1 SpecC Language; 2.3.2 The Semantics of par Statements; 2.3.3 Relationship with Simulation Time; 2.4 System-Level Design Methodology Based on C/C++-Based Design and Specification Languages; 2.5 Verification Problems in High-Level Designs
Chapter 3 Basic Technology for Formal Verification3.1 The Boolean Satisfiability Problem; 3.2 The DPLL Algorithm; 3.3 Enhancements to Modern SAT Solvers; 3.4 Capabilities of Modern SAT Solvers; 3.5 Binary Decision Diagrams; 3.5.1 Manipulation of BDDs; 3.5.2 Variants of BDDs; 3.6 Automatic Test Pattern Generation Engines; 3.6.1 Single Stuck-at Testing for Combinational Circuits; 3.6.2 Stuck-at Testing in Sequential Circuits; 3.7 SAT, BDD, and ATPG Engines for Validation; 3.8 Theorem-Proving and Decision Procedures; References; Chapter 4 Verification Algorithms for FSM Models 4.1 Combinational Equivalence Checking4.1.1 Sequential Equivalence Checking as Combinational Equivalence Checking; 4.1.2 Latch Mapping Problem; 4.1.3 EC Based on Internal Equivalences; 4.1.4 Anatomy and Capabilities of Modern CEC Tools; 4.2 Model Checking; 4.2.1 Modeling Concurrent Systems; 4.2.2 Temporal Logics; 4.2.3 Types of Properties; 4.2.4 Basic Model-Checking Algorithms; 4.2.5 Symbolic Model Checking; 4.3 Semi-Formal Verification Techniques; 4.3.1 SAT-Based Bounded Model Checking; 4.3.2 Symbolic Simulation; 4.3.3 Enhancing Simulation Using Formal Methods; 4.4 Conclusion; References Chapter 5 Static Checking of Higher-Level Design Descriptions5.1 Program Slicing; 5.1.1 System Dependence Graph; 5.1.2 Nodes and Edges; 5.1.3 Concurrency; 5.1.4 Synchronization on Concurrent Processes; 5.2 Checking Method and Its Implying Design Flow; 5.2.1 Basic Static Description Checking; 5.2.2 Improvement of Accuracy Using Conditions of Control Nodes; 5.3 Application of the Checking Methods to HW/SW Partitioning and Optimization; 5.4 Case Study; 5.4.1 MPEG2; 5.4.2 JPEG2000; 5.4.3 Experimental Results on Static Checking; References Chapter 6 Equivalence Checking on Higher-Level Design Descriptions6.1 Introduction; 6.2 High-Level Design Flow from the Viewpoint of Equivalence Checking; 6.3 Symbolic Simulation for Equivalence Checking; 6.4 Equivalence-Checking Methods Based on the Identification of Differences between two Descriptions; 6.4.1 Identification of Differences between Two Descriptions; 6.4.2 Symbolic Simulation Based on Textual Differences; 6.4.3 Example; 6.4.4 Experimental Results; 6.5 Further Improvement on the Use of Differences between Two Descriptions; 6.5.1 Extension of the Verification Area 6.5.2 Symbolic Simulation on SDGs |
| Record Nr. | UNINA-9910451297403321 |
Fujita Masahiro <1956->
|
||
| Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Verification techniques for system-level design [[electronic resource] /] / Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad
| Verification techniques for system-level design [[electronic resource] /] / Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad |
| Autore | Fujita Masahiro <1956-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 |
| Descrizione fisica | 1 online resource (251 p.) |
| Disciplina | 621.3815 |
| Altri autori (Persone) |
GhoshIndradeep <1970->
PrasadMukul |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Systems on a chip - Testing
Integrated circuits - Verification Formal methods (Computer science) |
| ISBN |
1-281-04964-6
9786611049645 0-08-055313-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Verification Techniques For System-Level Design; Copyright Page; Contents; Acknowledgments; Chapter 1 Introduction; Chapter 2 Higher-Level Design Methodology and Associated Verification Problems; 2.1 Introduction; 2.2 Issues in High-Level Design; 2.3 C/C++-Based Design and Specification Languages; 2.3.1 SpecC Language; 2.3.2 The Semantics of par Statements; 2.3.3 Relationship with Simulation Time; 2.4 System-Level Design Methodology Based on C/C++-Based Design and Specification Languages; 2.5 Verification Problems in High-Level Designs
Chapter 3 Basic Technology for Formal Verification3.1 The Boolean Satisfiability Problem; 3.2 The DPLL Algorithm; 3.3 Enhancements to Modern SAT Solvers; 3.4 Capabilities of Modern SAT Solvers; 3.5 Binary Decision Diagrams; 3.5.1 Manipulation of BDDs; 3.5.2 Variants of BDDs; 3.6 Automatic Test Pattern Generation Engines; 3.6.1 Single Stuck-at Testing for Combinational Circuits; 3.6.2 Stuck-at Testing in Sequential Circuits; 3.7 SAT, BDD, and ATPG Engines for Validation; 3.8 Theorem-Proving and Decision Procedures; References; Chapter 4 Verification Algorithms for FSM Models 4.1 Combinational Equivalence Checking4.1.1 Sequential Equivalence Checking as Combinational Equivalence Checking; 4.1.2 Latch Mapping Problem; 4.1.3 EC Based on Internal Equivalences; 4.1.4 Anatomy and Capabilities of Modern CEC Tools; 4.2 Model Checking; 4.2.1 Modeling Concurrent Systems; 4.2.2 Temporal Logics; 4.2.3 Types of Properties; 4.2.4 Basic Model-Checking Algorithms; 4.2.5 Symbolic Model Checking; 4.3 Semi-Formal Verification Techniques; 4.3.1 SAT-Based Bounded Model Checking; 4.3.2 Symbolic Simulation; 4.3.3 Enhancing Simulation Using Formal Methods; 4.4 Conclusion; References Chapter 5 Static Checking of Higher-Level Design Descriptions5.1 Program Slicing; 5.1.1 System Dependence Graph; 5.1.2 Nodes and Edges; 5.1.3 Concurrency; 5.1.4 Synchronization on Concurrent Processes; 5.2 Checking Method and Its Implying Design Flow; 5.2.1 Basic Static Description Checking; 5.2.2 Improvement of Accuracy Using Conditions of Control Nodes; 5.3 Application of the Checking Methods to HW/SW Partitioning and Optimization; 5.4 Case Study; 5.4.1 MPEG2; 5.4.2 JPEG2000; 5.4.3 Experimental Results on Static Checking; References Chapter 6 Equivalence Checking on Higher-Level Design Descriptions6.1 Introduction; 6.2 High-Level Design Flow from the Viewpoint of Equivalence Checking; 6.3 Symbolic Simulation for Equivalence Checking; 6.4 Equivalence-Checking Methods Based on the Identification of Differences between two Descriptions; 6.4.1 Identification of Differences between Two Descriptions; 6.4.2 Symbolic Simulation Based on Textual Differences; 6.4.3 Example; 6.4.4 Experimental Results; 6.5 Further Improvement on the Use of Differences between Two Descriptions; 6.5.1 Extension of the Verification Area 6.5.2 Symbolic Simulation on SDGs |
| Record Nr. | UNINA-9910784993803321 |
|
Fujita Masahiro <1956->
|
||
| Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Verification techniques for system-level design / / Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad
| Verification techniques for system-level design / / Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad |
| Autore | Fujita Masahiro <1956-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 |
| Descrizione fisica | 1 online resource (251 p.) |
| Disciplina | 621.3815 |
| Altri autori (Persone) |
GhoshIndradeep <1970->
PrasadMukul |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Systems on a chip - Testing
Integrated circuits - Verification Formal methods (Computer science) |
| ISBN |
1-281-04964-6
9786611049645 0-08-055313-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Verification Techniques For System-Level Design; Copyright Page; Contents; Acknowledgments; Chapter 1 Introduction; Chapter 2 Higher-Level Design Methodology and Associated Verification Problems; 2.1 Introduction; 2.2 Issues in High-Level Design; 2.3 C/C++-Based Design and Specification Languages; 2.3.1 SpecC Language; 2.3.2 The Semantics of par Statements; 2.3.3 Relationship with Simulation Time; 2.4 System-Level Design Methodology Based on C/C++-Based Design and Specification Languages; 2.5 Verification Problems in High-Level Designs
Chapter 3 Basic Technology for Formal Verification3.1 The Boolean Satisfiability Problem; 3.2 The DPLL Algorithm; 3.3 Enhancements to Modern SAT Solvers; 3.4 Capabilities of Modern SAT Solvers; 3.5 Binary Decision Diagrams; 3.5.1 Manipulation of BDDs; 3.5.2 Variants of BDDs; 3.6 Automatic Test Pattern Generation Engines; 3.6.1 Single Stuck-at Testing for Combinational Circuits; 3.6.2 Stuck-at Testing in Sequential Circuits; 3.7 SAT, BDD, and ATPG Engines for Validation; 3.8 Theorem-Proving and Decision Procedures; References; Chapter 4 Verification Algorithms for FSM Models 4.1 Combinational Equivalence Checking4.1.1 Sequential Equivalence Checking as Combinational Equivalence Checking; 4.1.2 Latch Mapping Problem; 4.1.3 EC Based on Internal Equivalences; 4.1.4 Anatomy and Capabilities of Modern CEC Tools; 4.2 Model Checking; 4.2.1 Modeling Concurrent Systems; 4.2.2 Temporal Logics; 4.2.3 Types of Properties; 4.2.4 Basic Model-Checking Algorithms; 4.2.5 Symbolic Model Checking; 4.3 Semi-Formal Verification Techniques; 4.3.1 SAT-Based Bounded Model Checking; 4.3.2 Symbolic Simulation; 4.3.3 Enhancing Simulation Using Formal Methods; 4.4 Conclusion; References Chapter 5 Static Checking of Higher-Level Design Descriptions5.1 Program Slicing; 5.1.1 System Dependence Graph; 5.1.2 Nodes and Edges; 5.1.3 Concurrency; 5.1.4 Synchronization on Concurrent Processes; 5.2 Checking Method and Its Implying Design Flow; 5.2.1 Basic Static Description Checking; 5.2.2 Improvement of Accuracy Using Conditions of Control Nodes; 5.3 Application of the Checking Methods to HW/SW Partitioning and Optimization; 5.4 Case Study; 5.4.1 MPEG2; 5.4.2 JPEG2000; 5.4.3 Experimental Results on Static Checking; References Chapter 6 Equivalence Checking on Higher-Level Design Descriptions6.1 Introduction; 6.2 High-Level Design Flow from the Viewpoint of Equivalence Checking; 6.3 Symbolic Simulation for Equivalence Checking; 6.4 Equivalence-Checking Methods Based on the Identification of Differences between two Descriptions; 6.4.1 Identification of Differences between Two Descriptions; 6.4.2 Symbolic Simulation Based on Textual Differences; 6.4.3 Example; 6.4.4 Experimental Results; 6.5 Further Improvement on the Use of Differences between Two Descriptions; 6.5.1 Extension of the Verification Area 6.5.2 Symbolic Simulation on SDGs |
| Record Nr. | UNINA-9910807040803321 |
|
Fujita Masahiro <1956->
|
||
| Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
