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ESL design and verification [[electronic resource] ] : a prescription for electronic system-level methodology / / Brian Bailey, Grant Martin, Andrew Piziali
ESL design and verification [[electronic resource] ] : a prescription for electronic system-level methodology / / Brian Bailey, Grant Martin, Andrew Piziali
Autore Bailey Brian <1959->
Pubbl/distr/stampa Amsterdam ; ; Boston, : Morgan Kaufmann, c2007
Descrizione fisica 1 online resource (489 p.)
Disciplina 621.3815
Altri autori (Persone) MartinGrant (Grant Edmund)
PizialiAndrew
Collana The Morgan Kaufmann series in systems on silicon
Soggetto topico Systems on a chip - Design and construction
Soggetto genere / forma Electronic books.
ISBN 1-281-05353-8
9786611053536
0-08-048883-8
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front cover; ESL DESIGN AND VERIFICATION; Copyright page; Table of contents; FOREWORD: ESL FROM THE TRENCHES; AUTHORS' ACKNOWLEDGMENTS; ABOUT THE AUTHORS; ABOUT THE CONTRIBUTORS; Chapter 1. WHAT IS ESL?; 1.1 SO, WHAT IS ESL?; 1.2 WHO SHOULD READ THIS BOOK; 1.3 STRUCTURE OF THE BOOK AND HOW TO READ IT; 1.4 CHAPTER LISTING; 1.5 THE PRESCRIPTION; References; Chapter 2. TAXONOMY AND DEFINITIONS FOR THE ELECTRONIC SYSTEM LEVEL; 2.1 TAXONOMY; 2.1.1 Introduction; 2.1.2 Model Taxonomy; 2.1.3 ESL Taxonomy; 2.2 DEFINITIONS; References; Chapter 3. EVOLUTION OF ESL DEVELOPMENT; 3.1 INTRODUCTION
3.2 MOTIVATION FOR ESL DESIGN3.3 TRADITIONAL SYSTEM DESIGN EFFECTIVENESS; 3.4 SYSTEM DESIGN WITH ESL METHODOLOGY; 3.5 BEHAVIORAL MODELING METHODOLOGY; 3.6 BEHAVIORAL MODELING ENVIRONMENTS; 3.7 HISTORICAL BARRIERS TO ADOPTION OF BEHAVIORAL MODELING; 3.8 AUTOMATED IMPLEMENTATION OF FIXED-FUNCTION HARDWARE; 3.9 AUTOMATED IMPLEMENTATION OF PROGRAMMABLE HARDWARE; 3.10 MAINSTREAMING ESL METHODOLOGY; 3.11 PROVOCATIVE THOUGHTS; 3.12 THE PRESCRIPTION; References; Chapter 4. WHAT ARE THE ENABLERS OF ESL?; 4.1 TOOL AND MODEL LANDSCAPE; 4.2 SYSTEM DESIGNER REQUIREMENTS; 4.3 SOFTWARE TEAM REQUIREMENTS
4.4 HARDWARE TEAM REQUIREMENTS4.5 WHO WILL SERVICE THESE DIVERSE REQUIREMENTS?; 4.6 FREE OR OPEN SOURCE SOFTWARE; 4.7 SUMMARY; 4.8 THE PRESCRIPTION; References; Chapter 5. ESL FLOW; 5.1 SPECIFICATIONS AND MODELING; 5.2 PRE-PARTITIONING ANALYSIS; 5.3 PARTITIONING; 5.4 POST-PARTITIONING ANALYSIS AND DEBUG; 5.5 POST-PARTITIONING VERIFICATION; 5.6 HARDWARE IMPLEMENTATION; 5.7 SOFTWARE IMPLEMENTATION; 5.8 USE OF ESL FOR IMPLEMENTATION VERIFICATION; 5.9 PROVOCATIVE THOUGHTS; 5.10 SUMMARY; 5.11 THE PRESCRIPTION; References; Chapter 6. SPECIFICATIONS AND MODELING; 6.1 THE PROBLEM OF SPECIFICATION
6.2 REQUIREMENTS MANAGEMENT AND PAPER SPECIFICATIONS6.3 ESL DOMAINS; 6.4 EXECUTABLE SPECIFICATIONS; 6.5 SOME ESL LANGUAGES FOR SPECIFICATION; 6.6 PROVOCATIVE THOUGHTS: MODEL-BASED DEVELOPMENT; 6.7 SUMMARY; 6.8 THE PRESCRIPTION; References; Chapter 7. PRE-PARTITIONING ANALYSIS; 7.1 STATIC ANALYSIS OF SYSTEM SPECIFICATIONS; 7.2 THE ROLE OF PLATFORM-BASED ESL DESIGN IN PRE-PARTITIONING ANALYSIS; 7.3 DYNAMIC ANALYSIS; 7.4 ALGORITHMIC ANALYSIS; 7.5 ANALYSIS SCENARIOS AND MODELING; 7.6 DOWNSTREAM USE OF ANALYSIS RESULTS; 7.7 CASE STUDY: JPEG ENCODING; 7.8 SUMMARY AND PROVOCATIVE THOUGHTS
7.9 THE PRESCRIPTIONReferences; Chapter 8. PARTITIONING; 8.1 INTRODUCTION; 8.2 FUNCTIONAL DECOMPOSITION; 8.3 ARCHITECTURE DESCRIPTION; 8.4 PARTITIONING; 8.5 THE HARDWARE PARTITION; 8.6 THE SOFTWARE PARTITION; 8.7 RECONFIGURABLE COMPUTING; 8.8 COMMUNICATION IMPLEMENTATION; 8.9 PROVOCATIVE THOUGHTS; 8.10 SUMMARY; 8.11 THE PRESCRIPTION; References; Chapter 9. POST-PARTITIONING ANALYSIS AND DEBUG; 9.1 ROLES AND RESPONSIBILITIES; 9.2 HARDWARE AND SOFTWARE MODELING AND CO-MODELING; 9.3 PARTITIONED SYSTEMS AND RE-PARTITIONING; 9.4 PRE-PARTITIONED MODEL COMPONENTS; 9.5 ABSTRACTION LEVELS
9.6 COMMUNICATION SPECIFICATION
Record Nr. UNINA-9910458648603321
Bailey Brian <1959->  
Amsterdam ; ; Boston, : Morgan Kaufmann, c2007
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
ESL design and verification [[electronic resource] ] : a prescription for electronic system-level methodology / / Brian Bailey, Grant Martin, Andrew Piziali
ESL design and verification [[electronic resource] ] : a prescription for electronic system-level methodology / / Brian Bailey, Grant Martin, Andrew Piziali
Autore Bailey Brian <1959->
Pubbl/distr/stampa Amsterdam ; ; Boston, : Morgan Kaufmann, c2007
Descrizione fisica 1 online resource (489 p.)
Disciplina 621.3815
Altri autori (Persone) MartinGrant (Grant Edmund)
PizialiAndrew
Collana The Morgan Kaufmann series in systems on silicon
Soggetto topico Systems on a chip - Design and construction
ISBN 1-281-05353-8
9786611053536
0-08-048883-8
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front cover; ESL DESIGN AND VERIFICATION; Copyright page; Table of contents; FOREWORD: ESL FROM THE TRENCHES; AUTHORS' ACKNOWLEDGMENTS; ABOUT THE AUTHORS; ABOUT THE CONTRIBUTORS; Chapter 1. WHAT IS ESL?; 1.1 SO, WHAT IS ESL?; 1.2 WHO SHOULD READ THIS BOOK; 1.3 STRUCTURE OF THE BOOK AND HOW TO READ IT; 1.4 CHAPTER LISTING; 1.5 THE PRESCRIPTION; References; Chapter 2. TAXONOMY AND DEFINITIONS FOR THE ELECTRONIC SYSTEM LEVEL; 2.1 TAXONOMY; 2.1.1 Introduction; 2.1.2 Model Taxonomy; 2.1.3 ESL Taxonomy; 2.2 DEFINITIONS; References; Chapter 3. EVOLUTION OF ESL DEVELOPMENT; 3.1 INTRODUCTION
3.2 MOTIVATION FOR ESL DESIGN3.3 TRADITIONAL SYSTEM DESIGN EFFECTIVENESS; 3.4 SYSTEM DESIGN WITH ESL METHODOLOGY; 3.5 BEHAVIORAL MODELING METHODOLOGY; 3.6 BEHAVIORAL MODELING ENVIRONMENTS; 3.7 HISTORICAL BARRIERS TO ADOPTION OF BEHAVIORAL MODELING; 3.8 AUTOMATED IMPLEMENTATION OF FIXED-FUNCTION HARDWARE; 3.9 AUTOMATED IMPLEMENTATION OF PROGRAMMABLE HARDWARE; 3.10 MAINSTREAMING ESL METHODOLOGY; 3.11 PROVOCATIVE THOUGHTS; 3.12 THE PRESCRIPTION; References; Chapter 4. WHAT ARE THE ENABLERS OF ESL?; 4.1 TOOL AND MODEL LANDSCAPE; 4.2 SYSTEM DESIGNER REQUIREMENTS; 4.3 SOFTWARE TEAM REQUIREMENTS
4.4 HARDWARE TEAM REQUIREMENTS4.5 WHO WILL SERVICE THESE DIVERSE REQUIREMENTS?; 4.6 FREE OR OPEN SOURCE SOFTWARE; 4.7 SUMMARY; 4.8 THE PRESCRIPTION; References; Chapter 5. ESL FLOW; 5.1 SPECIFICATIONS AND MODELING; 5.2 PRE-PARTITIONING ANALYSIS; 5.3 PARTITIONING; 5.4 POST-PARTITIONING ANALYSIS AND DEBUG; 5.5 POST-PARTITIONING VERIFICATION; 5.6 HARDWARE IMPLEMENTATION; 5.7 SOFTWARE IMPLEMENTATION; 5.8 USE OF ESL FOR IMPLEMENTATION VERIFICATION; 5.9 PROVOCATIVE THOUGHTS; 5.10 SUMMARY; 5.11 THE PRESCRIPTION; References; Chapter 6. SPECIFICATIONS AND MODELING; 6.1 THE PROBLEM OF SPECIFICATION
6.2 REQUIREMENTS MANAGEMENT AND PAPER SPECIFICATIONS6.3 ESL DOMAINS; 6.4 EXECUTABLE SPECIFICATIONS; 6.5 SOME ESL LANGUAGES FOR SPECIFICATION; 6.6 PROVOCATIVE THOUGHTS: MODEL-BASED DEVELOPMENT; 6.7 SUMMARY; 6.8 THE PRESCRIPTION; References; Chapter 7. PRE-PARTITIONING ANALYSIS; 7.1 STATIC ANALYSIS OF SYSTEM SPECIFICATIONS; 7.2 THE ROLE OF PLATFORM-BASED ESL DESIGN IN PRE-PARTITIONING ANALYSIS; 7.3 DYNAMIC ANALYSIS; 7.4 ALGORITHMIC ANALYSIS; 7.5 ANALYSIS SCENARIOS AND MODELING; 7.6 DOWNSTREAM USE OF ANALYSIS RESULTS; 7.7 CASE STUDY: JPEG ENCODING; 7.8 SUMMARY AND PROVOCATIVE THOUGHTS
7.9 THE PRESCRIPTIONReferences; Chapter 8. PARTITIONING; 8.1 INTRODUCTION; 8.2 FUNCTIONAL DECOMPOSITION; 8.3 ARCHITECTURE DESCRIPTION; 8.4 PARTITIONING; 8.5 THE HARDWARE PARTITION; 8.6 THE SOFTWARE PARTITION; 8.7 RECONFIGURABLE COMPUTING; 8.8 COMMUNICATION IMPLEMENTATION; 8.9 PROVOCATIVE THOUGHTS; 8.10 SUMMARY; 8.11 THE PRESCRIPTION; References; Chapter 9. POST-PARTITIONING ANALYSIS AND DEBUG; 9.1 ROLES AND RESPONSIBILITIES; 9.2 HARDWARE AND SOFTWARE MODELING AND CO-MODELING; 9.3 PARTITIONED SYSTEMS AND RE-PARTITIONING; 9.4 PRE-PARTITIONED MODEL COMPONENTS; 9.5 ABSTRACTION LEVELS
9.6 COMMUNICATION SPECIFICATION
Record Nr. UNINA-9910784656203321
Bailey Brian <1959->  
Amsterdam ; ; Boston, : Morgan Kaufmann, c2007
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
ESL design and verification : a prescription for electronic system-level methodology / / Brian Bailey, Grant Martin, Andrew Piziali
ESL design and verification : a prescription for electronic system-level methodology / / Brian Bailey, Grant Martin, Andrew Piziali
Autore Bailey Brian <1959->
Edizione [1st ed.]
Pubbl/distr/stampa Amsterdam ; ; Boston, : Morgan Kaufmann, c2007
Descrizione fisica 1 online resource (489 p.)
Disciplina 621.3815
Altri autori (Persone) MartinGrant (Grant Edmund)
PizialiAndrew
Collana The Morgan Kaufmann series in systems on silicon
Soggetto topico Systems on a chip - Design and construction
ISBN 1-281-05353-8
9786611053536
0-08-048883-8
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front cover; ESL DESIGN AND VERIFICATION; Copyright page; Table of contents; FOREWORD: ESL FROM THE TRENCHES; AUTHORS' ACKNOWLEDGMENTS; ABOUT THE AUTHORS; ABOUT THE CONTRIBUTORS; Chapter 1. WHAT IS ESL?; 1.1 SO, WHAT IS ESL?; 1.2 WHO SHOULD READ THIS BOOK; 1.3 STRUCTURE OF THE BOOK AND HOW TO READ IT; 1.4 CHAPTER LISTING; 1.5 THE PRESCRIPTION; References; Chapter 2. TAXONOMY AND DEFINITIONS FOR THE ELECTRONIC SYSTEM LEVEL; 2.1 TAXONOMY; 2.1.1 Introduction; 2.1.2 Model Taxonomy; 2.1.3 ESL Taxonomy; 2.2 DEFINITIONS; References; Chapter 3. EVOLUTION OF ESL DEVELOPMENT; 3.1 INTRODUCTION
3.2 MOTIVATION FOR ESL DESIGN3.3 TRADITIONAL SYSTEM DESIGN EFFECTIVENESS; 3.4 SYSTEM DESIGN WITH ESL METHODOLOGY; 3.5 BEHAVIORAL MODELING METHODOLOGY; 3.6 BEHAVIORAL MODELING ENVIRONMENTS; 3.7 HISTORICAL BARRIERS TO ADOPTION OF BEHAVIORAL MODELING; 3.8 AUTOMATED IMPLEMENTATION OF FIXED-FUNCTION HARDWARE; 3.9 AUTOMATED IMPLEMENTATION OF PROGRAMMABLE HARDWARE; 3.10 MAINSTREAMING ESL METHODOLOGY; 3.11 PROVOCATIVE THOUGHTS; 3.12 THE PRESCRIPTION; References; Chapter 4. WHAT ARE THE ENABLERS OF ESL?; 4.1 TOOL AND MODEL LANDSCAPE; 4.2 SYSTEM DESIGNER REQUIREMENTS; 4.3 SOFTWARE TEAM REQUIREMENTS
4.4 HARDWARE TEAM REQUIREMENTS4.5 WHO WILL SERVICE THESE DIVERSE REQUIREMENTS?; 4.6 FREE OR OPEN SOURCE SOFTWARE; 4.7 SUMMARY; 4.8 THE PRESCRIPTION; References; Chapter 5. ESL FLOW; 5.1 SPECIFICATIONS AND MODELING; 5.2 PRE-PARTITIONING ANALYSIS; 5.3 PARTITIONING; 5.4 POST-PARTITIONING ANALYSIS AND DEBUG; 5.5 POST-PARTITIONING VERIFICATION; 5.6 HARDWARE IMPLEMENTATION; 5.7 SOFTWARE IMPLEMENTATION; 5.8 USE OF ESL FOR IMPLEMENTATION VERIFICATION; 5.9 PROVOCATIVE THOUGHTS; 5.10 SUMMARY; 5.11 THE PRESCRIPTION; References; Chapter 6. SPECIFICATIONS AND MODELING; 6.1 THE PROBLEM OF SPECIFICATION
6.2 REQUIREMENTS MANAGEMENT AND PAPER SPECIFICATIONS6.3 ESL DOMAINS; 6.4 EXECUTABLE SPECIFICATIONS; 6.5 SOME ESL LANGUAGES FOR SPECIFICATION; 6.6 PROVOCATIVE THOUGHTS: MODEL-BASED DEVELOPMENT; 6.7 SUMMARY; 6.8 THE PRESCRIPTION; References; Chapter 7. PRE-PARTITIONING ANALYSIS; 7.1 STATIC ANALYSIS OF SYSTEM SPECIFICATIONS; 7.2 THE ROLE OF PLATFORM-BASED ESL DESIGN IN PRE-PARTITIONING ANALYSIS; 7.3 DYNAMIC ANALYSIS; 7.4 ALGORITHMIC ANALYSIS; 7.5 ANALYSIS SCENARIOS AND MODELING; 7.6 DOWNSTREAM USE OF ANALYSIS RESULTS; 7.7 CASE STUDY: JPEG ENCODING; 7.8 SUMMARY AND PROVOCATIVE THOUGHTS
7.9 THE PRESCRIPTIONReferences; Chapter 8. PARTITIONING; 8.1 INTRODUCTION; 8.2 FUNCTIONAL DECOMPOSITION; 8.3 ARCHITECTURE DESCRIPTION; 8.4 PARTITIONING; 8.5 THE HARDWARE PARTITION; 8.6 THE SOFTWARE PARTITION; 8.7 RECONFIGURABLE COMPUTING; 8.8 COMMUNICATION IMPLEMENTATION; 8.9 PROVOCATIVE THOUGHTS; 8.10 SUMMARY; 8.11 THE PRESCRIPTION; References; Chapter 9. POST-PARTITIONING ANALYSIS AND DEBUG; 9.1 ROLES AND RESPONSIBILITIES; 9.2 HARDWARE AND SOFTWARE MODELING AND CO-MODELING; 9.3 PARTITIONED SYSTEMS AND RE-PARTITIONING; 9.4 PRE-PARTITIONED MODEL COMPONENTS; 9.5 ABSTRACTION LEVELS
9.6 COMMUNICATION SPECIFICATION
Altri titoli varianti Electronic system-level design
Record Nr. UNINA-9910808930603321
Bailey Brian <1959->  
Amsterdam ; ; Boston, : Morgan Kaufmann, c2007
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
ISOCC : 2017 International SoC Design Conference : 5-8 November 2017, Seoul, South Korea / / Institute of Electrical and Electronics Engineers
ISOCC : 2017 International SoC Design Conference : 5-8 November 2017, Seoul, South Korea / / Institute of Electrical and Electronics Engineers
Pubbl/distr/stampa Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018
Descrizione fisica 1 online resource (323 pages)
Disciplina 621
Soggetto topico Systems on a chip - Design and construction
Electronic digital computers - Circuits
ISBN 1-5386-2285-8
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNISA-996280717403316
Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
ISOCC : 2017 International SoC Design Conference : 5-8 November 2017, Seoul, South Korea / / Institute of Electrical and Electronics Engineers
ISOCC : 2017 International SoC Design Conference : 5-8 November 2017, Seoul, South Korea / / Institute of Electrical and Electronics Engineers
Pubbl/distr/stampa Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018
Descrizione fisica 1 online resource (323 pages)
Disciplina 621
Soggetto topico Systems on a chip - Design and construction
Electronic digital computers - Circuits
ISBN 1-5386-2285-8
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNINA-9910280932003321
Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
ISOCC 2018 : International SoC Design Conference : proceedings of technical papers : November 12-15, 2018, Hotel Inter-Burgo Daegu, Daegu, Korea. / / Institute of Electrical and Electronics Engineers
ISOCC 2018 : International SoC Design Conference : proceedings of technical papers : November 12-15, 2018, Hotel Inter-Burgo Daegu, Daegu, Korea. / / Institute of Electrical and Electronics Engineers
Pubbl/distr/stampa Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018
Descrizione fisica 1 online resource (150 pages)
Disciplina 621
Soggetto topico Systems on a chip - Design and construction
Electronic digital computers - Circuits
Integrated circuits - Very large scale integration - Design and construction
Smart materials
ISBN 1-5386-7960-4
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNINA-9910312657803321
Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
ISOCC 2018 : International SoC Design Conference : proceedings of technical papers : November 12-15, 2018, Hotel Inter-Burgo Daegu, Daegu, Korea. / / Institute of Electrical and Electronics Engineers
ISOCC 2018 : International SoC Design Conference : proceedings of technical papers : November 12-15, 2018, Hotel Inter-Burgo Daegu, Daegu, Korea. / / Institute of Electrical and Electronics Engineers
Pubbl/distr/stampa Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018
Descrizione fisica 1 online resource (150 pages)
Disciplina 621
Soggetto topico Systems on a chip - Design and construction
Electronic digital computers - Circuits
Integrated circuits - Very large scale integration - Design and construction
Smart materials
ISBN 1-5386-7960-4
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNISA-996577944503316
Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
Metamodeling-driven IP reuse for SoC integration and microprocessor design / / Deepak A. Mathaikutty, Sandeep K. Shukla
Metamodeling-driven IP reuse for SoC integration and microprocessor design / / Deepak A. Mathaikutty, Sandeep K. Shukla
Autore Mathaikutty Deepak A.
Pubbl/distr/stampa Boston : , : Artech House, , ©2009
Descrizione fisica 1 online resource (310 p.)
Disciplina 621.39
621.3916
Altri autori (Persone) ShuklaSandeep K
Soggetto topico Computer software - Reusability
Computer software - Verification
Intellectual property
Microprocessors - Design and construction
System design
Systems on a chip - Design and construction
Soggetto genere / forma Electronic books.
ISBN 1-59693-425-5
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Metamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design; Contents; Preface; References; Acknowledgments; Chapter 1 Introduction; Design IP; Verification IP; Design Reuse; Verification Reuse; 1.1 ONGOING EFFORTS IN DESIGN IP REUSE; 1.2 ONGOING EFFORTS IN VERIFICATION IP REUSE; 1.3 ESSENTIAL ISSUES WITH IP REUSE; Essential Issues with Design IP Reuse; (1) IP Provider; IP Library; Documentation; Quality Assurance; Standardization; (2) IP Integrator; Exploration; Integration; Methodology and Environment; (3) Tool Developer for IP Reuse; Support for IP Provider
Support for IP IntegratorEssential Issues with Verification IP Reuse; (1) Modeling Language; (2) Generation Algorithms; 1.4 METAMODELING APPROACH TO REUSE; 1.5 PROBLEM STATEMENT; 1.6 RESEARCH CONTRIBUTIONS; 1.7 TOOLS AND TECHNIQUES DEVELOPED; References; Chapter 2 Background; 2.1 METAMODELING; 2.1.1 Implicit Metamodeling Versus Explicit Metamodeling; 2.1.2 Generic Modeling Environment; 2.2 COMPONENT COMPOSITION FRAMEWORK; 2.3 REFLECTION AND INTROSPECTION (R-I); 2.4 SYSTEMC; 2.5 MODEL-DRIVEN VALIDATION; 2.5.1 Microprocessor Validation Flow; 2.5.2 Simulation-Based Functional Validation
2.6 TEST GENERATION2.6.1 Constraint Programming; 2.6.2 Esterel Studio; 2.7 COVERAGE-DIRECTED TEST GENERATION; 2.7.1 Structural Coverage; 2.7.2 Functional Coverage; 2.7.3 Property Specification Language (PSL); 2.7.4 Fault Classification; References; Chapter 3 Related Work; 3.1 COMPONENT COMPOSITION FRAMEWORK; 3.1.1 The BALBOA Framework; 3.1.2 Liberty Simulation Environment (LSE); 3.1.3 EWD; 3.1.4 Ptolemy II; 3.1.5 Metropolis; 3.2 COMPONENT-BASED SOFTWARE DESIGN ENVIRONMENTS; 3.3 IP INTERFACING STANDARDS; 3.3.1 SPIRIT; 3.4 EXISTING TOOLS FOR STRUCTURAL REFLECTION
3.5 ARCHITECTURE DESCRIPTION LANGUAGES3.6 TEST GENERATION; References; Part I Design Reuse; Chapter 4 A Metamodel for Component Composition; 4.1 CC LANGUAGE, METAMODEL, AND MODEL; 4.1.1 Component Composition Language (CCL); 4.1.2 Component Composition Metamodel (CCMM); 4.1.3 Component Composition Model (CCM); 4.2 CC ANALYSIS AND TRANSLATION; 4.2.1 Consistency Checking; 4.2.2 Type Inference; 4.2.3 XML Translation; 4.3 CASE STUDIES; 4.3.1 AMBA AHB RTL Bus Model; 4.3.2 Simple Bus TL Model; 4.4 DESIGN EXPERIENCE AND SUMMARY; References; Chapter 5 IP Reflection and Selection
5.1 METADATA FOR IP COMPOSITION5.2 METADATA ON A SYSTEMC IP SPECIFICATION; 5.3 TOOLS AND METHODOLOGY; 5.3.1 Stage 1: SystemC Parsing; 5.3.2 Stage 2: AST Parsing and DOM Population; 5.3.3 Stage 3: Processing and Constraining DOM; 5.4 IP SELECTION; 5.4.1 Illustrative Example; 5.5 CASE STUDY; 5.6 SUMMARY; References; Chapter 6 Typing Problems in IP Composition; 6.1 MCF TYPE DEFINITIONS; 6.1.1 Component Composition Language; 6.1.2 IP Library; 6.2 TYPE RESOLUTION IN MCF; 6.2.1 Type Inference on Architectural Template; 6.2.2 Type Substitution Using IP Library; 6.3 COMPARATIVE STUDY; 6.4 CASE STUDY
6.5 SUMMARY
Record Nr. UNINA-9910456628003321
Mathaikutty Deepak A.  
Boston : , : Artech House, , ©2009
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Metamodeling-driven IP reuse for SoC integration and microprocessor design / / Deepak A. Mathaikutty, Sandeep K. Shukla
Metamodeling-driven IP reuse for SoC integration and microprocessor design / / Deepak A. Mathaikutty, Sandeep K. Shukla
Autore Mathaikutty Deepak A.
Pubbl/distr/stampa Boston : , : Artech House, , ©2009
Descrizione fisica 1 online resource (310 p.)
Disciplina 621.39
621.3916
Altri autori (Persone) ShuklaSandeep K
Soggetto topico Computer software - Reusability
Computer software - Verification
Intellectual property
Microprocessors - Design and construction
System design
Systems on a chip - Design and construction
ISBN 1-59693-425-5
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Metamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design; Contents; Preface; References; Acknowledgments; Chapter 1 Introduction; Design IP; Verification IP; Design Reuse; Verification Reuse; 1.1 ONGOING EFFORTS IN DESIGN IP REUSE; 1.2 ONGOING EFFORTS IN VERIFICATION IP REUSE; 1.3 ESSENTIAL ISSUES WITH IP REUSE; Essential Issues with Design IP Reuse; (1) IP Provider; IP Library; Documentation; Quality Assurance; Standardization; (2) IP Integrator; Exploration; Integration; Methodology and Environment; (3) Tool Developer for IP Reuse; Support for IP Provider
Support for IP IntegratorEssential Issues with Verification IP Reuse; (1) Modeling Language; (2) Generation Algorithms; 1.4 METAMODELING APPROACH TO REUSE; 1.5 PROBLEM STATEMENT; 1.6 RESEARCH CONTRIBUTIONS; 1.7 TOOLS AND TECHNIQUES DEVELOPED; References; Chapter 2 Background; 2.1 METAMODELING; 2.1.1 Implicit Metamodeling Versus Explicit Metamodeling; 2.1.2 Generic Modeling Environment; 2.2 COMPONENT COMPOSITION FRAMEWORK; 2.3 REFLECTION AND INTROSPECTION (R-I); 2.4 SYSTEMC; 2.5 MODEL-DRIVEN VALIDATION; 2.5.1 Microprocessor Validation Flow; 2.5.2 Simulation-Based Functional Validation
2.6 TEST GENERATION2.6.1 Constraint Programming; 2.6.2 Esterel Studio; 2.7 COVERAGE-DIRECTED TEST GENERATION; 2.7.1 Structural Coverage; 2.7.2 Functional Coverage; 2.7.3 Property Specification Language (PSL); 2.7.4 Fault Classification; References; Chapter 3 Related Work; 3.1 COMPONENT COMPOSITION FRAMEWORK; 3.1.1 The BALBOA Framework; 3.1.2 Liberty Simulation Environment (LSE); 3.1.3 EWD; 3.1.4 Ptolemy II; 3.1.5 Metropolis; 3.2 COMPONENT-BASED SOFTWARE DESIGN ENVIRONMENTS; 3.3 IP INTERFACING STANDARDS; 3.3.1 SPIRIT; 3.4 EXISTING TOOLS FOR STRUCTURAL REFLECTION
3.5 ARCHITECTURE DESCRIPTION LANGUAGES3.6 TEST GENERATION; References; Part I Design Reuse; Chapter 4 A Metamodel for Component Composition; 4.1 CC LANGUAGE, METAMODEL, AND MODEL; 4.1.1 Component Composition Language (CCL); 4.1.2 Component Composition Metamodel (CCMM); 4.1.3 Component Composition Model (CCM); 4.2 CC ANALYSIS AND TRANSLATION; 4.2.1 Consistency Checking; 4.2.2 Type Inference; 4.2.3 XML Translation; 4.3 CASE STUDIES; 4.3.1 AMBA AHB RTL Bus Model; 4.3.2 Simple Bus TL Model; 4.4 DESIGN EXPERIENCE AND SUMMARY; References; Chapter 5 IP Reflection and Selection
5.1 METADATA FOR IP COMPOSITION5.2 METADATA ON A SYSTEMC IP SPECIFICATION; 5.3 TOOLS AND METHODOLOGY; 5.3.1 Stage 1: SystemC Parsing; 5.3.2 Stage 2: AST Parsing and DOM Population; 5.3.3 Stage 3: Processing and Constraining DOM; 5.4 IP SELECTION; 5.4.1 Illustrative Example; 5.5 CASE STUDY; 5.6 SUMMARY; References; Chapter 6 Typing Problems in IP Composition; 6.1 MCF TYPE DEFINITIONS; 6.1.1 Component Composition Language; 6.1.2 IP Library; 6.2 TYPE RESOLUTION IN MCF; 6.2.1 Type Inference on Architectural Template; 6.2.2 Type Substitution Using IP Library; 6.3 COMPARATIVE STUDY; 6.4 CASE STUDY
6.5 SUMMARY
Record Nr. UNINA-9910780935303321
Mathaikutty Deepak A.  
Boston : , : Artech House, , ©2009
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Metamodeling-driven IP reuse for SoC integration and microprocessor design / / Deepak A. Mathaikutty, Sandeep K. Shukla
Metamodeling-driven IP reuse for SoC integration and microprocessor design / / Deepak A. Mathaikutty, Sandeep K. Shukla
Autore Mathaikutty Deepak A
Edizione [1st ed.]
Pubbl/distr/stampa Boston ; ; London, : Artech House, c2009
Descrizione fisica 1 online resource (310 p.)
Disciplina 621.39
621.3916
Altri autori (Persone) ShuklaSandeep K
Soggetto topico Computer software - Reusability
Computer software - Verification
Intellectual property
Microprocessors - Design and construction
System design
Systems on a chip - Design and construction
ISBN 1-59693-425-5
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Metamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design; Contents; Preface; References; Acknowledgments; Chapter 1 Introduction; Design IP; Verification IP; Design Reuse; Verification Reuse; 1.1 ONGOING EFFORTS IN DESIGN IP REUSE; 1.2 ONGOING EFFORTS IN VERIFICATION IP REUSE; 1.3 ESSENTIAL ISSUES WITH IP REUSE; Essential Issues with Design IP Reuse; (1) IP Provider; IP Library; Documentation; Quality Assurance; Standardization; (2) IP Integrator; Exploration; Integration; Methodology and Environment; (3) Tool Developer for IP Reuse; Support for IP Provider
Support for IP IntegratorEssential Issues with Verification IP Reuse; (1) Modeling Language; (2) Generation Algorithms; 1.4 METAMODELING APPROACH TO REUSE; 1.5 PROBLEM STATEMENT; 1.6 RESEARCH CONTRIBUTIONS; 1.7 TOOLS AND TECHNIQUES DEVELOPED; References; Chapter 2 Background; 2.1 METAMODELING; 2.1.1 Implicit Metamodeling Versus Explicit Metamodeling; 2.1.2 Generic Modeling Environment; 2.2 COMPONENT COMPOSITION FRAMEWORK; 2.3 REFLECTION AND INTROSPECTION (R-I); 2.4 SYSTEMC; 2.5 MODEL-DRIVEN VALIDATION; 2.5.1 Microprocessor Validation Flow; 2.5.2 Simulation-Based Functional Validation
2.6 TEST GENERATION2.6.1 Constraint Programming; 2.6.2 Esterel Studio; 2.7 COVERAGE-DIRECTED TEST GENERATION; 2.7.1 Structural Coverage; 2.7.2 Functional Coverage; 2.7.3 Property Specification Language (PSL); 2.7.4 Fault Classification; References; Chapter 3 Related Work; 3.1 COMPONENT COMPOSITION FRAMEWORK; 3.1.1 The BALBOA Framework; 3.1.2 Liberty Simulation Environment (LSE); 3.1.3 EWD; 3.1.4 Ptolemy II; 3.1.5 Metropolis; 3.2 COMPONENT-BASED SOFTWARE DESIGN ENVIRONMENTS; 3.3 IP INTERFACING STANDARDS; 3.3.1 SPIRIT; 3.4 EXISTING TOOLS FOR STRUCTURAL REFLECTION
3.5 ARCHITECTURE DESCRIPTION LANGUAGES3.6 TEST GENERATION; References; Part I Design Reuse; Chapter 4 A Metamodel for Component Composition; 4.1 CC LANGUAGE, METAMODEL, AND MODEL; 4.1.1 Component Composition Language (CCL); 4.1.2 Component Composition Metamodel (CCMM); 4.1.3 Component Composition Model (CCM); 4.2 CC ANALYSIS AND TRANSLATION; 4.2.1 Consistency Checking; 4.2.2 Type Inference; 4.2.3 XML Translation; 4.3 CASE STUDIES; 4.3.1 AMBA AHB RTL Bus Model; 4.3.2 Simple Bus TL Model; 4.4 DESIGN EXPERIENCE AND SUMMARY; References; Chapter 5 IP Reflection and Selection
5.1 METADATA FOR IP COMPOSITION5.2 METADATA ON A SYSTEMC IP SPECIFICATION; 5.3 TOOLS AND METHODOLOGY; 5.3.1 Stage 1: SystemC Parsing; 5.3.2 Stage 2: AST Parsing and DOM Population; 5.3.3 Stage 3: Processing and Constraining DOM; 5.4 IP SELECTION; 5.4.1 Illustrative Example; 5.5 CASE STUDY; 5.6 SUMMARY; References; Chapter 6 Typing Problems in IP Composition; 6.1 MCF TYPE DEFINITIONS; 6.1.1 Component Composition Language; 6.1.2 IP Library; 6.2 TYPE RESOLUTION IN MCF; 6.2.1 Type Inference on Architectural Template; 6.2.2 Type Substitution Using IP Library; 6.3 COMPARATIVE STUDY; 6.4 CASE STUDY
6.5 SUMMARY
Record Nr. UNINA-9910825013703321
Mathaikutty Deepak A  
Boston ; ; London, : Artech House, c2009
Materiale a stampa
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