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Multi-processor system-on-chip 2 : applications / / Liliana Andrade, Frédéric Rousseau
| Multi-processor system-on-chip 2 : applications / / Liliana Andrade, Frédéric Rousseau |
| Autore | Rousseau Frédéric <1967-> |
| Pubbl/distr/stampa | Hoboken, NJ : , : Wiley, , [2021] |
| Descrizione fisica | 1 online resource (271 pages) |
| Disciplina | 006.22 |
| Soggetto topico |
Multiprocessors
Systems on a chip |
| ISBN |
1-119-81840-0
1-119-81838-9 1-119-81841-9 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910676632603321 |
Rousseau Frédéric <1967->
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| Hoboken, NJ : , : Wiley, , [2021] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Multi-processor system-on-chip 2 : applications / / Liliana Andrade, Frédéric Rousseau
| Multi-processor system-on-chip 2 : applications / / Liliana Andrade, Frédéric Rousseau |
| Autore | Rousseau Frédéric <1967-> |
| Pubbl/distr/stampa | Hoboken, NJ : , : Wiley, , [2021] |
| Descrizione fisica | 1 online resource (271 pages) |
| Disciplina | 006.22 |
| Soggetto topico |
Multiprocessors
Systems on a chip |
| ISBN |
1-119-81840-0
1-119-81838-9 1-119-81841-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910811305803321 |
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Rousseau Frédéric <1967->
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| Hoboken, NJ : , : Wiley, , [2021] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Multicore software development techniques : applications, tips, and tricks / / Rob Oshana
| Multicore software development techniques : applications, tips, and tricks / / Rob Oshana |
| Autore | Oshana Robert |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam : , : Elsevier : , : Newnes, , [2016] |
| Descrizione fisica | 1 online resource (233 p.) |
| Disciplina | 005.2/75 |
| Collana | Newnes Pocket Bks. |
| Soggetto topico |
Parallel programming (Computer science)
Multiprocessors Computer software - Development Systems on a chip |
| ISBN |
0-12-800958-6
0-12-801037-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Multicore Software Development Techniques; Copyright Page; Dedication; Contents; 1 Principles of Parallel Computing; 1.1 Concurrency versus Parallelism; 1.2 Symmetric and Asymmetric Multiprocessing; 1.2.1 Symmetric Multiprocessing; 1.2.2 Asymmetric Multiprocessing; 1.3 Parallelism Saves Power; 1.3.1 Limit: "Hidden Parallelism" Gains are Slowing Down; 1.3.2 Another Limit: Chip Yield and Process Technologies; 1.3.3 Another Limit: Basic Laws of Physics and the Speed of Light; 1.4 Key Challenges of Parallel Computing; 1.4.1 Finding Enough Parallelism; 1.4.2 Data Dependencies
1.4.3 Achieving the Right Level of Granularity1.4.4 Locality and Parallelism; 1.4.5 Load Imbalance; 1.4.6 Speedup; 1.4.7 Directed Graphs; 2 Parallelism in All of Its Forms; 2.1 Bit-Level Parallelism; 2.2 Instruction-Level Parallelism (ILP); 2.3 Simultaneous Multithreading; 2.4 Single Instruction, Multiple Data (SIMD); 2.5 Data Parallelism; 2.6 Task Parallelism; 2.7 Acceleration and Offload Engines; 3 Multicore System Architectures; 3.1 Shared Memory Multicore Systems; 3.2 Cache Coherency; 3.3 Shared Data Synchronization; 3.4 Distributed Memory; 3.5 Symmetric Multiprocessing 3.6 Asymmetric Multiprocessing3.7 Hybrid Approaches; 3.8 Speaking of Cores; 3.9 Graphical Processing Units (GPU); 3.10 Putting It All Together; 4 Multicore Software Architectures; 4.1 Multicore Software Architectures; 4.1.1 Master/Worker; 4.1.2 Peer; 4.1.3 Pipelined; 4.2 A Decision Tree Approach to Selecting a Multicore Architecture; 4.2.1 Decision 1: Select the Programming Model; 4.2.2 Decision 2: Choose the Operating System Framework; 4.2.3 Decision 3: Determine the Control Plane and Data Plane Model 4.2.4 Decisions 4 and 5: Choose the Type of Operating System Needed for the Control Plane and Data Plane4.2.5 Decision 6: Determine the Type of Acceleration Needed; 5 Multicore Software Development Process; 5.1 Multicore Programming Models; 6 Putting it All Together, A Case Study of Multicore Development; 6.1 Multiple-Single-Cores; 6.2 Cooperating-Multiple-Cores; 6.3 Getting Started; 6.3.1 JPEG Encoding Application; 6.4 System Requirements; 6.4.1 Intercore Communication; 6.4.2 Master-and-Slaves Implementation; 7 Multicore Virtualization; 7.1 Hypervisor Classifications 7.2 Virtualization Use Cases for Multicore7.3 Linux Hypervisors; 7.4 Virtual Networking in Multicore; 7.5 I/O Activity in a Virtualized Environment; 7.6 Direct Device Assignment; 8 Performance and Optimization of Multicore Systems; 8.1 Select the Right "Core" for Your Multicore; 8.2 Improve Serial Performance before Migrating to Multicore (Especially ILP); 8.3 Achieve Proper Load Balancing (SMP Linux) and Scheduling; 8.4 Improve Data Locality; 8.5 Reduce or Eliminate False Sharing; 8.6 Use Affinity Scheduling When Necessary; 8.7 Apply the Proper Lock Granularity and Frequency 8.8 Remove Sync Barriers Where Possible |
| Record Nr. | UNINA-9910797826403321 |
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Oshana Robert
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| Amsterdam : , : Elsevier : , : Newnes, , [2016] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Multicore software development techniques : applications, tips, and tricks / / Rob Oshana
| Multicore software development techniques : applications, tips, and tricks / / Rob Oshana |
| Autore | Oshana Robert |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam : , : Elsevier : , : Newnes, , [2016] |
| Descrizione fisica | 1 online resource (233 p.) |
| Disciplina | 005.2/75 |
| Collana | Newnes Pocket Bks. |
| Soggetto topico |
Parallel programming (Computer science)
Multiprocessors Computer software - Development Systems on a chip |
| ISBN |
0-12-800958-6
0-12-801037-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Multicore Software Development Techniques; Copyright Page; Dedication; Contents; 1 Principles of Parallel Computing; 1.1 Concurrency versus Parallelism; 1.2 Symmetric and Asymmetric Multiprocessing; 1.2.1 Symmetric Multiprocessing; 1.2.2 Asymmetric Multiprocessing; 1.3 Parallelism Saves Power; 1.3.1 Limit: "Hidden Parallelism" Gains are Slowing Down; 1.3.2 Another Limit: Chip Yield and Process Technologies; 1.3.3 Another Limit: Basic Laws of Physics and the Speed of Light; 1.4 Key Challenges of Parallel Computing; 1.4.1 Finding Enough Parallelism; 1.4.2 Data Dependencies
1.4.3 Achieving the Right Level of Granularity1.4.4 Locality and Parallelism; 1.4.5 Load Imbalance; 1.4.6 Speedup; 1.4.7 Directed Graphs; 2 Parallelism in All of Its Forms; 2.1 Bit-Level Parallelism; 2.2 Instruction-Level Parallelism (ILP); 2.3 Simultaneous Multithreading; 2.4 Single Instruction, Multiple Data (SIMD); 2.5 Data Parallelism; 2.6 Task Parallelism; 2.7 Acceleration and Offload Engines; 3 Multicore System Architectures; 3.1 Shared Memory Multicore Systems; 3.2 Cache Coherency; 3.3 Shared Data Synchronization; 3.4 Distributed Memory; 3.5 Symmetric Multiprocessing 3.6 Asymmetric Multiprocessing3.7 Hybrid Approaches; 3.8 Speaking of Cores; 3.9 Graphical Processing Units (GPU); 3.10 Putting It All Together; 4 Multicore Software Architectures; 4.1 Multicore Software Architectures; 4.1.1 Master/Worker; 4.1.2 Peer; 4.1.3 Pipelined; 4.2 A Decision Tree Approach to Selecting a Multicore Architecture; 4.2.1 Decision 1: Select the Programming Model; 4.2.2 Decision 2: Choose the Operating System Framework; 4.2.3 Decision 3: Determine the Control Plane and Data Plane Model 4.2.4 Decisions 4 and 5: Choose the Type of Operating System Needed for the Control Plane and Data Plane4.2.5 Decision 6: Determine the Type of Acceleration Needed; 5 Multicore Software Development Process; 5.1 Multicore Programming Models; 6 Putting it All Together, A Case Study of Multicore Development; 6.1 Multiple-Single-Cores; 6.2 Cooperating-Multiple-Cores; 6.3 Getting Started; 6.3.1 JPEG Encoding Application; 6.4 System Requirements; 6.4.1 Intercore Communication; 6.4.2 Master-and-Slaves Implementation; 7 Multicore Virtualization; 7.1 Hypervisor Classifications 7.2 Virtualization Use Cases for Multicore7.3 Linux Hypervisors; 7.4 Virtual Networking in Multicore; 7.5 I/O Activity in a Virtualized Environment; 7.6 Direct Device Assignment; 8 Performance and Optimization of Multicore Systems; 8.1 Select the Right "Core" for Your Multicore; 8.2 Improve Serial Performance before Migrating to Multicore (Especially ILP); 8.3 Achieve Proper Load Balancing (SMP Linux) and Scheduling; 8.4 Improve Data Locality; 8.5 Reduce or Eliminate False Sharing; 8.6 Use Affinity Scheduling When Necessary; 8.7 Apply the Proper Lock Granularity and Frequency 8.8 Remove Sync Barriers Where Possible |
| Record Nr. | UNINA-9910819381503321 |
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Oshana Robert
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| Amsterdam : , : Elsevier : , : Newnes, , [2016] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Multicore systems on-chip : practical software/hardware design / / Abderazek Ben Abdallah
| Multicore systems on-chip : practical software/hardware design / / Abderazek Ben Abdallah |
| Autore | Ben Abdallah Abderazek |
| Edizione | [2nd ed.] |
| Pubbl/distr/stampa | New York, : Springer, 2013 |
| Descrizione fisica | 1 online resource (xxvi, 273 pages) : illustrations (some color) |
| Disciplina |
004.21
006.2 006.2/2 |
| Collana | Atlantis ambient and pervasive intelligence |
| Soggetto topico |
Systems on a chip
Software architecture |
| ISBN | 94-91216-92-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction to Multicore Systems On-Chip -- Multicore SoCs Design Methods -- Multicore SoC Organization -- 2D Network-on-Chip -- 3D Network-on-Chip -- Network Interface Architecture and Design for 2D/3D NoCs -- Parallelizing Compiler for Single and Multicore Computing -- Power Optimization Techniques for Multicore SoCs -- Soft-Core Processor for Low-Power Embedded -- Dual-Execution Processor Architecture for Embedded -- Case Study: Deign of Embedded Multicore SoC. |
| Record Nr. | UNINA-9910437959803321 |
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Ben Abdallah Abderazek
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| New York, : Springer, 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Networks on chips [[electronic resource] ] : technology and tools / / Luca Benini and Giovanni De Micheli
| Networks on chips [[electronic resource] ] : technology and tools / / Luca Benini and Giovanni De Micheli |
| Autore | Benini Luca <1967-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006 |
| Descrizione fisica | 1 online resource (408 p.) |
| Disciplina | 621.3815 |
| Altri autori (Persone) | De MicheliGiovanni |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Systems on a chip
Computer networks - Equipment and supplies |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-280-96683-1
9786610966837 0-08-047356-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Title page; Copyright Page; Table of contents; About The Authors; List of Contributors; 1 Networks on Chip; 1.1 Why On-Chip Networking?; 1.2 Technology Trends; 1.3 SoC Objectives and NoC Needs; 1.4 Once Over Lightly; 1.5 Perspectives; 2 Network Architecture: Principles and Examples; 2.1 Network Architecture; 2.2 Network Architectures for On-Chip Realization; 2.3 Ad Hoc Network Architectures; 2.4 Component Design for NoCs; 2.5 Properties of Network Architectures; 2.6 Summary; 3 Physical Network Layer; 3.1 Interconnection in DSM SoC; 3.2 High-Performance Signaling
3.3 Building Blocks3.4 Summary; 4 The Data-Link Layer in NoC Design; 4.1 Tasks of the Data-Link Layer; 4.2 On-Chip Communication Reliability; 4.3 Fault Models for NoCs; 4.4 Principles of Coding Theory; 4.5 The Power-Reliability Trade-Off; 4.6 Unified Coding Framework; 4.7 Adaptive Error Protection; 4.8 Data-Link Layer Architecture: Case Studies; 4.9 On-Chip Stochastic Communication; 4.10 Link-Level versus End-to-End Error Protection; 4.11 Flow Control; 4.12 Performance Exploration; 4.13 Summary; 5 Network and Transport Layers in Network on Chip; 5.1 Network and Transport Layers in NoCs 5.2 NoC QoS5.3 NoC Topology; 5.4 Switching Techniques; 5.5 NoC Addressing and Routing; 5.6 NoC Addressing; 5.7 Congestion Control and Flow Control; 5.8 Summary; 6 Network Interface Architecture and Design Issues; 6.1 NI Services; 6.2 NI Structure; 6.3 Evolution of Communication Protocols; 6.4 Point-to-Point Communication Protocols; 6.5 Latest Advances in Processor Interfaces; 6.6 The Packetization Stage; 6.7 End-to-End Flow Control; 6.8 Packet and Circuit Switching; 6.9 NI Architecture: The Aethereal Case Study; 6.10 NI Architecture: The xpipes Case Study 6.11 NIs for Asynchronous NoCs: The Mango Case Study6.12 Summary; 7 NoC Programming; 7.1 Architectural Template; 7.2 Task-Level Parallel Programming; 7.3 Communication-Exposed Programming; 7.4 Computer-Aided Software Development Tools; 7.5 Summary; 8 Design Methodologies and CAD Tool Flows for NoCs; 8.1 Network Analysis and Simulation; 8.2 Network Synthesis and Optimization; 8.3 Design Flows for NoCs; 8.4 Tool Kits for Designing Bus-Based Interconnect; 8.5 Summary; 9 Designs and Implementations of NoC-Based SoCs; 9.1 KAIST BONE Series; 9.2 NoC-Based Experimental Systems; 9.3 Summary; Index |
| Record Nr. | UNINA-9910458595103321 |
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Benini Luca <1967->
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| Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Networks on chips [[electronic resource] ] : technology and tools / / Luca Benini and Giovanni De Micheli
| Networks on chips [[electronic resource] ] : technology and tools / / Luca Benini and Giovanni De Micheli |
| Autore | Benini Luca <1967-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006 |
| Descrizione fisica | 1 online resource (408 p.) |
| Disciplina | 621.3815 |
| Altri autori (Persone) | De MicheliGiovanni |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Systems on a chip
Computer networks - Equipment and supplies |
| ISBN |
1-280-96683-1
9786610966837 0-08-047356-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Title page; Copyright Page; Table of contents; About The Authors; List of Contributors; 1 Networks on Chip; 1.1 Why On-Chip Networking?; 1.2 Technology Trends; 1.3 SoC Objectives and NoC Needs; 1.4 Once Over Lightly; 1.5 Perspectives; 2 Network Architecture: Principles and Examples; 2.1 Network Architecture; 2.2 Network Architectures for On-Chip Realization; 2.3 Ad Hoc Network Architectures; 2.4 Component Design for NoCs; 2.5 Properties of Network Architectures; 2.6 Summary; 3 Physical Network Layer; 3.1 Interconnection in DSM SoC; 3.2 High-Performance Signaling
3.3 Building Blocks3.4 Summary; 4 The Data-Link Layer in NoC Design; 4.1 Tasks of the Data-Link Layer; 4.2 On-Chip Communication Reliability; 4.3 Fault Models for NoCs; 4.4 Principles of Coding Theory; 4.5 The Power-Reliability Trade-Off; 4.6 Unified Coding Framework; 4.7 Adaptive Error Protection; 4.8 Data-Link Layer Architecture: Case Studies; 4.9 On-Chip Stochastic Communication; 4.10 Link-Level versus End-to-End Error Protection; 4.11 Flow Control; 4.12 Performance Exploration; 4.13 Summary; 5 Network and Transport Layers in Network on Chip; 5.1 Network and Transport Layers in NoCs 5.2 NoC QoS5.3 NoC Topology; 5.4 Switching Techniques; 5.5 NoC Addressing and Routing; 5.6 NoC Addressing; 5.7 Congestion Control and Flow Control; 5.8 Summary; 6 Network Interface Architecture and Design Issues; 6.1 NI Services; 6.2 NI Structure; 6.3 Evolution of Communication Protocols; 6.4 Point-to-Point Communication Protocols; 6.5 Latest Advances in Processor Interfaces; 6.6 The Packetization Stage; 6.7 End-to-End Flow Control; 6.8 Packet and Circuit Switching; 6.9 NI Architecture: The Aethereal Case Study; 6.10 NI Architecture: The xpipes Case Study 6.11 NIs for Asynchronous NoCs: The Mango Case Study6.12 Summary; 7 NoC Programming; 7.1 Architectural Template; 7.2 Task-Level Parallel Programming; 7.3 Communication-Exposed Programming; 7.4 Computer-Aided Software Development Tools; 7.5 Summary; 8 Design Methodologies and CAD Tool Flows for NoCs; 8.1 Network Analysis and Simulation; 8.2 Network Synthesis and Optimization; 8.3 Design Flows for NoCs; 8.4 Tool Kits for Designing Bus-Based Interconnect; 8.5 Summary; 9 Designs and Implementations of NoC-Based SoCs; 9.1 KAIST BONE Series; 9.2 NoC-Based Experimental Systems; 9.3 Summary; Index |
| Record Nr. | UNINA-9910784651503321 |
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Benini Luca <1967->
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| Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Networks on chips : technology and tools / / Luca Benini and Giovanni De Micheli
| Networks on chips : technology and tools / / Luca Benini and Giovanni De Micheli |
| Autore | Benini Luca <1967-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006 |
| Descrizione fisica | 1 online resource (408 p.) |
| Disciplina | 621.3815 |
| Altri autori (Persone) | De MicheliGiovanni |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Systems on a chip
Computer networks - Equipment and supplies |
| ISBN |
1-280-96683-1
9786610966837 0-08-047356-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Title page; Copyright Page; Table of contents; About The Authors; List of Contributors; 1 Networks on Chip; 1.1 Why On-Chip Networking?; 1.2 Technology Trends; 1.3 SoC Objectives and NoC Needs; 1.4 Once Over Lightly; 1.5 Perspectives; 2 Network Architecture: Principles and Examples; 2.1 Network Architecture; 2.2 Network Architectures for On-Chip Realization; 2.3 Ad Hoc Network Architectures; 2.4 Component Design for NoCs; 2.5 Properties of Network Architectures; 2.6 Summary; 3 Physical Network Layer; 3.1 Interconnection in DSM SoC; 3.2 High-Performance Signaling
3.3 Building Blocks3.4 Summary; 4 The Data-Link Layer in NoC Design; 4.1 Tasks of the Data-Link Layer; 4.2 On-Chip Communication Reliability; 4.3 Fault Models for NoCs; 4.4 Principles of Coding Theory; 4.5 The Power-Reliability Trade-Off; 4.6 Unified Coding Framework; 4.7 Adaptive Error Protection; 4.8 Data-Link Layer Architecture: Case Studies; 4.9 On-Chip Stochastic Communication; 4.10 Link-Level versus End-to-End Error Protection; 4.11 Flow Control; 4.12 Performance Exploration; 4.13 Summary; 5 Network and Transport Layers in Network on Chip; 5.1 Network and Transport Layers in NoCs 5.2 NoC QoS5.3 NoC Topology; 5.4 Switching Techniques; 5.5 NoC Addressing and Routing; 5.6 NoC Addressing; 5.7 Congestion Control and Flow Control; 5.8 Summary; 6 Network Interface Architecture and Design Issues; 6.1 NI Services; 6.2 NI Structure; 6.3 Evolution of Communication Protocols; 6.4 Point-to-Point Communication Protocols; 6.5 Latest Advances in Processor Interfaces; 6.6 The Packetization Stage; 6.7 End-to-End Flow Control; 6.8 Packet and Circuit Switching; 6.9 NI Architecture: The Aethereal Case Study; 6.10 NI Architecture: The xpipes Case Study 6.11 NIs for Asynchronous NoCs: The Mango Case Study6.12 Summary; 7 NoC Programming; 7.1 Architectural Template; 7.2 Task-Level Parallel Programming; 7.3 Communication-Exposed Programming; 7.4 Computer-Aided Software Development Tools; 7.5 Summary; 8 Design Methodologies and CAD Tool Flows for NoCs; 8.1 Network Analysis and Simulation; 8.2 Network Synthesis and Optimization; 8.3 Design Flows for NoCs; 8.4 Tool Kits for Designing Bus-Based Interconnect; 8.5 Summary; 9 Designs and Implementations of NoC-Based SoCs; 9.1 KAIST BONE Series; 9.2 NoC-Based Experimental Systems; 9.3 Summary; Index |
| Record Nr. | UNINA-9910809103403321 |
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Benini Luca <1967->
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| Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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NoCArc 2015 : eighth International Workshop on Network on Chip Architectures / / sponsor, ACM
| NoCArc 2015 : eighth International Workshop on Network on Chip Architectures / / sponsor, ACM |
| Pubbl/distr/stampa | New York : , : ACM, , 2015 |
| Descrizione fisica | 1 online resource (47 pages) |
| Disciplina | 004.22 |
| Soggetto topico |
Computer architecture
Networks on a chip Systems on a chip |
| ISBN | 1-4503-3963-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
Network on Chip Architectures 2015
Proceedings of the 8th International Workshop on Network on Chip Architectures |
| Record Nr. | UNINA-9910376538203321 |
| New York : , : ACM, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Pipelined multiprocessor system-on-chip for multimedia / / Haris Javaid, Sri Parameswaran
| Pipelined multiprocessor system-on-chip for multimedia / / Haris Javaid, Sri Parameswaran |
| Autore | Javaid Haris |
| Edizione | [1st ed. 2014.] |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , 2014 |
| Descrizione fisica | 1 online resource (viii, 169 pages) : illustrations (some color) |
| Disciplina | 004.35 |
| Collana | Gale eBooks |
| Soggetto topico |
Embedded computer systems - Design and construction
Multiprocessors Systems on a chip |
| ISBN | 3-319-01113-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Literature Survey -- Optimisation Framework -- Performance Estimation of Pipelined MPSoCs -- Design Space Exploration of Pipelined MPSoCs -- Adaptive Pipelined MPSoCs -- Power Management in Adaptive Pipelined MPSocs -- Multi-mode Pipelined MPSoCs -- Conclusions and Future Work. |
| Record Nr. | UNINA-9910299471103321 |
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Javaid Haris
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| Cham, Switzerland : , : Springer, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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