Info
- Utilizzare la checkbox di selezione a fianco di ciascun documento per attivare le funzionalità di stampa, invio email, download nei formati disponibili del (i) record.
IWSOC 2004 : 4th IEEE International Workshop on System-on-Chip for Real-Time Applications : proceedings : 19-21 July, 2004, Banff, Alberta, Canada
| IWSOC 2004 : 4th IEEE International Workshop on System-on-Chip for Real-Time Applications : proceedings : 19-21 July, 2004, Banff, Alberta, Canada |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society, 2004 |
| Disciplina | 621.3815 |
| Soggetto topico |
Application specific integrated circuits - Design and construction
Systems on a chip Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910872521003321 |
| [Place of publication not identified], : IEEE Computer Society, 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Micro, nanosystems, and systems on chips [[electronic resource]] : modeling, control, and estimation / / edited by Alina Voda
| Micro, nanosystems, and systems on chips [[electronic resource]] : modeling, control, and estimation / / edited by Alina Voda |
| Pubbl/distr/stampa | London, : ISTE |
| Descrizione fisica | 1 online resource (330 p.) |
| Disciplina | 621.381 |
| Altri autori (Persone) | VodaAlina |
| Collana | ISTE |
| Soggetto topico |
Microelectromechanical systems
Systems on a chip |
| ISBN |
1-118-55781-6
1-299-31845-2 1-118-62267-7 1-61344-555-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover; Title Page; Copyright Page; Table of Contents; Introduction; PART I. MINI AND MICROSYSTEMS; Chapter 1. Modeling and Control of Stick-slip Micropositioning Devices; 1.1. Introduction; 1.2. General description of stick-slip micropositioning devices; 1.2.1. Principle; 1.2.2. Experimental device; 1.3. Model of the sub-step mode; 1.3.1. Assumptions; 1.3.2. Microactuator equation; 1.3.3. The elastoplastic friction model; 1.3.4. The state equation; 1.3.5. The output equation; 1.3.6. Experimental and simulation curves; 1.4. PI control of the sub-step mode; 1.5. Modeling the coarse mode
1.5.1. The model1.5.2. Experimental results; 1.5.3. Remarks; 1.6. Voltage/frequency (U/f) proportional control of the coarse mode; 1.6.1. Principle scheme of the proposed controller; 1.6.2. Analysis; 1.6.3. Stability analysis; 1.6.4. Experiments; 1.7. Conclusion; 1.8. Bibliography; Chapter 2. Microbeam Dynamic Shaping by Closed-loop Electrostatic Actuation using Modal Control; 2.1. Introduction; 2.2. System description; 2.3. Modal analysis; 2.4. Mode-based control; 2.4.1. PID control; 2.4.2. FSF-LTR control; 2.5. Conclusion; 2.6. Bibliography; PART II. NANOSYSTEMS AND NANOWORLD Chapter 3. Observer-based Estimation of Weak Forces in a Nanosystem Measurement Device 3.1. Introduction; 3.2. Observer approach in an AFM measurement set-up; 3.2.1. Considered AFM model and force measurement problem; 3.2.2. Proposed observer approach; 3.2.3. Experimental application and validation; 3.3. Extension to back action evasion; 3.3.1. Back action problem and illustration; 3.3.2. Observer-based approach; 3.3.3. Simulation results and comments; 3.4. Conclusion; 3.5. Acknowledgements; 3.6. Bibliography Chapter 4. Tunnel Current for a Robust, High-bandwidth and Ultraprecise Nanopositioning 4.1. Introduction; 4.2. System description; 4.2.1. Forces between the tip and the beam; 4.3. System modeling; 4.3.1. Cantilever model; 4.3.2. System actuators; 4.3.3. Tunnel current; 4.3.4. System model; 4.3.5. System analysis; 4.4. Problem statement; 4.4.1. Robustness and non-linearities; 4.4.2. Experimental noise; 4.5. Tools to deal with noise; 4.5.1. Kalman filter; 4.5.2. Minimum variance controller; 4.6. Closed-loop requirements; 4.6.1. Sensitivity functions; 4.6.2. Robustness margins 4.6.3. Templates of the sensibility functions 4.7. Control strategy; 4.7.1. Actuator linearization; 4.7.2. Sensor approximation; 4.7.3. Kalman filtering; 4.7.4. RST1 synthesis; 4.7.5. z reconstruction; 4.7.6. RST2 synthesis; 4.8. Results; 4.8.1. Position control; 4.8.2. Distance d control; 4.8.3. Robustness; 4.9. Conclusion; 4.10. Bibliography; Chapter 5. Controller Design and Analysis for High-performance STM; 5.1. Introduction; 5.2. General description of STM; 5.2.1. STM operation modes; 5.2.2. Principle; 5.3. Control design model; 5.3.1. Linear approximation approach 5.3.2. Open-loop analysis |
| Record Nr. | UNINA-9910138300703321 |
| London, : ISTE | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Micro, nanosystems, and systems on chips : modeling, control, and estimation / / edited by Alina Voda
| Micro, nanosystems, and systems on chips : modeling, control, and estimation / / edited by Alina Voda |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | London, : ISTE |
| Descrizione fisica | 1 online resource (330 p.) |
| Disciplina | 621.381 |
| Altri autori (Persone) | VodaAlina |
| Collana | ISTE |
| Soggetto topico |
Microelectromechanical systems
Systems on a chip |
| ISBN |
1-118-55781-6
1-299-31845-2 1-118-62267-7 1-61344-555-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover; Title Page; Copyright Page; Table of Contents; Introduction; PART I. MINI AND MICROSYSTEMS; Chapter 1. Modeling and Control of Stick-slip Micropositioning Devices; 1.1. Introduction; 1.2. General description of stick-slip micropositioning devices; 1.2.1. Principle; 1.2.2. Experimental device; 1.3. Model of the sub-step mode; 1.3.1. Assumptions; 1.3.2. Microactuator equation; 1.3.3. The elastoplastic friction model; 1.3.4. The state equation; 1.3.5. The output equation; 1.3.6. Experimental and simulation curves; 1.4. PI control of the sub-step mode; 1.5. Modeling the coarse mode
1.5.1. The model1.5.2. Experimental results; 1.5.3. Remarks; 1.6. Voltage/frequency (U/f) proportional control of the coarse mode; 1.6.1. Principle scheme of the proposed controller; 1.6.2. Analysis; 1.6.3. Stability analysis; 1.6.4. Experiments; 1.7. Conclusion; 1.8. Bibliography; Chapter 2. Microbeam Dynamic Shaping by Closed-loop Electrostatic Actuation using Modal Control; 2.1. Introduction; 2.2. System description; 2.3. Modal analysis; 2.4. Mode-based control; 2.4.1. PID control; 2.4.2. FSF-LTR control; 2.5. Conclusion; 2.6. Bibliography; PART II. NANOSYSTEMS AND NANOWORLD Chapter 3. Observer-based Estimation of Weak Forces in a Nanosystem Measurement Device 3.1. Introduction; 3.2. Observer approach in an AFM measurement set-up; 3.2.1. Considered AFM model and force measurement problem; 3.2.2. Proposed observer approach; 3.2.3. Experimental application and validation; 3.3. Extension to back action evasion; 3.3.1. Back action problem and illustration; 3.3.2. Observer-based approach; 3.3.3. Simulation results and comments; 3.4. Conclusion; 3.5. Acknowledgements; 3.6. Bibliography Chapter 4. Tunnel Current for a Robust, High-bandwidth and Ultraprecise Nanopositioning 4.1. Introduction; 4.2. System description; 4.2.1. Forces between the tip and the beam; 4.3. System modeling; 4.3.1. Cantilever model; 4.3.2. System actuators; 4.3.3. Tunnel current; 4.3.4. System model; 4.3.5. System analysis; 4.4. Problem statement; 4.4.1. Robustness and non-linearities; 4.4.2. Experimental noise; 4.5. Tools to deal with noise; 4.5.1. Kalman filter; 4.5.2. Minimum variance controller; 4.6. Closed-loop requirements; 4.6.1. Sensitivity functions; 4.6.2. Robustness margins 4.6.3. Templates of the sensibility functions 4.7. Control strategy; 4.7.1. Actuator linearization; 4.7.2. Sensor approximation; 4.7.3. Kalman filtering; 4.7.4. RST1 synthesis; 4.7.5. z reconstruction; 4.7.6. RST2 synthesis; 4.8. Results; 4.8.1. Position control; 4.8.2. Distance d control; 4.8.3. Robustness; 4.9. Conclusion; 4.10. Bibliography; Chapter 5. Controller Design and Analysis for High-performance STM; 5.1. Introduction; 5.2. General description of STM; 5.2.1. STM operation modes; 5.2.2. Principle; 5.3. Control design model; 5.3.1. Linear approximation approach 5.3.2. Open-loop analysis |
| Record Nr. | UNINA-9910808453903321 |
| London, : ISTE | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Mixed-signal embedded systems design : a hands-on guide to the Cypress PSoC / / Edward H. Currie
| Mixed-signal embedded systems design : a hands-on guide to the Cypress PSoC / / Edward H. Currie |
| Autore | Currie Edward H. |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , [2022] |
| Descrizione fisica | 1 online resource (891 pages) : (XLIII, 860 p. 517 illus., 182 illus. in color.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Systems on a chip
Mixed signal circuits |
| ISBN | 3-030-70312-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction to Embedded Systems --Microcontroller Subsystems --System and Software Development --Communication Peripherals --Programmable Logic --Mixed-Signal Processing --PSoC3/5 Design Examples --Designing/Building a Simple Embedded System --Polling, Interrupts and ISRs --Phase-Locked Loops --The Pierce Oscillator. |
| Record Nr. | UNINA-9910510552103321 |
Currie Edward H.
|
||
| Cham, Switzerland : , : Springer, , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Mobile 3D graphics SoC : from algorithm to chip / / Jeong-Ho Woo ... [et al.]
| Mobile 3D graphics SoC : from algorithm to chip / / Jeong-Ho Woo ... [et al.] |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Singapore ; , : John Wiley & Sons, , c2010 |
| Descrizione fisica | 1 online resource (342 p.) |
| Disciplina | 621.3815 |
| Altri autori (Persone) | WooJeong-Ho |
| Soggetto topico |
Computer graphics
Mobile computing Systems on a chip Three-dimensional display systems |
| ISBN |
1-282-68797-2
9786612687976 0-470-82379-8 0-470-82378-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Preface -- 1 Introduction -- 1.1 Mobile 3D Graphics -- 1.2 Mobile Devices and Design Challenges -- 1.2.1 Mobile Computing Power -- 1.2.2 Mobile Display Devices -- 1.2.3 Design Challenges -- 1.3 Introduction to SoC Design -- 1.4 About this Book -- 2 Application Platform -- 2.1 SoC Design Paradigms -- 2.1.1 Platform and Set-based Design -- 2.1.2 Modeling: Memory and Operations -- 2.2 System Architecture -- 2.2.1 Reference Machine and API -- 2.2.2 Communication Architecture Design -- 2.2.3 System Analysis -- 2.3 Low-power SoC Design -- 2.3.1 CMOS Circuit-level Low-power Design -- 2.3.2 Architecture-level Low-power Design -- 2.3.3 System-level Low-power Design -- 2.4 Network-on-Chip based SoC -- 2.4.1 Network-on-Chip Basics -- 2.4.2 NoC Design Considerations -- 2.4.3 Case Studies of Chip Implementation -- 3 Introduction to 3D Graphics -- 3.1 The 3D Graphics Pipeline -- 3.1.1 The Application Stage -- 3.1.2 The Geometry Stage -- 3.1.3 The Rendering Stage -- 3.2 Programmable 3D Graphics -- 3.2.1 Programmable Graphics Pipeline -- 3.2.2 Shader Models -- 4 Mobile 3D Graphics -- 4.1 Principles of Mobile 3D Graphics -- 4.1.1 Application Challenges -- 4.1.2 Design Principles -- 4.2 Mobile 3D Graphics APIs -- 4.2.1 KAIST MobileGL -- 4.2.2 Khronos OpenGL-ES -- 4.2.3 Microsoft's Direct3D-Mobile -- 4.3 Summary and Future Directions -- 5 Mobile 3D Graphics SoC -- 5.1 Low-power Rendering Processor -- 5.1.1 Early Depth Test -- 5.1.2 Logarithmic Datapaths -- 5.1.3 Low-power Texture Unit -- 5.1.4 Tile-based Rendering -- 5.1.5 Texture Compression -- 5.1.6 Texture Filtering and Anti-aliasing -- 5.2 Low-power Shader -- 5.2.1 Vertex Cache -- 5.2.2 Low-power Register File -- 5.2.3 Mobile Unified Shader -- 6 Real Chip Implementations -- 6.1 KAIST RAMP Architecture -- 6.1.1 RAMP-IV -- 6.1.2 RAMP-V -- 6.1.3 RAMP-VI -- 6.1.4 RAMP-VII -- 6.2 Industry Architecture -- 6.2.1 nVidia Mobile GPU - SC10 and Tegra -- 6.2.2 Sony PSP -- 6.2.3 Imagination Technology MBX/SGX -- 7 Low-power Rasterizer Design.
7.1 Target System Architecture -- 7.2 Summary of Performance and Features -- 7.3 Block Diagram of the Rasterizer -- 7.4 Instruction Set Architecture (ISA) -- 7.5 Detailed Design with Register Transfer Level Code -- 7.5.1 Rasterization Top Block -- 7.5.2 Pipeline Architecture -- 7.5.3 Main Controller Design -- 7.5.4 Rasterization Core Unit -- 8 The Future of Mobile 3D Graphics -- 8.1 Game and Mapping Applications Involving Networking -- 8.2 Moves Towards More User-centered Applications -- 8.3 Final Remarks -- Appendix Verilog HDL Design -- A.1 Introduction to Verilog Design -- A.2 Design Level -- A.2.1 Behavior Level -- A.2.2 Register Transfer Level -- A.2.3 Gate Level -- A.3 Design Flow -- A.3.1 Specification -- A.3.2 High-level Design -- A.3.3 Low-level Design -- A.3.4 RTL Coding -- A.3.5 Simulation -- A.3.6 Synthesis -- A.3.7 Placement and Routing -- A.4 Verilog Syntax -- A.4.1 Modules -- A.4.2 Logic Values and Numbers -- A.4.3 Data Types -- A.4.4 Operators -- A.4.5 Assignment -- A.4.6 Ports and Connections -- A.4.7 Expressions -- A.4.8 Instantiation -- A.4.9 Miscellaneous -- A.5 Example of Four-bit Adder with Zero Detection -- A.6 Synthesis Scripts -- Glossaries -- Index. |
| Altri titoli varianti | Mobile three-dimensional graphics systems on a chip |
| Record Nr. | UNINA-9910140576503321 |
| Singapore ; , : John Wiley & Sons, , c2010 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Mobile 3D graphics SoC : from algorithm to chip / / Jeong-Ho Woo ... [et al.]
| Mobile 3D graphics SoC : from algorithm to chip / / Jeong-Ho Woo ... [et al.] |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Singapore ; , : John Wiley & Sons, , c2010 |
| Descrizione fisica | 1 online resource (342 p.) |
| Disciplina | 621.3815 |
| Altri autori (Persone) | WooJeong-Ho |
| Soggetto topico |
Computer graphics
Mobile computing Systems on a chip Three-dimensional display systems |
| ISBN |
1-282-68797-2
9786612687976 0-470-82379-8 0-470-82378-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Preface -- 1 Introduction -- 1.1 Mobile 3D Graphics -- 1.2 Mobile Devices and Design Challenges -- 1.2.1 Mobile Computing Power -- 1.2.2 Mobile Display Devices -- 1.2.3 Design Challenges -- 1.3 Introduction to SoC Design -- 1.4 About this Book -- 2 Application Platform -- 2.1 SoC Design Paradigms -- 2.1.1 Platform and Set-based Design -- 2.1.2 Modeling: Memory and Operations -- 2.2 System Architecture -- 2.2.1 Reference Machine and API -- 2.2.2 Communication Architecture Design -- 2.2.3 System Analysis -- 2.3 Low-power SoC Design -- 2.3.1 CMOS Circuit-level Low-power Design -- 2.3.2 Architecture-level Low-power Design -- 2.3.3 System-level Low-power Design -- 2.4 Network-on-Chip based SoC -- 2.4.1 Network-on-Chip Basics -- 2.4.2 NoC Design Considerations -- 2.4.3 Case Studies of Chip Implementation -- 3 Introduction to 3D Graphics -- 3.1 The 3D Graphics Pipeline -- 3.1.1 The Application Stage -- 3.1.2 The Geometry Stage -- 3.1.3 The Rendering Stage -- 3.2 Programmable 3D Graphics -- 3.2.1 Programmable Graphics Pipeline -- 3.2.2 Shader Models -- 4 Mobile 3D Graphics -- 4.1 Principles of Mobile 3D Graphics -- 4.1.1 Application Challenges -- 4.1.2 Design Principles -- 4.2 Mobile 3D Graphics APIs -- 4.2.1 KAIST MobileGL -- 4.2.2 Khronos OpenGL-ES -- 4.2.3 Microsoft's Direct3D-Mobile -- 4.3 Summary and Future Directions -- 5 Mobile 3D Graphics SoC -- 5.1 Low-power Rendering Processor -- 5.1.1 Early Depth Test -- 5.1.2 Logarithmic Datapaths -- 5.1.3 Low-power Texture Unit -- 5.1.4 Tile-based Rendering -- 5.1.5 Texture Compression -- 5.1.6 Texture Filtering and Anti-aliasing -- 5.2 Low-power Shader -- 5.2.1 Vertex Cache -- 5.2.2 Low-power Register File -- 5.2.3 Mobile Unified Shader -- 6 Real Chip Implementations -- 6.1 KAIST RAMP Architecture -- 6.1.1 RAMP-IV -- 6.1.2 RAMP-V -- 6.1.3 RAMP-VI -- 6.1.4 RAMP-VII -- 6.2 Industry Architecture -- 6.2.1 nVidia Mobile GPU - SC10 and Tegra -- 6.2.2 Sony PSP -- 6.2.3 Imagination Technology MBX/SGX -- 7 Low-power Rasterizer Design.
7.1 Target System Architecture -- 7.2 Summary of Performance and Features -- 7.3 Block Diagram of the Rasterizer -- 7.4 Instruction Set Architecture (ISA) -- 7.5 Detailed Design with Register Transfer Level Code -- 7.5.1 Rasterization Top Block -- 7.5.2 Pipeline Architecture -- 7.5.3 Main Controller Design -- 7.5.4 Rasterization Core Unit -- 8 The Future of Mobile 3D Graphics -- 8.1 Game and Mapping Applications Involving Networking -- 8.2 Moves Towards More User-centered Applications -- 8.3 Final Remarks -- Appendix Verilog HDL Design -- A.1 Introduction to Verilog Design -- A.2 Design Level -- A.2.1 Behavior Level -- A.2.2 Register Transfer Level -- A.2.3 Gate Level -- A.3 Design Flow -- A.3.1 Specification -- A.3.2 High-level Design -- A.3.3 Low-level Design -- A.3.4 RTL Coding -- A.3.5 Simulation -- A.3.6 Synthesis -- A.3.7 Placement and Routing -- A.4 Verilog Syntax -- A.4.1 Modules -- A.4.2 Logic Values and Numbers -- A.4.3 Data Types -- A.4.4 Operators -- A.4.5 Assignment -- A.4.6 Ports and Connections -- A.4.7 Expressions -- A.4.8 Instantiation -- A.4.9 Miscellaneous -- A.5 Example of Four-bit Adder with Zero Detection -- A.6 Synthesis Scripts -- Glossaries -- Index. |
| Altri titoli varianti | Mobile three-dimensional graphics systems on a chip |
| Record Nr. | UNINA-9910824767603321 |
| Singapore ; , : John Wiley & Sons, , c2010 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Multi-processor system-on-chip . 1 Architectures / / coordinated by Liliana Andrade, Frédéric Rousseau
| Multi-processor system-on-chip . 1 Architectures / / coordinated by Liliana Andrade, Frédéric Rousseau |
| Pubbl/distr/stampa | London : , : ISTE |
| Descrizione fisica | 1 online resource (321 pages) |
| Disciplina | 621.3815 |
| Soggetto topico | Systems on a chip |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-119-81829-X
1-119-81827-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover -- Half-Title Page -- Dedication -- Title Page -- Copyright Page -- Contents -- Foreword -- Acknowledgments -- PART 1: Processors -- 1 Processors for the Internet of Things -- 1.1. Introduction -- 1.2. Versatile processors for low-power IoT edge devices -- 1.2.1. Control processing, DSP and machine learning -- 1.2.2. Configurability and extensibility -- 1.3. Machine learning inference -- 1.3.1. Requirements for low/mid-end machine learning inference -- 1.3.2. Processor capabilities for low-power machine learning inference -- 1.3.3. A software library for machine learning inference -- 1.3.4. Example machine learning applications and benchmarks -- 1.4. Conclusion -- 1.5. References -- 2 A Qualitative Approach to Many-core Architecture -- 2.1. Introduction -- 2.2. Motivations and context -- 2.2.1. Many-core processors -- 2.2.2. Machine learning inference -- 2.2.3. Application requirements -- 2.3. The MPPA3 many-core processor -- 2.3.1. Global architecture -- 2.3.2. Compute cluster -- 2.3.3. VLIW core -- 2.3.4. Coprocessor -- 2.4. The MPPA3 software environments -- 2.4.1. High-performance computing -- 2.4.2. KaNN code generator -- 2.4.3. High-integrity computing -- 2.5. Conclusion -- 2.6. References -- 3 The Plural Many-core Architecture - High Performance at Low Power -- 3.1. Introduction -- 3.2. Related works -- 3.3. Plural many-core architecture -- 3.4. Plural programming model -- 3.5. Plural hardware scheduler/synchronizer -- 3.6. Plural networks-on-chip -- 3.6.1. Scheduler NoC -- 3.6.2. Shared memory NoC -- 3.7. Hardware and software accelerators for the Plural architecture -- 3.8. Plural system software -- 3.9. Plural software development tools -- 3.10. Matrix multiplication algorithm on the Plural architecture -- 4 ASIP-Based Multi-Processor Systems for an Efficient Implementation of CNNs -- 4.1. Introduction -- 4.2. Related works.
4.3. ASIP architecture -- 4.4. Single-core scaling -- 4.5. MPSoC overview -- 4.6. NoC parameter exploration -- 4.7. Summary and conclusion -- 4.8. References -- PART 2: Memory -- 5 Tackling the MPSoC DataLocality Challenge -- 5.1. Motivation -- 5.2. MPSoC target platform -- 5.3. Related work -- 5.4. Coherence-on-demand: region-based cache coherence -- 5.4.1. RBCC versus global coherence -- 5.4.2. OS extensions for coherence-on-demand -- 5.4.3. Coherency region manager -- 5.4.4. Experimental evaluations -- 5.4.5. RBCC and data placement -- 5.5. Near-memory acceleration -- 5.5.1. Near-memory synchronization accelerator -- 5.5.2. Near-memory queue management accelerator -- 5.5.3. Near-memory graph copy accelerator -- 5.5.4. Near-cache accelerator -- 5.6. The big picture -- 5.7. Conclusion -- 5.8. Acknowledgments -- 5.9. References -- 6 mMPU: Building a Memristor-based General-purpose In-memory Computation Architecture -- 6.1. Introduction -- 6.2. MAGIC NOR gate -- 6.3. In-memory algorithms for latency reduction -- 6.4. Synthesis and in-memory mapping methods -- 6.4.1. SIMPLE -- 6.4.2. SIMPLER -- 6.5. Designing the memory controller -- 6.6. Conclusion -- 6.7. References -- 7 Removing Load/Store Helpers in Dynamic Binary Translation -- 7.1. Introduction -- 7.2. Emulating memory accesses -- 7.3. Design of our solution -- 7.4. Implementation -- 7.4.1. Kernel module -- 7.4.2. Dynamic binary translation -- 7.4.3. Optimizing our slow path -- 7.5. Evaluation -- 7.5.1. QEMU emulation performance analysis -- 7.5.2. Our performance overview -- 7.5.3. Optimized slow path -- 7.6. Related works -- 7.7. Conclusion -- 7.8. References -- 8 Study and Comparison of Hardware Methods for Distributing Memory Bank Accesses in Many-core Architectures -- 8.1. Introduction -- 8.1.1. Context -- 8.1.2. MPSoC architecture -- 8.1.3. Interconnect -- 8.2. Basics on banked memory. 8.2.1. Banked memory -- 8.2.2. Memory bank conflict and granularity -- 8.2.3. Efficient use of memory banks: interleaving -- 8.3. Overview of software approaches -- 8.3.1. Padding -- 8.3.2. Static scheduling of memory accesses -- 8.3.3. The need for hardware approaches -- 8.4. Hardware approaches -- 8.4.1. Prime modulus indexing -- 8.4.2. Interleaving schemes using hash functions -- 8.5. Modeling and experimenting -- 8.5.1. Simulator implementation -- 8.5.2. Implementation of the Kalray MPPA cluster interconnect -- 8.5.3. Objectives and method -- 8.5.4. Results and discussion -- 8.6. Conclusion -- 8.7. References -- PART 3: Interconnect and Interfaces -- 9 Network-on-Chip (NoC): The Technology that Enabled Multi-processor Systems-on-Chip (MPSoCs) -- 9.1. History: transition from buses and crossbars to NoCs -- 9.1.1. NoC architecture -- 9.1.2. Extending the bus comparison to crossbars -- 9.1.3. Bus, crossbar and NoC comparison summary and conclusion -- 9.2. NoC configurability -- 9.2.1. Human-guided design flow -- 9.2.2. Physical placement awareness and NoC architecture design -- 9.3. System-level services -- 9.3.1. Quality-of-service (QoS) and arbitration -- 9.3.2. Hardware debug and performance analysis -- 9.3.3. Functional safety and security -- 9.4. Hardware cache coherence -- 9.4.1. NoC protocols, semantics and messaging -- 9.5. Future NoC technology developments -- 9.5.1. Topology synthesis and floorplan awareness -- 9.5.2. Advanced resilience and functional safety for autonomous vehicles -- 9.5.3. Alternatives to von Neumann architectures for SoCs -- 9.5.4. Chiplets and multi-die NoC connectivity -- 9.5.5. Runtime software automation -- 9.5.6. Instrumentation, diagnostics and analytics for performance, safety and security -- 9.6. Summary and conclusion -- 9.7. References -- 10 Minimum Energy Computing via Supply and Threshold Voltage Scaling. 10.1. Introduction -- 10.2. Standard-cell-based memory for minimum energy computing -- 10.2.1. Overview of low-voltage on-chip memories -- 10.2.2. Design strategy for areaand energy-efficient SCMs -- 10.2.3. Hybrid memory design towards energyand area-efficient memory systems -- 10.2.4. Body biasing as an alternative to power gating -- 10.2. Standard-cell-based memory for minimum energy computing -- 10.3. Minimum energy point tracking -- 10.3.1. Basic theory -- 10.3.2. Algorithms and implementation -- 10.3.3. OS-based approach to minimum energy point tracking -- 10.4. Conclusion -- 10.5. Acknowledgments -- 10.6. References -- 11 Maintaining Communication Consistency During Task Migrations in Heterogeneous Reconfigurable Devices -- 11.1. Introduction -- 11.1.1. Reconfigurable architectures -- 11.1.2. Contribution -- 11.2. Background -- 11.2.1. Definitions -- 11.2.2. Problem scenario and technical challenges -- 11.3. Related works -- 11.3.1. Hardware context switch -- 11.3.2. Communication management -- 11.4. Proposed communication methodology in hardware context switching -- 11.5. Implementation of the communication management on reconfigurable computing architectures -- 11.5.1. Reconfigurable channels in FIFO -- 11.5.2. Communication infrastructure -- 11.6. Experimental results -- 11.6.1. Setup -- 11.6.2. Experiment scenario -- 11.6.3. Resource overhead -- 11.6.4. Impact on the total execution time -- 11.6.5. Impact on the context extract and restore time -- 11.6.6. System responsiveness to context switch requests -- 11.6.7. Hardware task migration between heterogeneous FPGAs -- 11.7. Conclusion -- 11.8. References -- List of Authors -- Author Biographies -- Index -- EULA. |
| Record Nr. | UNINA-9910555252703321 |
| London : , : ISTE | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Multi-processor system-on-chip . 1 Architectures / / coordinated by Liliana Andrade, Frédéric Rousseau
| Multi-processor system-on-chip . 1 Architectures / / coordinated by Liliana Andrade, Frédéric Rousseau |
| Pubbl/distr/stampa | London : , : ISTE |
| Descrizione fisica | 1 online resource (321 pages) |
| Disciplina | 621.3815 |
| Soggetto topico | Systems on a chip |
| ISBN |
1-119-81829-X
1-119-81827-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover -- Half-Title Page -- Dedication -- Title Page -- Copyright Page -- Contents -- Foreword -- Acknowledgments -- PART 1: Processors -- 1 Processors for the Internet of Things -- 1.1. Introduction -- 1.2. Versatile processors for low-power IoT edge devices -- 1.2.1. Control processing, DSP and machine learning -- 1.2.2. Configurability and extensibility -- 1.3. Machine learning inference -- 1.3.1. Requirements for low/mid-end machine learning inference -- 1.3.2. Processor capabilities for low-power machine learning inference -- 1.3.3. A software library for machine learning inference -- 1.3.4. Example machine learning applications and benchmarks -- 1.4. Conclusion -- 1.5. References -- 2 A Qualitative Approach to Many-core Architecture -- 2.1. Introduction -- 2.2. Motivations and context -- 2.2.1. Many-core processors -- 2.2.2. Machine learning inference -- 2.2.3. Application requirements -- 2.3. The MPPA3 many-core processor -- 2.3.1. Global architecture -- 2.3.2. Compute cluster -- 2.3.3. VLIW core -- 2.3.4. Coprocessor -- 2.4. The MPPA3 software environments -- 2.4.1. High-performance computing -- 2.4.2. KaNN code generator -- 2.4.3. High-integrity computing -- 2.5. Conclusion -- 2.6. References -- 3 The Plural Many-core Architecture - High Performance at Low Power -- 3.1. Introduction -- 3.2. Related works -- 3.3. Plural many-core architecture -- 3.4. Plural programming model -- 3.5. Plural hardware scheduler/synchronizer -- 3.6. Plural networks-on-chip -- 3.6.1. Scheduler NoC -- 3.6.2. Shared memory NoC -- 3.7. Hardware and software accelerators for the Plural architecture -- 3.8. Plural system software -- 3.9. Plural software development tools -- 3.10. Matrix multiplication algorithm on the Plural architecture -- 4 ASIP-Based Multi-Processor Systems for an Efficient Implementation of CNNs -- 4.1. Introduction -- 4.2. Related works.
4.3. ASIP architecture -- 4.4. Single-core scaling -- 4.5. MPSoC overview -- 4.6. NoC parameter exploration -- 4.7. Summary and conclusion -- 4.8. References -- PART 2: Memory -- 5 Tackling the MPSoC DataLocality Challenge -- 5.1. Motivation -- 5.2. MPSoC target platform -- 5.3. Related work -- 5.4. Coherence-on-demand: region-based cache coherence -- 5.4.1. RBCC versus global coherence -- 5.4.2. OS extensions for coherence-on-demand -- 5.4.3. Coherency region manager -- 5.4.4. Experimental evaluations -- 5.4.5. RBCC and data placement -- 5.5. Near-memory acceleration -- 5.5.1. Near-memory synchronization accelerator -- 5.5.2. Near-memory queue management accelerator -- 5.5.3. Near-memory graph copy accelerator -- 5.5.4. Near-cache accelerator -- 5.6. The big picture -- 5.7. Conclusion -- 5.8. Acknowledgments -- 5.9. References -- 6 mMPU: Building a Memristor-based General-purpose In-memory Computation Architecture -- 6.1. Introduction -- 6.2. MAGIC NOR gate -- 6.3. In-memory algorithms for latency reduction -- 6.4. Synthesis and in-memory mapping methods -- 6.4.1. SIMPLE -- 6.4.2. SIMPLER -- 6.5. Designing the memory controller -- 6.6. Conclusion -- 6.7. References -- 7 Removing Load/Store Helpers in Dynamic Binary Translation -- 7.1. Introduction -- 7.2. Emulating memory accesses -- 7.3. Design of our solution -- 7.4. Implementation -- 7.4.1. Kernel module -- 7.4.2. Dynamic binary translation -- 7.4.3. Optimizing our slow path -- 7.5. Evaluation -- 7.5.1. QEMU emulation performance analysis -- 7.5.2. Our performance overview -- 7.5.3. Optimized slow path -- 7.6. Related works -- 7.7. Conclusion -- 7.8. References -- 8 Study and Comparison of Hardware Methods for Distributing Memory Bank Accesses in Many-core Architectures -- 8.1. Introduction -- 8.1.1. Context -- 8.1.2. MPSoC architecture -- 8.1.3. Interconnect -- 8.2. Basics on banked memory. 8.2.1. Banked memory -- 8.2.2. Memory bank conflict and granularity -- 8.2.3. Efficient use of memory banks: interleaving -- 8.3. Overview of software approaches -- 8.3.1. Padding -- 8.3.2. Static scheduling of memory accesses -- 8.3.3. The need for hardware approaches -- 8.4. Hardware approaches -- 8.4.1. Prime modulus indexing -- 8.4.2. Interleaving schemes using hash functions -- 8.5. Modeling and experimenting -- 8.5.1. Simulator implementation -- 8.5.2. Implementation of the Kalray MPPA cluster interconnect -- 8.5.3. Objectives and method -- 8.5.4. Results and discussion -- 8.6. Conclusion -- 8.7. References -- PART 3: Interconnect and Interfaces -- 9 Network-on-Chip (NoC): The Technology that Enabled Multi-processor Systems-on-Chip (MPSoCs) -- 9.1. History: transition from buses and crossbars to NoCs -- 9.1.1. NoC architecture -- 9.1.2. Extending the bus comparison to crossbars -- 9.1.3. Bus, crossbar and NoC comparison summary and conclusion -- 9.2. NoC configurability -- 9.2.1. Human-guided design flow -- 9.2.2. Physical placement awareness and NoC architecture design -- 9.3. System-level services -- 9.3.1. Quality-of-service (QoS) and arbitration -- 9.3.2. Hardware debug and performance analysis -- 9.3.3. Functional safety and security -- 9.4. Hardware cache coherence -- 9.4.1. NoC protocols, semantics and messaging -- 9.5. Future NoC technology developments -- 9.5.1. Topology synthesis and floorplan awareness -- 9.5.2. Advanced resilience and functional safety for autonomous vehicles -- 9.5.3. Alternatives to von Neumann architectures for SoCs -- 9.5.4. Chiplets and multi-die NoC connectivity -- 9.5.5. Runtime software automation -- 9.5.6. Instrumentation, diagnostics and analytics for performance, safety and security -- 9.6. Summary and conclusion -- 9.7. References -- 10 Minimum Energy Computing via Supply and Threshold Voltage Scaling. 10.1. Introduction -- 10.2. Standard-cell-based memory for minimum energy computing -- 10.2.1. Overview of low-voltage on-chip memories -- 10.2.2. Design strategy for areaand energy-efficient SCMs -- 10.2.3. Hybrid memory design towards energyand area-efficient memory systems -- 10.2.4. Body biasing as an alternative to power gating -- 10.2. Standard-cell-based memory for minimum energy computing -- 10.3. Minimum energy point tracking -- 10.3.1. Basic theory -- 10.3.2. Algorithms and implementation -- 10.3.3. OS-based approach to minimum energy point tracking -- 10.4. Conclusion -- 10.5. Acknowledgments -- 10.6. References -- 11 Maintaining Communication Consistency During Task Migrations in Heterogeneous Reconfigurable Devices -- 11.1. Introduction -- 11.1.1. Reconfigurable architectures -- 11.1.2. Contribution -- 11.2. Background -- 11.2.1. Definitions -- 11.2.2. Problem scenario and technical challenges -- 11.3. Related works -- 11.3.1. Hardware context switch -- 11.3.2. Communication management -- 11.4. Proposed communication methodology in hardware context switching -- 11.5. Implementation of the communication management on reconfigurable computing architectures -- 11.5.1. Reconfigurable channels in FIFO -- 11.5.2. Communication infrastructure -- 11.6. Experimental results -- 11.6.1. Setup -- 11.6.2. Experiment scenario -- 11.6.3. Resource overhead -- 11.6.4. Impact on the total execution time -- 11.6.5. Impact on the context extract and restore time -- 11.6.6. System responsiveness to context switch requests -- 11.6.7. Hardware task migration between heterogeneous FPGAs -- 11.7. Conclusion -- 11.8. References -- List of Authors -- Author Biographies -- Index -- EULA. |
| Record Nr. | UNINA-9910677401503321 |
| London : , : ISTE | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Multi-processor system-on-chip . 1 Architectures / / coordinated by Liliana Andrade, Frédéric Rousseau
| Multi-processor system-on-chip . 1 Architectures / / coordinated by Liliana Andrade, Frédéric Rousseau |
| Pubbl/distr/stampa | London : , : ISTE |
| Descrizione fisica | 1 online resource (321 pages) |
| Disciplina | 621.3815 |
| Soggetto topico | Systems on a chip |
| ISBN |
1-119-81829-X
1-119-81827-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover -- Half-Title Page -- Dedication -- Title Page -- Copyright Page -- Contents -- Foreword -- Acknowledgments -- PART 1: Processors -- 1 Processors for the Internet of Things -- 1.1. Introduction -- 1.2. Versatile processors for low-power IoT edge devices -- 1.2.1. Control processing, DSP and machine learning -- 1.2.2. Configurability and extensibility -- 1.3. Machine learning inference -- 1.3.1. Requirements for low/mid-end machine learning inference -- 1.3.2. Processor capabilities for low-power machine learning inference -- 1.3.3. A software library for machine learning inference -- 1.3.4. Example machine learning applications and benchmarks -- 1.4. Conclusion -- 1.5. References -- 2 A Qualitative Approach to Many-core Architecture -- 2.1. Introduction -- 2.2. Motivations and context -- 2.2.1. Many-core processors -- 2.2.2. Machine learning inference -- 2.2.3. Application requirements -- 2.3. The MPPA3 many-core processor -- 2.3.1. Global architecture -- 2.3.2. Compute cluster -- 2.3.3. VLIW core -- 2.3.4. Coprocessor -- 2.4. The MPPA3 software environments -- 2.4.1. High-performance computing -- 2.4.2. KaNN code generator -- 2.4.3. High-integrity computing -- 2.5. Conclusion -- 2.6. References -- 3 The Plural Many-core Architecture - High Performance at Low Power -- 3.1. Introduction -- 3.2. Related works -- 3.3. Plural many-core architecture -- 3.4. Plural programming model -- 3.5. Plural hardware scheduler/synchronizer -- 3.6. Plural networks-on-chip -- 3.6.1. Scheduler NoC -- 3.6.2. Shared memory NoC -- 3.7. Hardware and software accelerators for the Plural architecture -- 3.8. Plural system software -- 3.9. Plural software development tools -- 3.10. Matrix multiplication algorithm on the Plural architecture -- 4 ASIP-Based Multi-Processor Systems for an Efficient Implementation of CNNs -- 4.1. Introduction -- 4.2. Related works.
4.3. ASIP architecture -- 4.4. Single-core scaling -- 4.5. MPSoC overview -- 4.6. NoC parameter exploration -- 4.7. Summary and conclusion -- 4.8. References -- PART 2: Memory -- 5 Tackling the MPSoC DataLocality Challenge -- 5.1. Motivation -- 5.2. MPSoC target platform -- 5.3. Related work -- 5.4. Coherence-on-demand: region-based cache coherence -- 5.4.1. RBCC versus global coherence -- 5.4.2. OS extensions for coherence-on-demand -- 5.4.3. Coherency region manager -- 5.4.4. Experimental evaluations -- 5.4.5. RBCC and data placement -- 5.5. Near-memory acceleration -- 5.5.1. Near-memory synchronization accelerator -- 5.5.2. Near-memory queue management accelerator -- 5.5.3. Near-memory graph copy accelerator -- 5.5.4. Near-cache accelerator -- 5.6. The big picture -- 5.7. Conclusion -- 5.8. Acknowledgments -- 5.9. References -- 6 mMPU: Building a Memristor-based General-purpose In-memory Computation Architecture -- 6.1. Introduction -- 6.2. MAGIC NOR gate -- 6.3. In-memory algorithms for latency reduction -- 6.4. Synthesis and in-memory mapping methods -- 6.4.1. SIMPLE -- 6.4.2. SIMPLER -- 6.5. Designing the memory controller -- 6.6. Conclusion -- 6.7. References -- 7 Removing Load/Store Helpers in Dynamic Binary Translation -- 7.1. Introduction -- 7.2. Emulating memory accesses -- 7.3. Design of our solution -- 7.4. Implementation -- 7.4.1. Kernel module -- 7.4.2. Dynamic binary translation -- 7.4.3. Optimizing our slow path -- 7.5. Evaluation -- 7.5.1. QEMU emulation performance analysis -- 7.5.2. Our performance overview -- 7.5.3. Optimized slow path -- 7.6. Related works -- 7.7. Conclusion -- 7.8. References -- 8 Study and Comparison of Hardware Methods for Distributing Memory Bank Accesses in Many-core Architectures -- 8.1. Introduction -- 8.1.1. Context -- 8.1.2. MPSoC architecture -- 8.1.3. Interconnect -- 8.2. Basics on banked memory. 8.2.1. Banked memory -- 8.2.2. Memory bank conflict and granularity -- 8.2.3. Efficient use of memory banks: interleaving -- 8.3. Overview of software approaches -- 8.3.1. Padding -- 8.3.2. Static scheduling of memory accesses -- 8.3.3. The need for hardware approaches -- 8.4. Hardware approaches -- 8.4.1. Prime modulus indexing -- 8.4.2. Interleaving schemes using hash functions -- 8.5. Modeling and experimenting -- 8.5.1. Simulator implementation -- 8.5.2. Implementation of the Kalray MPPA cluster interconnect -- 8.5.3. Objectives and method -- 8.5.4. Results and discussion -- 8.6. Conclusion -- 8.7. References -- PART 3: Interconnect and Interfaces -- 9 Network-on-Chip (NoC): The Technology that Enabled Multi-processor Systems-on-Chip (MPSoCs) -- 9.1. History: transition from buses and crossbars to NoCs -- 9.1.1. NoC architecture -- 9.1.2. Extending the bus comparison to crossbars -- 9.1.3. Bus, crossbar and NoC comparison summary and conclusion -- 9.2. NoC configurability -- 9.2.1. Human-guided design flow -- 9.2.2. Physical placement awareness and NoC architecture design -- 9.3. System-level services -- 9.3.1. Quality-of-service (QoS) and arbitration -- 9.3.2. Hardware debug and performance analysis -- 9.3.3. Functional safety and security -- 9.4. Hardware cache coherence -- 9.4.1. NoC protocols, semantics and messaging -- 9.5. Future NoC technology developments -- 9.5.1. Topology synthesis and floorplan awareness -- 9.5.2. Advanced resilience and functional safety for autonomous vehicles -- 9.5.3. Alternatives to von Neumann architectures for SoCs -- 9.5.4. Chiplets and multi-die NoC connectivity -- 9.5.5. Runtime software automation -- 9.5.6. Instrumentation, diagnostics and analytics for performance, safety and security -- 9.6. Summary and conclusion -- 9.7. References -- 10 Minimum Energy Computing via Supply and Threshold Voltage Scaling. 10.1. Introduction -- 10.2. Standard-cell-based memory for minimum energy computing -- 10.2.1. Overview of low-voltage on-chip memories -- 10.2.2. Design strategy for areaand energy-efficient SCMs -- 10.2.3. Hybrid memory design towards energyand area-efficient memory systems -- 10.2.4. Body biasing as an alternative to power gating -- 10.2. Standard-cell-based memory for minimum energy computing -- 10.3. Minimum energy point tracking -- 10.3.1. Basic theory -- 10.3.2. Algorithms and implementation -- 10.3.3. OS-based approach to minimum energy point tracking -- 10.4. Conclusion -- 10.5. Acknowledgments -- 10.6. References -- 11 Maintaining Communication Consistency During Task Migrations in Heterogeneous Reconfigurable Devices -- 11.1. Introduction -- 11.1.1. Reconfigurable architectures -- 11.1.2. Contribution -- 11.2. Background -- 11.2.1. Definitions -- 11.2.2. Problem scenario and technical challenges -- 11.3. Related works -- 11.3.1. Hardware context switch -- 11.3.2. Communication management -- 11.4. Proposed communication methodology in hardware context switching -- 11.5. Implementation of the communication management on reconfigurable computing architectures -- 11.5.1. Reconfigurable channels in FIFO -- 11.5.2. Communication infrastructure -- 11.6. Experimental results -- 11.6.1. Setup -- 11.6.2. Experiment scenario -- 11.6.3. Resource overhead -- 11.6.4. Impact on the total execution time -- 11.6.5. Impact on the context extract and restore time -- 11.6.6. System responsiveness to context switch requests -- 11.6.7. Hardware task migration between heterogeneous FPGAs -- 11.7. Conclusion -- 11.8. References -- List of Authors -- Author Biographies -- Index -- EULA. |
| Record Nr. | UNINA-9910819692203321 |
| London : , : ISTE | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Multi-processor system-on-chip 2 : applications / / Liliana Andrade, Frédéric Rousseau
| Multi-processor system-on-chip 2 : applications / / Liliana Andrade, Frédéric Rousseau |
| Autore | Rousseau Frédéric <1967-> |
| Pubbl/distr/stampa | Hoboken, NJ : , : Wiley, , [2021] |
| Descrizione fisica | 1 online resource (271 pages) |
| Disciplina | 006.22 |
| Soggetto topico |
Multiprocessors
Systems on a chip |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-119-81840-0
1-119-81838-9 1-119-81841-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910555149303321 |
|
Rousseau Frédéric <1967->
|
||
| Hoboken, NJ : , : Wiley, , [2021] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
