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2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era : 16-18 April 2019, Mykonos, Greece / / Institute of Electrical and Electronics Engineers
| 2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era : 16-18 April 2019, Mykonos, Greece / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2019 |
| Descrizione fisica | 1 online resource (30 pages) |
| Disciplina | 621.3815 |
| Soggetto topico |
Integrated circuits - Design and construction
Integrated circuits - Testing Systems on a chip |
| ISBN | 1-7281-3424-2 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910326659403321 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era : 16-18 April 2019, Mykonos, Greece / / Institute of Electrical and Electronics Engineers
| 2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era : 16-18 April 2019, Mykonos, Greece / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2019 |
| Descrizione fisica | 1 online resource (30 pages) |
| Disciplina | 621.3815 |
| Soggetto topico |
Integrated circuits - Design and construction
Integrated circuits - Testing Systems on a chip |
| ISBN | 1-7281-3424-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996575446903316 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
3D interconnect architectures for heterogeneous technologies : modeling and optimization / / Lennart Bamberg [and three others]
| 3D interconnect architectures for heterogeneous technologies : modeling and optimization / / Lennart Bamberg [and three others] |
| Autore | Bamberg Lennart |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , [2022] |
| Descrizione fisica | 1 online resource (403 pages) |
| Disciplina | 621.3815 |
| Soggetto topico |
Interconnects (Integrated circuit technology)
Systems on a chip Three-dimensional integrated circuits |
| ISBN | 3-030-98229-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | Three-dimensional interconnect architectures for heterogeneous technologies |
| Record Nr. | UNINA-9910735388803321 |
Bamberg Lennart
|
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| Cham, Switzerland : , : Springer, , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Computer System Design [[electronic resource] ] : System-on-Chip
| Computer System Design [[electronic resource] ] : System-on-Chip |
| Autore | Flynn Michael J |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, : Wiley, 2011 |
| Descrizione fisica | 1 online resource (356 p.) |
| Disciplina | 004.1 |
| Altri autori (Persone) | LukWayne |
| Soggetto topico |
Systems on a chip
Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN |
1-283-15735-7
9786613157355 1-118-00991-6 1-118-00992-4 1-118-00990-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
COMPUTER SYSTEM DESIGN; CONTENTS; PREFACE; LIST OF ABBREVIATIONS AND ACRONYMS; 1: Introduction to the Systems Approach; 1.1 SYSTEM ARCHITECTURE: AN OVERVIEW; 1.2 COMPONENTS OF THE SYSTEM: PROCESSORS, MEMORIES, AND INTERCONNECTS; 1.3 HARDWARE AND SOFTWARE: PROGRAMMABILITY VERSUS PERFORMANCE; 1.4 PROCESSOR ARCHITECTURES; 1.4.1 Processor: A Functional View; 1.4.2 Processor: An Architectural View; 1.5 MEMORY AND ADDRESSING; 1.5.1 SOC Memory Examples; 1.5.2 Addressing: The Architecture of Memory; 1.5.3 Memory for SOC Operating System; 1.6 SYSTEM-LEVEL INTERCONNECTION; 1.6.1 Bus-Based Approach
1.6.2 Network-on-Chip Approach1.7 AN APPROACH FOR SOC DESIGN; 1.7.1 Requirements and Specifications; 1.7.2 Design Iteration; 1.8 SYSTEM ARCHITECTURE AND COMPLEXITY; 1.9 PRODUCT ECONOMICS AND IMPLICATIONS FOR SOC; 1.9.1 Factors Affecting Product Costs; 1.9.2 Modeling Product Economics and Technology Complexity: The Lesson for SOC; 1.10 DEALING WITH DESIGN COMPLEXITY; 1.10.1 Buying IP; 1.10.2 Reconfiguration; 1.11 CONCLUSIONS; 1.12 PROBLEM SET; 2: Chip Basics: Time, Area, Power, Reliability, and Configurability; 2.1 INTRODUCTION; 2.1.1 Design Trade-Offs; 2.1.2 Requirements and Specifications 2.2 CYCLE TIME2.2.1 Defining a Cycle; 2.2.2 Optimum Pipeline; 2.2.3 Performance; 2.3 DIE AREA AND COST; 2.3.1 Processor Area; 2.3.2 Processor Subunits; 2.4 IDEAL AND PRACTICAL SCALING; 2.5 POWER; 2.6 AREA-TIME-POWER TRADE-OFFS IN PROCESSOR DESIGN; 2.6.1 Workstation Processor; 2.6.2 Embedded Processor; 2.7 RELIABILITY; 2.7.1 Dealing with Physical Faults; 2.7.2 Error Detection and Correction; 2.7.3 Dealing with Manufacturing Faults; 2.7.4 Memory and Function Scrubbing; 2.8 CONFIGURABILITY; 2.8.1 Why Reconfigurable Design?; 2.8.2 Area Estimate of Reconfigurable Devices; 2.9 CONCLUSION 2.10 PROBLEM SET3: Processors; 3.1 INTRODUCTION; 3.2 PROCESSOR SELECTION FOR SOC; 3.2.1 Overview; 3.2.2 Example: Soft Processors; 3.2.3 Examples: Processor Core Selection; 3.3 BASIC CONCEPTS IN PROCESSOR ARCHITECTURE; 3.3.1 Instruction Set; 3.3.2 Some Instruction Set Conventions; 3.3.3 Branches; 3.3.4 Interrupts and Exceptions; 3.4 BASIC CONCEPTS IN PROCESSOR MICROARCHITECTURE; 3.5 BASIC ELEMENTS IN INSTRUCTION HANDLING; 3.5.1 The Instruction Decoder and Interlocks; 3.5.2 Bypassing; 3.5.3 Execution Unit; 3.6 BUFFERS: MINIMIZING PIPELINE DELAYS; 3.6.1 Mean Request Rate Buffers 3.6.2 Buffers Designed for a Fixed or Maximum Request Rate3.7 BRANCHES: REDUCING THE COST OF BRANCHES; 3.7.1 Branch Target Capture: Branch Target Buffers (BTBs); 3.7.2 Branch Prediction; 3.8 MORE ROBUST PROCESSORS: VECTOR, VERY LONG INSTRUCTION WORD (VLIW), AND SUPERSCALAR; 3.9 VECTOR PROCESSORS AND VECTOR INSTRUCTION EXTENSIONS; 3.9.1 Vector Functional Units; 3.10 VLIW PROCESSORS; 3.11 SUPERSCALAR PROCESSORS; 3.11.1 Data Dependencies; 3.11.2 Detecting Instruction Concurrency; 3.11.3 A Simple Implementation; 3.11.4 Preserving State with Out-of-Order Execution 3.12 PROCESSOR EVOLUTION AND TWO EXAMPLES |
| Record Nr. | UNINA-9910139647903321 |
|
Flynn Michael J
|
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| Hoboken, : Wiley, 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Computer System Design : System-on-Chip
| Computer System Design : System-on-Chip |
| Autore | Flynn Michael J |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, : Wiley, 2011 |
| Descrizione fisica | 1 online resource (356 p.) |
| Disciplina | 004.1 |
| Altri autori (Persone) | LukWayne |
| Soggetto topico |
Systems on a chip
Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN |
1-283-15735-7
9786613157355 1-118-00991-6 1-118-00992-4 1-118-00990-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
COMPUTER SYSTEM DESIGN; CONTENTS; PREFACE; LIST OF ABBREVIATIONS AND ACRONYMS; 1: Introduction to the Systems Approach; 1.1 SYSTEM ARCHITECTURE: AN OVERVIEW; 1.2 COMPONENTS OF THE SYSTEM: PROCESSORS, MEMORIES, AND INTERCONNECTS; 1.3 HARDWARE AND SOFTWARE: PROGRAMMABILITY VERSUS PERFORMANCE; 1.4 PROCESSOR ARCHITECTURES; 1.4.1 Processor: A Functional View; 1.4.2 Processor: An Architectural View; 1.5 MEMORY AND ADDRESSING; 1.5.1 SOC Memory Examples; 1.5.2 Addressing: The Architecture of Memory; 1.5.3 Memory for SOC Operating System; 1.6 SYSTEM-LEVEL INTERCONNECTION; 1.6.1 Bus-Based Approach
1.6.2 Network-on-Chip Approach1.7 AN APPROACH FOR SOC DESIGN; 1.7.1 Requirements and Specifications; 1.7.2 Design Iteration; 1.8 SYSTEM ARCHITECTURE AND COMPLEXITY; 1.9 PRODUCT ECONOMICS AND IMPLICATIONS FOR SOC; 1.9.1 Factors Affecting Product Costs; 1.9.2 Modeling Product Economics and Technology Complexity: The Lesson for SOC; 1.10 DEALING WITH DESIGN COMPLEXITY; 1.10.1 Buying IP; 1.10.2 Reconfiguration; 1.11 CONCLUSIONS; 1.12 PROBLEM SET; 2: Chip Basics: Time, Area, Power, Reliability, and Configurability; 2.1 INTRODUCTION; 2.1.1 Design Trade-Offs; 2.1.2 Requirements and Specifications 2.2 CYCLE TIME2.2.1 Defining a Cycle; 2.2.2 Optimum Pipeline; 2.2.3 Performance; 2.3 DIE AREA AND COST; 2.3.1 Processor Area; 2.3.2 Processor Subunits; 2.4 IDEAL AND PRACTICAL SCALING; 2.5 POWER; 2.6 AREA-TIME-POWER TRADE-OFFS IN PROCESSOR DESIGN; 2.6.1 Workstation Processor; 2.6.2 Embedded Processor; 2.7 RELIABILITY; 2.7.1 Dealing with Physical Faults; 2.7.2 Error Detection and Correction; 2.7.3 Dealing with Manufacturing Faults; 2.7.4 Memory and Function Scrubbing; 2.8 CONFIGURABILITY; 2.8.1 Why Reconfigurable Design?; 2.8.2 Area Estimate of Reconfigurable Devices; 2.9 CONCLUSION 2.10 PROBLEM SET3: Processors; 3.1 INTRODUCTION; 3.2 PROCESSOR SELECTION FOR SOC; 3.2.1 Overview; 3.2.2 Example: Soft Processors; 3.2.3 Examples: Processor Core Selection; 3.3 BASIC CONCEPTS IN PROCESSOR ARCHITECTURE; 3.3.1 Instruction Set; 3.3.2 Some Instruction Set Conventions; 3.3.3 Branches; 3.3.4 Interrupts and Exceptions; 3.4 BASIC CONCEPTS IN PROCESSOR MICROARCHITECTURE; 3.5 BASIC ELEMENTS IN INSTRUCTION HANDLING; 3.5.1 The Instruction Decoder and Interlocks; 3.5.2 Bypassing; 3.5.3 Execution Unit; 3.6 BUFFERS: MINIMIZING PIPELINE DELAYS; 3.6.1 Mean Request Rate Buffers 3.6.2 Buffers Designed for a Fixed or Maximum Request Rate3.7 BRANCHES: REDUCING THE COST OF BRANCHES; 3.7.1 Branch Target Capture: Branch Target Buffers (BTBs); 3.7.2 Branch Prediction; 3.8 MORE ROBUST PROCESSORS: VECTOR, VERY LONG INSTRUCTION WORD (VLIW), AND SUPERSCALAR; 3.9 VECTOR PROCESSORS AND VECTOR INSTRUCTION EXTENSIONS; 3.9.1 Vector Functional Units; 3.10 VLIW PROCESSORS; 3.11 SUPERSCALAR PROCESSORS; 3.11.1 Data Dependencies; 3.11.2 Detecting Instruction Concurrency; 3.11.3 A Simple Implementation; 3.11.4 Preserving State with Out-of-Order Execution 3.12 PROCESSOR EVOLUTION AND TWO EXAMPLES |
| Altri titoli varianti | System-on-chip |
| Record Nr. | UNINA-9910826714103321 |
|
Flynn Michael J
|
||
| Hoboken, : Wiley, 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Embedded SOPC design with NIOS II processor and VHDL examples [[electronic resource] /] / Pong P. Chu
| Embedded SOPC design with NIOS II processor and VHDL examples [[electronic resource] /] / Pong P. Chu |
| Autore | Chu Pong P. <1959-> |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley, c2011 |
| Descrizione fisica | 1 online resource (738 p.) |
| Disciplina |
621.392
621.395 |
| Soggetto topico |
Systems on a chip
Field programmable gate arrays Computer input-output equipment - Design and construction VHDL (Computer hardware description language) |
| ISBN |
1-283-28288-7
9786613282880 1-118-14653-0 1-118-14652-2 1-118-14650-6 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Embedded SOPC Design with Nios II Processor and VHDL Examples; CONTENTS; Preface; Acknowledgments; 1 Overview of Embedded System; 1.1 Introduction; 1.1.1 Definition of an embedded system; 1.1.2 Example systems; 1.2 System design requirements; 1.3 Embedded SoPC systems; 1.3.1 Basic development flow; 1.4 Book organization; 1.5 Bibliographic notes; PART I BASIC DIGITAL CIRCUITS DEVELOPMENT; 2 Gate-level Combinational Circuit; 2.1 Overview of VHDL; 2.2 General description; 2.2.1 Basic lexical rules; 2.2.2 Library and package; 2.2.3 Entity declaration; 2.2.4 Data type and operators
2.2.5 Architecture body2.2.6 Code of a 2-bit comparator; 2.3 Structural description; 2.4 Testbench; 2.5 Bibliographic notes; 2.6 Suggested experiments; 2.6.1 Code for gate-level greater-than circuit; 2.6.2 Code for gate-level binary decoder; 3 Overview of FPGA and EDA Software; 3.1 FPGA; 3.1.1 Overview of a general FPGA device; 3.1.2 Overview of the Altera Cyclone II devices; 3.2 Overview of the Altera DE1 and DE2 boards; 3.3 Development flow; 3.4 Overview of Quartus II; 3.5 Short tutorial of Quartus II; 3.5.1 Create the design project; 3.5.2 Create a testbench and perform the RTL simulation 3.5.3 Compile the project3.5.4 Perform timing analysis; 3.5.5 Program the FPGA device; 3.6 Short tutorial on the ModelSim HDL simulator; 3.7 Bibliographic notes; 3.8 Suggested experiments; 3.8.1 Gate-level greater-than circuit; 3.8.2 Gate-level binary decoder; 4 RT-level Combinational Circuit; 4.1 RT-level components; 4.1.1 Relational operators; 4.1.2 Arithmetic operators; 4.1.3 Other synthesis-related VHDL constructs; 4.1.4 Summary; 4.2 Routing circuit with concurrent assignment statements; 4.2.1 Conditional signal assignment statement; 4.2.2 Selected signal assignment statement 4.3 Modeling with a process4.3.1 Process; 4.3.2 Sequential signal assignment statement; 4.4 Routing circuit with if and case statements; 4.4.1 If statement; 4.4.2 Case statement; 4.4.3 Comparison to concurrent statements; 4.4.4 Unintended memory; 4.5 Constants and generics; 4.5.1 Constants; 4.5.2 Generics; 4.6 Design examples; 4.6.1 Hexadecimal digit to seven-segment LED decoder; 4.6.2 Sign-magnitude adder; 4.6.3 Barrel shifter; 4.6.4 Simplified floating-point adder; 4.7 Bibliographic notes; 4.8 Suggested experiments; 4.8.1 Multi-function barrel shifter; 4.8.2 Dual-priority encoder 4.8.3 BCD incrementor4.8.4 Floating-point greater-than circuit; 4.8.5 Floating-point and signed integer conversion circuit; 4.8.6 Enhanced floating-point adder; 5 Regular Sequential Circuit; 5.1 Introduction; 5.1.1 D FF and register; 5.1.2 Synchronous system; 5.1.3 Code development; 5.2 HDL code of the basic storage elements; 5.2.1 D FF; 5.2.2 Register; 5.2.3 Register file; 5.2.4 SRAM; 5.3 Simple design examples; 5.3.1 Shift register; 5.3.2 Binary counter and variant; 5.4 Testbench for sequential circuits; 5.5 Timing analysis; 5.5.1 Timing parameters; 5.5.2 Timing considerations in Quartus II 5.6 Case study |
| Record Nr. | UNINA-9910141240503321 |
|
Chu Pong P. <1959->
|
||
| Hoboken, N.J., : Wiley, c2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Embedded SOPC design with NIOS II processor and VHDL examples / / Pong P. Chu
| Embedded SOPC design with NIOS II processor and VHDL examples / / Pong P. Chu |
| Autore | Chu Pong P. <1959-> |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley, c2011 |
| Descrizione fisica | 1 online resource (738 p.) |
| Disciplina |
621.392
621.395 |
| Soggetto topico |
Systems on a chip
Field programmable gate arrays Computer input-output equipment - Design and construction VHDL (Computer hardware description language) |
| ISBN |
1-283-28288-7
9786613282880 1-118-14653-0 1-118-14652-2 1-118-14650-6 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Embedded SOPC Design with Nios II Processor and VHDL Examples; CONTENTS; Preface; Acknowledgments; 1 Overview of Embedded System; 1.1 Introduction; 1.1.1 Definition of an embedded system; 1.1.2 Example systems; 1.2 System design requirements; 1.3 Embedded SoPC systems; 1.3.1 Basic development flow; 1.4 Book organization; 1.5 Bibliographic notes; PART I BASIC DIGITAL CIRCUITS DEVELOPMENT; 2 Gate-level Combinational Circuit; 2.1 Overview of VHDL; 2.2 General description; 2.2.1 Basic lexical rules; 2.2.2 Library and package; 2.2.3 Entity declaration; 2.2.4 Data type and operators
2.2.5 Architecture body2.2.6 Code of a 2-bit comparator; 2.3 Structural description; 2.4 Testbench; 2.5 Bibliographic notes; 2.6 Suggested experiments; 2.6.1 Code for gate-level greater-than circuit; 2.6.2 Code for gate-level binary decoder; 3 Overview of FPGA and EDA Software; 3.1 FPGA; 3.1.1 Overview of a general FPGA device; 3.1.2 Overview of the Altera Cyclone II devices; 3.2 Overview of the Altera DE1 and DE2 boards; 3.3 Development flow; 3.4 Overview of Quartus II; 3.5 Short tutorial of Quartus II; 3.5.1 Create the design project; 3.5.2 Create a testbench and perform the RTL simulation 3.5.3 Compile the project3.5.4 Perform timing analysis; 3.5.5 Program the FPGA device; 3.6 Short tutorial on the ModelSim HDL simulator; 3.7 Bibliographic notes; 3.8 Suggested experiments; 3.8.1 Gate-level greater-than circuit; 3.8.2 Gate-level binary decoder; 4 RT-level Combinational Circuit; 4.1 RT-level components; 4.1.1 Relational operators; 4.1.2 Arithmetic operators; 4.1.3 Other synthesis-related VHDL constructs; 4.1.4 Summary; 4.2 Routing circuit with concurrent assignment statements; 4.2.1 Conditional signal assignment statement; 4.2.2 Selected signal assignment statement 4.3 Modeling with a process4.3.1 Process; 4.3.2 Sequential signal assignment statement; 4.4 Routing circuit with if and case statements; 4.4.1 If statement; 4.4.2 Case statement; 4.4.3 Comparison to concurrent statements; 4.4.4 Unintended memory; 4.5 Constants and generics; 4.5.1 Constants; 4.5.2 Generics; 4.6 Design examples; 4.6.1 Hexadecimal digit to seven-segment LED decoder; 4.6.2 Sign-magnitude adder; 4.6.3 Barrel shifter; 4.6.4 Simplified floating-point adder; 4.7 Bibliographic notes; 4.8 Suggested experiments; 4.8.1 Multi-function barrel shifter; 4.8.2 Dual-priority encoder 4.8.3 BCD incrementor4.8.4 Floating-point greater-than circuit; 4.8.5 Floating-point and signed integer conversion circuit; 4.8.6 Enhanced floating-point adder; 5 Regular Sequential Circuit; 5.1 Introduction; 5.1.1 D FF and register; 5.1.2 Synchronous system; 5.1.3 Code development; 5.2 HDL code of the basic storage elements; 5.2.1 D FF; 5.2.2 Register; 5.2.3 Register file; 5.2.4 SRAM; 5.3 Simple design examples; 5.3.1 Shift register; 5.3.2 Binary counter and variant; 5.4 Testbench for sequential circuits; 5.5 Timing analysis; 5.5.1 Timing parameters; 5.5.2 Timing considerations in Quartus II 5.6 Case study |
| Record Nr. | UNINA-9910808346303321 |
|
Chu Pong P. <1959->
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| Hoboken, N.J., : Wiley, c2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Enhanced virtual prototyping for heterogeneous systems / / Muhammad Hassan, Daniel Grosse, and Rolf Drechsler
| Enhanced virtual prototyping for heterogeneous systems / / Muhammad Hassan, Daniel Grosse, and Rolf Drechsler |
| Autore | Hassan Muhammad |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , [2022] |
| Descrizione fisica | 1 online resource (181 pages) |
| Disciplina | 620.0042 |
| Soggetto topico |
Systems on a chip
Prototypes, Engineering |
| ISBN | 3-031-05574-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910627272503321 |
|
Hassan Muhammad
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| Cham, Switzerland : , : Springer, , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Fifth International Workshop on System-on-Chip for Real-Time Applications : proceedings : 20-24 July, 2005, Banff, Alberta, Canada
| Fifth International Workshop on System-on-Chip for Real-Time Applications : proceedings : 20-24 July, 2005, Banff, Alberta, Canada |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society, 2004 |
| Disciplina | 621.3815 |
| Soggetto topico |
Application specific integrated circuits - Design and construction
Systems on a chip Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN | 1-5090-9941-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996206220603316 |
| [Place of publication not identified], : IEEE Computer Society, 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Fifth International Workshop on System-on-Chip for Real-Time Applications : proceedings : 20-24 July, 2005, Banff, Alberta, Canada
| Fifth International Workshop on System-on-Chip for Real-Time Applications : proceedings : 20-24 July, 2005, Banff, Alberta, Canada |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society, 2004 |
| Disciplina | 621.3815 |
| Soggetto topico |
Application specific integrated circuits - Design and construction
Systems on a chip Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN | 1-5090-9941-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910142340703321 |
| [Place of publication not identified], : IEEE Computer Society, 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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