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Enhanced phase-locked loop structures for power and energy applications / / Masoud Karimi-Ghartemani
Enhanced phase-locked loop structures for power and energy applications / / Masoud Karimi-Ghartemani
Autore Karimi-Ghartema Masoud
Pubbl/distr/stampa Hoboken, New Jersey : , : John Wiley & Sons, , 2014
Descrizione fisica 1 online resource (230 p.)
Disciplina 621.31/7
Collana IEEE Press Series on Microelectronic Systems
Soggetto topico Phase-locked loops
Electric power systems - Equipment and supplies
Power electronics
ISBN 1-118-79513-X
1-118-79516-4
Classificazione TEC008010
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto ENHANCED PHASE-LOCKED LOOP STRUCTURES FOR POWER AND ENERGY APPLICATIONS; Copyright; BRIEF CONTENTS; CONTENTS; PREFACE; ACKNOWLEDGMENTS; ACRONYMS; SYMBOLS; INTRODUCTION; I PLL STRUCTURES FOR SINGLE-PHASEAPPLICATIONS; 1 PLL Basics and Standard Structure; 1.1 Standard PLL Structure; 1.2 Approximate Linear Model; 1.3 Loop Filter Design; 1.4 Remarks; 1.5 Numerical Results; 1.6 Summary and Conclusion; Problems; 2 Enhanced Phase-Locked Loop; 2.1 Structure of EPLL; 2.2 Removal of Double-Frequency Error; 2.3 Linear Analysis; 2.4 Derivation of EPLL Using Gradient Method; 2.5 Pseudolinear EPLL
2.6 Derivation of PL-EPLL from Newton Approach2.7 Linear Time Invariant EPLL; 2.8 LTI-EPLL as a Resonant Controller; 2.9 Extension of LTI-EPLL as a General Transfer Function; 2.10 Resonant Controller with Phase Compensation; 2.11 VCO-Less Representation of EPLL; 2.12 VCO-Less EPLL versus ANF and SOGI-FLL; 2.13 EPLL and Droop Control Method; 2.14 Adjustment of EPLL Parameters; 2.15 Numerical Results; 2.16 Summary and Conclusion; Problems; 3 EPLL Extensions and Modifications; 3.1 Prefiltering and Postfiltering; 3.2 In-Loop Filters and Concept of Windowing; 3.3 Design of W-EPLL
3.4 Estimation and Rejection of DC Component3.5 Estimation and Rejection of Harmonics; 3.6 Mitigation of Multiple Harmonics Using SingleBand-Stop Filter; 3.7 Estimation and Rejection of Interharmonics; 3.8 EPLL with Generalized Filtering; 3.9 Soft Start and Problem of Phase Jumps; 3.10 Summary and Conclusion; Problems; 4 Digital Implementation of EPLL; 4.1 First-Order Digitization; 4.2 LTI-EPLL Resonant Controller; 4.3 Robustness in Low Sampling Frequency Applications; 4.4 Robustness in Fixed-Point, High Sampling FrequencyApplications; 4.5 Summary and Conclusion; Problems
5 Integrated Synchronization and Control5.1 Brief Review of Synronization/Control Methods; 5.2 ISC Method; 5.3 Stability Analysis of ISC Method; 5.4 Design Algorithm for ISC Method; 5.5 Comments on Reference Values; 5.6 Power Quality Issues; 5.7 Soft Start Process; 5.8 LCL Output Filter; 5.9 Sensitivity Analysis; 5.10 Numerical Results; 5.11 Summary and Conclusion; Problems; II PLL STRUCTURES FOR THREE-PHASEAPPLICATIONS; 6 Synchronous Reference Frame PLL; 6.1 Structure of SRF-PLL; 6.2 Linear Model and Design; 6.3 Alternative Representation of SRF-PLL; 6.4 SRF-PLL Operation in Stationary Frame
6.5 Single-Phase SRF-PLL6.6 Correspondence between SRF-PLL and Single-PhaseEPLL; 6.7 Impact of Unbalance, DC, and Harmonics on SRF-PLL; 6.8 Numerical Results; 6.9 Summary and Conclusion; Problems; 7 Three-Phase EPLL-I; 7.1 Structure of Three-Phase EPLL-I; 7.2 Relationship between 3EPLL-I and SRF-PLL; 7.3 3EPLL-I in Stationary Frame; 7.4 Mathematical Derivation of 3EPLL-I; 7.5 LTI-3EPLL-I; 7.6 VCO-Less Representation of 3EPLL-I; 7.7 Design Guidelines for 3EPLL-I; 7.8 Numerical Results; 7.9 Summary and Conclusion; Problems; 8 Three-Phase EPLL-II; 8.1 Structure of Three-Phase EPLL-II
8.2 Derivation of Three-Phase EPLL-II
Record Nr. UNINA-9910132218303321
Karimi-Ghartema Masoud  
Hoboken, New Jersey : , : John Wiley & Sons, , 2014
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Enhanced phase-locked loop structures for power and energy applications / / Masoud Karimi-Ghartemani
Enhanced phase-locked loop structures for power and energy applications / / Masoud Karimi-Ghartemani
Autore Karimi-Ghartema Masoud
Pubbl/distr/stampa Hoboken, New Jersey : , : John Wiley & Sons, , 2014
Descrizione fisica 1 online resource (230 p.)
Disciplina 621.31/7
Collana IEEE Press Series on Microelectronic Systems
Soggetto topico Phase-locked loops
Electric power systems - Equipment and supplies
Power electronics
ISBN 1-118-79513-X
1-118-79516-4
Classificazione TEC008010
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto ENHANCED PHASE-LOCKED LOOP STRUCTURES FOR POWER AND ENERGY APPLICATIONS; Copyright; BRIEF CONTENTS; CONTENTS; PREFACE; ACKNOWLEDGMENTS; ACRONYMS; SYMBOLS; INTRODUCTION; I PLL STRUCTURES FOR SINGLE-PHASEAPPLICATIONS; 1 PLL Basics and Standard Structure; 1.1 Standard PLL Structure; 1.2 Approximate Linear Model; 1.3 Loop Filter Design; 1.4 Remarks; 1.5 Numerical Results; 1.6 Summary and Conclusion; Problems; 2 Enhanced Phase-Locked Loop; 2.1 Structure of EPLL; 2.2 Removal of Double-Frequency Error; 2.3 Linear Analysis; 2.4 Derivation of EPLL Using Gradient Method; 2.5 Pseudolinear EPLL
2.6 Derivation of PL-EPLL from Newton Approach2.7 Linear Time Invariant EPLL; 2.8 LTI-EPLL as a Resonant Controller; 2.9 Extension of LTI-EPLL as a General Transfer Function; 2.10 Resonant Controller with Phase Compensation; 2.11 VCO-Less Representation of EPLL; 2.12 VCO-Less EPLL versus ANF and SOGI-FLL; 2.13 EPLL and Droop Control Method; 2.14 Adjustment of EPLL Parameters; 2.15 Numerical Results; 2.16 Summary and Conclusion; Problems; 3 EPLL Extensions and Modifications; 3.1 Prefiltering and Postfiltering; 3.2 In-Loop Filters and Concept of Windowing; 3.3 Design of W-EPLL
3.4 Estimation and Rejection of DC Component3.5 Estimation and Rejection of Harmonics; 3.6 Mitigation of Multiple Harmonics Using SingleBand-Stop Filter; 3.7 Estimation and Rejection of Interharmonics; 3.8 EPLL with Generalized Filtering; 3.9 Soft Start and Problem of Phase Jumps; 3.10 Summary and Conclusion; Problems; 4 Digital Implementation of EPLL; 4.1 First-Order Digitization; 4.2 LTI-EPLL Resonant Controller; 4.3 Robustness in Low Sampling Frequency Applications; 4.4 Robustness in Fixed-Point, High Sampling FrequencyApplications; 4.5 Summary and Conclusion; Problems
5 Integrated Synchronization and Control5.1 Brief Review of Synronization/Control Methods; 5.2 ISC Method; 5.3 Stability Analysis of ISC Method; 5.4 Design Algorithm for ISC Method; 5.5 Comments on Reference Values; 5.6 Power Quality Issues; 5.7 Soft Start Process; 5.8 LCL Output Filter; 5.9 Sensitivity Analysis; 5.10 Numerical Results; 5.11 Summary and Conclusion; Problems; II PLL STRUCTURES FOR THREE-PHASEAPPLICATIONS; 6 Synchronous Reference Frame PLL; 6.1 Structure of SRF-PLL; 6.2 Linear Model and Design; 6.3 Alternative Representation of SRF-PLL; 6.4 SRF-PLL Operation in Stationary Frame
6.5 Single-Phase SRF-PLL6.6 Correspondence between SRF-PLL and Single-PhaseEPLL; 6.7 Impact of Unbalance, DC, and Harmonics on SRF-PLL; 6.8 Numerical Results; 6.9 Summary and Conclusion; Problems; 7 Three-Phase EPLL-I; 7.1 Structure of Three-Phase EPLL-I; 7.2 Relationship between 3EPLL-I and SRF-PLL; 7.3 3EPLL-I in Stationary Frame; 7.4 Mathematical Derivation of 3EPLL-I; 7.5 LTI-3EPLL-I; 7.6 VCO-Less Representation of 3EPLL-I; 7.7 Design Guidelines for 3EPLL-I; 7.8 Numerical Results; 7.9 Summary and Conclusion; Problems; 8 Three-Phase EPLL-II; 8.1 Structure of Three-Phase EPLL-II
8.2 Derivation of Three-Phase EPLL-II
Record Nr. UNINA-9910830130103321
Karimi-Ghartema Masoud  
Hoboken, New Jersey : , : John Wiley & Sons, , 2014
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Frequency acquisition techniques for phase locked loop / / author Daniel Talbot
Frequency acquisition techniques for phase locked loop / / author Daniel Talbot
Autore Talbot Daniel (Daniel B.)
Pubbl/distr/stampa Hoboken, New Jersey : , : John Wiley & Sons, Inc., , [2012]
Descrizione fisica 1 online resource (238 p.)
Disciplina 621.3815/486
621.382
Soggetto topico Frequency synthesizers
Phase-locked loops
ISBN 1-118-38330-3
1-283-59323-8
9786613905680
1-118-38331-1
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Preface xi -- 1 Introduction 1 -- 2 A Review of PLL Fundamentals 3 -- 2.1 What is a PLL?, 3 -- 2.2 Second-Order PLL, 7 -- 2.3 Second-Order PLL Type One, 7 -- 2.4 Second-Order PLL Type Two, 7 -- 2.5 Higher-Order PLL's, 8 -- 2.6 Disturbances, 8 -- 2.7 Frequency Steering and Capture, 9 -- 2.8 Effect of DC Offsets or Noise Prior to the Loop Filter, 10 -- 2.9 Injection-Locked Oscillations, 15 -- 3 Simulating the PLL Linear Operation Mode 17 -- 3.1 Linear Model, 17 -- 3.2 A Word About Damping, 19 -- 4 Sideband Suppression Filtering 21 -- 4.1 Reference Sidebands and VCO Pushing, 21 -- 4.2 Superiority of the Cauer (or Elliptical) Filter, 22 -- 5 Pros and Cons of Sampled Data Phase Detection 25 -- 5.1 What are the Forms of Sampled Data Phase Detectors?, 25 -- 5.2 A. Ramp and Sample Analog Phase Detector, 25 -- 5.3 B. The RF Sampling Phase Detector, 28 -- 5.4 C. Edge-Triggered S-R Flip-Flop, 29 -- 5.5 D. Edge-Triggered Flip-Flop Ensemble, 31 -- 5.6 E. Sample and Hold as a Phase Detector, 31 -- 6 Phase Compression 33 -- 7 Hard Limiting of a Signal Plus Noise 35 -- 8 Phase Noise and Other Spurious Interferers 39 -- 8.1 The Mechanism for Phase Noise in an Oscillator, 42 -- 8.2 Additive Noise in an FM Channel and the Bowtie, 42 -- 8.3 Importance of FM Theory to Frequency Acquisition, 45 -- 9 Impulse Modulation and Noise Aliasing 47 -- 9.1 Impulse Train Spectrum, 47 -- 9.2 Sampling Phase Detector Noise, 47 -- 9.3 Spur Aliasing, 50 -- 10 Time and Phase Jitter, Heterodyning, and Multiplication 53 -- 10.1 Heterodyning and Resulting Time Jitter, 53 -- 10.2 Frequency Multiplication and Angle Modulation Index, 54 -- 10.3 Frequency Multiplication's Role in Carrier Recovery, 54 -- 11 Carrier Recovery Applications and Acquisition 57 -- 11.1 Frequency Multiplier Carrier Recovery in General, 57 -- 11.2 The Simplest Form of Costas PLL, 59 -- 11.3 Higher Level Quadrature Demodulation Costas PLL, 61 -- 11.4 False Lock in BPSK Costas PLL, 62 -- 11.5 Additional Measures for Prevention of False Locking, 65.
11.6 False Lock Prevention Using DC Offset, 72 -- 12 Notes on Sweep Methods 73 -- 12.1 Sweep Waveform Superimposed Directly on VCO Input, 73 -- 12.2 Maximum Sweep Rate (Acceleration), 74 -- 12.3 False Lock due to High-Order Filtering, 77 -- 12.4 Sweep Waveform Applied Directly to PLL Loop Integrator, 79 -- 12.5 Self-Sweeping PLL, 79 -- 13 Nonsweep Acquisition Methods 85 -- 13.1 Delay Line Frequency Discriminator, 85 -- 13.2 The Fully Unbalanced Quadricorrelator, 87 -- 13.3 The Fully Balanced Quadricorrelator, 88 -- 13.4 The Multipulse Balanced Quadricorrelator, 89 -- 13.5 Conclusion Regarding Pulsed Frequency Detection, 91 -- 13.6 Quadricorrelator Linearity, 92 -- 13.7 Limiter Asymmetry due to DC Offset, 97 -- 13.8 Taylor Series Demonstrates Second-Order-Caused DC Offset, 100 -- 13.9 Third-Order Intermodulation Distortion and Taylor Series, 101 -- 14 AM Rejection in Frequency Detection Schemes 105 -- 14.1 AM Rejection with Limiter and Interferer, 105 -- 14.2 AM Rejection of the Balanced Limiter/Quadricorrelator Versus the Limiter/Discriminator in the Presence of a Single Spur, 106 -- 14.3 Impairment due to Filter Response Tilt (Asymmetry), 110 -- 14.4 Bandpass Filter Geometric and Arithmetic Symmetry, 114 -- 14.5 Comments on Degree of Scrutiny, 117 -- 15 Interfacing the Frequency Discriminator to the PLL 119 -- 15.1 Continuous Connection: Pros and Cons, 119 -- 15.2 Connection to PLL via a Dead Band, 120 -- 15.3 Switched Connection, 121 -- 16 Actual Frequency Discriminator Implementations 125 -- 16.1 Quadricorrelator, Low-Frequency Implementation, 125 -- 16.2 Frequency Ratio Calculating Circuit for Wide-Bandwidth Use, 128 -- 16.3 Dividing the Frequency and Resultant Implementation, 131 -- 16.4 Marriage of Both Frequency and Phaselock Loops, 135 -- 16.5 Comments on Spurs' Numerical Influence on the VCO, 141 -- 16.6 Frequency Compression, 143 -- 17 Clock Recovery Using a PLL 145 -- 17.1 PLL Only, 145 -- 17.2 PLL with Sideband Crystal Filter(s), 152 -- 17.3 PLL with Sideband Cavity Filter, 153.
17.4 The Hogge Phase Detector, 161 -- 17.5 Bang-Bang Phase Detectors, 162 -- 18 Frequency Synthesis Applications 165 -- 18.1 Direct Frequency Synthesis with Wadley Loop, 166 -- 18.2 Indirect Frequency Synthesis with PLLs, 173 -- 18.3 Simple Frequency Acquisition Improvement for a PLL, 175 -- 18.4 Hybrid Frequency Synthesis with DDS and PLL, 176 -- 18.5 Phase Noise Considerations, 181 -- 18.6 Pros and Cons of DDS-Augmented Synthesis, 185 -- 18.7 Multiple Loops, 185 -- 18.8 Reference Signal Considerations and Filtering, 186 -- 18.9 SNR of Various Phase Detectors, 187 -- 18.10 Phase Detector Dead Band (Dead Zone) and Remediation, 187 -- 18.11 Sideband Energy due to DC Offset Following Phase Detector, 191 -- 18.12 Brute Force PLL Frequency Acquisition via Speedup, 193 -- 18.13 Short-Term and Long-Term Settling, 193 -- 18.14 N-over-M Synthesis, 193 -- 19 Injection Pulling of Multiple VCO's as in a Serdes 195 -- 19.1 Allowable Coupling Between any Two VCOs Versus Q and BW, 195 -- 19.2 Topology Suggestion for Eliminating the Injection Pulling, 195 -- 20 Digital PLL Example 199 -- 21 Conclusion 203 -- References 205 -- Index 209.
Record Nr. UNINA-9910141433803321
Talbot Daniel (Daniel B.)  
Hoboken, New Jersey : , : John Wiley & Sons, Inc., , [2012]
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Frequency acquisition techniques for phase locked loop / / author Daniel Talbot
Frequency acquisition techniques for phase locked loop / / author Daniel Talbot
Autore Talbot Daniel (Daniel B.)
Pubbl/distr/stampa Hoboken, New Jersey : , : John Wiley & Sons, Inc., , [2012]
Descrizione fisica 1 online resource (238 p.)
Disciplina 621.3815/486
621.382
Soggetto topico Frequency synthesizers
Phase-locked loops
ISBN 1-118-38330-3
1-283-59323-8
9786613905680
1-118-38331-1
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Preface xi -- 1 Introduction 1 -- 2 A Review of PLL Fundamentals 3 -- 2.1 What is a PLL?, 3 -- 2.2 Second-Order PLL, 7 -- 2.3 Second-Order PLL Type One, 7 -- 2.4 Second-Order PLL Type Two, 7 -- 2.5 Higher-Order PLL's, 8 -- 2.6 Disturbances, 8 -- 2.7 Frequency Steering and Capture, 9 -- 2.8 Effect of DC Offsets or Noise Prior to the Loop Filter, 10 -- 2.9 Injection-Locked Oscillations, 15 -- 3 Simulating the PLL Linear Operation Mode 17 -- 3.1 Linear Model, 17 -- 3.2 A Word About Damping, 19 -- 4 Sideband Suppression Filtering 21 -- 4.1 Reference Sidebands and VCO Pushing, 21 -- 4.2 Superiority of the Cauer (or Elliptical) Filter, 22 -- 5 Pros and Cons of Sampled Data Phase Detection 25 -- 5.1 What are the Forms of Sampled Data Phase Detectors?, 25 -- 5.2 A. Ramp and Sample Analog Phase Detector, 25 -- 5.3 B. The RF Sampling Phase Detector, 28 -- 5.4 C. Edge-Triggered S-R Flip-Flop, 29 -- 5.5 D. Edge-Triggered Flip-Flop Ensemble, 31 -- 5.6 E. Sample and Hold as a Phase Detector, 31 -- 6 Phase Compression 33 -- 7 Hard Limiting of a Signal Plus Noise 35 -- 8 Phase Noise and Other Spurious Interferers 39 -- 8.1 The Mechanism for Phase Noise in an Oscillator, 42 -- 8.2 Additive Noise in an FM Channel and the Bowtie, 42 -- 8.3 Importance of FM Theory to Frequency Acquisition, 45 -- 9 Impulse Modulation and Noise Aliasing 47 -- 9.1 Impulse Train Spectrum, 47 -- 9.2 Sampling Phase Detector Noise, 47 -- 9.3 Spur Aliasing, 50 -- 10 Time and Phase Jitter, Heterodyning, and Multiplication 53 -- 10.1 Heterodyning and Resulting Time Jitter, 53 -- 10.2 Frequency Multiplication and Angle Modulation Index, 54 -- 10.3 Frequency Multiplication's Role in Carrier Recovery, 54 -- 11 Carrier Recovery Applications and Acquisition 57 -- 11.1 Frequency Multiplier Carrier Recovery in General, 57 -- 11.2 The Simplest Form of Costas PLL, 59 -- 11.3 Higher Level Quadrature Demodulation Costas PLL, 61 -- 11.4 False Lock in BPSK Costas PLL, 62 -- 11.5 Additional Measures for Prevention of False Locking, 65.
11.6 False Lock Prevention Using DC Offset, 72 -- 12 Notes on Sweep Methods 73 -- 12.1 Sweep Waveform Superimposed Directly on VCO Input, 73 -- 12.2 Maximum Sweep Rate (Acceleration), 74 -- 12.3 False Lock due to High-Order Filtering, 77 -- 12.4 Sweep Waveform Applied Directly to PLL Loop Integrator, 79 -- 12.5 Self-Sweeping PLL, 79 -- 13 Nonsweep Acquisition Methods 85 -- 13.1 Delay Line Frequency Discriminator, 85 -- 13.2 The Fully Unbalanced Quadricorrelator, 87 -- 13.3 The Fully Balanced Quadricorrelator, 88 -- 13.4 The Multipulse Balanced Quadricorrelator, 89 -- 13.5 Conclusion Regarding Pulsed Frequency Detection, 91 -- 13.6 Quadricorrelator Linearity, 92 -- 13.7 Limiter Asymmetry due to DC Offset, 97 -- 13.8 Taylor Series Demonstrates Second-Order-Caused DC Offset, 100 -- 13.9 Third-Order Intermodulation Distortion and Taylor Series, 101 -- 14 AM Rejection in Frequency Detection Schemes 105 -- 14.1 AM Rejection with Limiter and Interferer, 105 -- 14.2 AM Rejection of the Balanced Limiter/Quadricorrelator Versus the Limiter/Discriminator in the Presence of a Single Spur, 106 -- 14.3 Impairment due to Filter Response Tilt (Asymmetry), 110 -- 14.4 Bandpass Filter Geometric and Arithmetic Symmetry, 114 -- 14.5 Comments on Degree of Scrutiny, 117 -- 15 Interfacing the Frequency Discriminator to the PLL 119 -- 15.1 Continuous Connection: Pros and Cons, 119 -- 15.2 Connection to PLL via a Dead Band, 120 -- 15.3 Switched Connection, 121 -- 16 Actual Frequency Discriminator Implementations 125 -- 16.1 Quadricorrelator, Low-Frequency Implementation, 125 -- 16.2 Frequency Ratio Calculating Circuit for Wide-Bandwidth Use, 128 -- 16.3 Dividing the Frequency and Resultant Implementation, 131 -- 16.4 Marriage of Both Frequency and Phaselock Loops, 135 -- 16.5 Comments on Spurs' Numerical Influence on the VCO, 141 -- 16.6 Frequency Compression, 143 -- 17 Clock Recovery Using a PLL 145 -- 17.1 PLL Only, 145 -- 17.2 PLL with Sideband Crystal Filter(s), 152 -- 17.3 PLL with Sideband Cavity Filter, 153.
17.4 The Hogge Phase Detector, 161 -- 17.5 Bang-Bang Phase Detectors, 162 -- 18 Frequency Synthesis Applications 165 -- 18.1 Direct Frequency Synthesis with Wadley Loop, 166 -- 18.2 Indirect Frequency Synthesis with PLLs, 173 -- 18.3 Simple Frequency Acquisition Improvement for a PLL, 175 -- 18.4 Hybrid Frequency Synthesis with DDS and PLL, 176 -- 18.5 Phase Noise Considerations, 181 -- 18.6 Pros and Cons of DDS-Augmented Synthesis, 185 -- 18.7 Multiple Loops, 185 -- 18.8 Reference Signal Considerations and Filtering, 186 -- 18.9 SNR of Various Phase Detectors, 187 -- 18.10 Phase Detector Dead Band (Dead Zone) and Remediation, 187 -- 18.11 Sideband Energy due to DC Offset Following Phase Detector, 191 -- 18.12 Brute Force PLL Frequency Acquisition via Speedup, 193 -- 18.13 Short-Term and Long-Term Settling, 193 -- 18.14 N-over-M Synthesis, 193 -- 19 Injection Pulling of Multiple VCO's as in a Serdes 195 -- 19.1 Allowable Coupling Between any Two VCOs Versus Q and BW, 195 -- 19.2 Topology Suggestion for Eliminating the Injection Pulling, 195 -- 20 Digital PLL Example 199 -- 21 Conclusion 203 -- References 205 -- Index 209.
Record Nr. UNINA-9910830451403321
Talbot Daniel (Daniel B.)  
Hoboken, New Jersey : , : John Wiley & Sons, Inc., , [2012]
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Microwave and wireless synthesizers : theory and design / / Ulrich L. Rohde, Enrico Rubiola, Jerry C. Whitaker
Microwave and wireless synthesizers : theory and design / / Ulrich L. Rohde, Enrico Rubiola, Jerry C. Whitaker
Autore Rohde Ulrich L.
Edizione [Second edition.]
Pubbl/distr/stampa Hoboken, NJ : , : Wiley, , 2021
Descrizione fisica 1 online resource (xxii, 794 pages) : illustrations
Disciplina 621.3815486
Soggetto topico Frequency synthesizers - Design and construction
Phase-locked loops
Digital electronics
Microwave circuits - Design and construction
Radio frequency
Soggetto genere / forma Electronic books.
ISBN 1-5231-4359-2
1-119-66611-2
1-119-66609-0
1-119-66612-0
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Cover -- Title Page -- Copyright -- Contents -- Author Biography -- Preface -- Important Notations -- Chapter 1 Loop Fundamentals -- 1-1 Introduction to Linear Loops -- 1-2 Characteristics of a Loop -- 1-3 Digital Loops -- 1-4 Type 1 First‐Order Loop -- 1-5 Type 1 Second‐Order Loop -- 1-6 Type 2 Second‐Order Loop -- 1-6-1 Transient Behavior of Digital Loops Using Tri‐state Phase Detectors -- 1-7 Type 2 Third‐Order Loop -- 1-7-1 Transfer Function of Type 2 Third‐Order Loop -- 1-7-2 FM Noise Suppression -- 1-8 Higher‐Order Loops -- 1-8-1 Fifth‐Order Loop Transient Response -- 1-9 Digital Loops with Mixers -- 1-10 Acquisition -- 1-10-0 Example 1 -- 1-10-1 Pull‐in Performance of the Digital Loop -- 1-10-2 Coarse Steering of the VCO as an Acquisition Aid -- 1-10-3 Loop Stability -- References -- Suggested Reading -- Chapter 2 ALMOST ALL ABOUT PHASE NOISE -- 2-1 INTRODUCTION TO PHASE NOISE -- 2-1-1 The Clock Signal -- 2-1-2 The Power Spectral Density (PSD) -- 2-1-3 Basics of Noise -- 2-1-4 Phase and Frequency Noise -- 2-2 THE ALLAN VARIANCE AND OTHER TWO‐SAMPLE VARIANCES -- 2-2-1 Frequency Counters -- 2-2-2 The Two‐Sample Variances AVAR, MVAR, and PVAR -- 2-2-3 Conversion from Spectra to Two‐Sample Variances -- 2-3 PHASE NOISE IN COMPONENTS -- 2-3-1 Amplifiers -- 2-3-2 Frequency Dividers -- 2-3-3 Frequency Multipliers -- 2-3-4 Direct Digital Synthesizer (DDS) -- 2-3-5 Phase Detectors -- 2-3-6 Noise Contribution from Power Supplies -- 2-4 PHASE NOISE IN OSCILLATORS -- 2-4-1 Modern View of the Leeson Model -- 2-4-2 Circumventing the Resonator's Thermal Noise -- 2-4-3 Oscillator Hacking -- 2-5 THE MEASUREMENT OF PHASE NOISE -- 2-5-1 Double‐Balanced Mixer Instruments -- 2-5-2 The Cross‐Spectrum Method -- 2-5-3 Digital Instruments -- 2-5-4 Pitfalls and Limitations of the Cross‐Spectrum Measurements -- 2-5-5 The Bridge (Interferometric) Method.
2-5-6 Artifacts and Oddities Often Found in the Real World -- 2-5 References -- 2-5 SUGGESTED READINGS -- 2-5-6 Power spectra and Fourier transform -- 2-5-6 Electromagnetic Compatibility -- 2-5-6 General Aspects of Noise -- 2-5-6 Phase Noise, Frequency Stability, and Measurements -- 2-5-6 Amplifiers -- 2-5-6 Frequency Dividers -- 2-5-6 Frequency Multipliers -- 2-5-6 DDS -- 2-5-6 Phase‐Frequency Detectors -- 2-5-6 Oscillators -- 2-5-6 Resonators -- 2-5-6 Double‐Balanced Mixer -- Chapter 3 Special Loops -- 3-1 Introduction -- 3-2 Direct Digital Synthesis Techniques -- 3-2-1 A First Look at Fractional N -- 3-2-2 Digital Waveform Synthesizers -- 3-2-3 Signal Quality -- 3-2-4 Future Prospects -- 3-3 Loops with Delay Line as Phase Comparators -- 3-4 Fractional Division N Synthesizers -- 3-4-1 Example Implementation -- 3-4-2 Some Special Past Patents for Fractional Division N Synthesizers -- References -- Bibliography -- FRACTIONAL DIVISION N READINGS -- Chapter 4 LOOP COMPONENTS -- 4-1 INTRODUCTION TO OSCILLATORS AND THEIR MATHEMATICAL TREATMENT -- 4-2 THE COLPITTS OSCILLATOR -- 4-2-1 Linear Approach -- 4-2-2 Design Example for a 350 MHz Fixed‐Frequency Colpitts Oscillator -- 4-2-3 Validation Circuits -- 4-2-4 Series Feedback Oscillator [5, Appendix A, pp. 384-388] -- 4-2-5 2400 MHz MOSFET‐Based Push-Pull Oscillator -- 4-2-6 Oscillators for IC Applications -- 4-2-7 Noise in Semiconductors and Circuits -- 4-2-8 Summary -- 4-3 USE OF TUNING DIODES -- 4-3-1 Diode Tuned Resonant Circuits -- 4-3-2 Practical Circuits -- 4-4 USE OF DIODE SWITCHES -- 4-4-1 Diode Switches for Electronic Band Selection -- 4-4-2 Use of Diodes for Frequency Multiplication -- 4-5 REFERENCE FREQUENCY STANDARDS -- 4-5-1 Specifying Oscillators -- 4-5-2 Typical Examples of Crystal Oscillator Specifications -- 4-6 MIXER APPLICATIONS -- 4-7 PHASE/FREQUENCY COMPARATORS -- 4-7-1 Diode Rings.
4-7-2 Exclusive ORs -- 4-7-3 Sample/Hold Detectors -- 4-7-4 Edge‐Triggered JK Master/Slave Flip‐Flops -- 4-7-5 Digital Tri‐State Comparators -- 4-8 WIDEBAND HIGH‐GAIN AMPLIFIERS -- 4-8-1 Summation Amplifiers -- 4-8-2 Differential Limiters -- 4-8-3 Isolation Amplifiers -- 4-8-4 Example Implementations -- 4-9 PROGRAMMABLE DIVIDERS -- 4-9-1 Asynchronous Counters -- 4-9-2 Programmable Synchronous Up‐/Down‐Counters -- 4-9-3 Advanced Implementation Example -- 4-9-4 Swallow Counters/Dual‐Modulus Counters -- 4-9-5 Look‐Ahead and Delay Compensation -- 4-10 LOOP FILTERS -- 4-10-1 Passive RC Filters -- 4-10-2 Active RC Filters -- 4-10-3 Active Second‐Order Low‐Pass Filters -- 4-10-4 Passive LC Filters -- 4-10-5 Spur‐Suppression Techniques -- 4-11 MICROWAVE OSCILLATOR DESIGN -- 4-11-1 The Compressed Smith Chart -- 4-11-2 Series or Parallel Resonance -- 4-11-3 Two‐Port Oscillator Design -- 4-12 MICROWAVE RESONATORS -- 4-12-1 SAW Oscillators -- 4-12-2 Dielectric Resonators -- 4-12-3 YIG Oscillators -- 4-12-4 Varactor Resonators -- 4-12-5 Ceramic Resonators -- 4-12 REFERENCES -- 4-12 SUGGESTED READINGS -- 4-12-5 Section 4‐3 Documents -- 4-12-5 Section 4‐5 Documents -- 4-12-5 Section 4‐6 Documents -- 4-12-5 Section 4‐7 Documents -- 4-12-5 Section 4‐8 Documents -- 4-12-5 Section 4.9 Documents -- 4-12-5 Section 4.10 Documents -- 4-12-5 Section 4.11 Documents -- 4-12-5 Section 4.12 Documents -- Chapter 5 Digital PLL Synthesizers -- 5-1 Multiloop Synthesizers Using Different Techniques -- 5-1-1 Direct Frequency Synthesis -- 5-1-2 Multiple Loops -- 5-2 System Analysis -- 5-3 Low‐Noise Microwave Synthesizers -- 5-3-1 Building Blocks -- 5-3-2 Output Loop Response -- 5-3-3 Low Phase Noise References: Frequency Standards -- 5-3-4 Critical Stage -- 5-3-5 Time Domain Analysis -- 5-3-6 Summary -- 5-3-7 Two Commercial Synthesizer Examples.
5-4 Microprocessor Applications in Synthesizers -- 5-5 Transceiver Applications -- 5-6 About Bits, Symbols, and Waveforms -- 5-6-1 Representation of a Modulated RF Carrier -- 5-6-2 Generation of the Modulated Carrier -- 5-6-3 Putting It all Together -- 5-6-4 Combination of Techniques -- 5-6 Acknowledgments -- 5-6 References -- 5-6 Bibliography and Suggested Reading -- Chapter 6 A High‐Performance Hybrid Synthesizer -- 6-1 Introduction -- 6-2 Basic Synthesizer Approach -- 6-3 Loop Filter Design -- 6-4 Summary -- Bibliography -- Chapter A Mathematical Review -- A-1 FUNCTIONS OF A COMPLEX VARIABLE -- A-2 COMPLEX PLANES -- A-2-1 Functions in the Complex Frequency Plane -- A-3 BODE DIAGRAM -- A-4 LAPLACE TRANSFORM -- A-4-1 The Step Function -- A-4-2 The Ramp -- A-4-3 Linearity Theorem -- A-4-4 Differentiation and Integration -- A-4-5 Initial Value Theorem -- A-4-6 Final Value Theorem -- A-4-7 The Active Integrator -- A-4-8 Locking Behavior of the PLL -- A-5 LOW‐NOISE OSCILLATOR DESIGN -- A-5-1 Example Implementation -- A-6 OSCILLATOR AMPLITUDE STABILIZATION -- A-7 VERY LOW PHASE NOISE VCO FOR 800 MHZ -- REFERENCES -- Chapter B A General‐Purpose Nonlinear Approach to the Computation of Sideband Phase Noise in Free‐Running Microwave and RF Oscillators -- B-1 Introduction -- B-2 Noise Generation in Oscillators -- B-3 Bias‐Dependent Noise Model -- B-3-1 Bias‐Dependent Model -- B-3-2 Derivation of the Model -- B-4 General Concept of Noisy Circuits -- B-4-1 Noise from Linear Elements -- B-5 Noise Figure of Mixer Circuits -- B-6 Oscillator Noise Analysis -- B-7 Limitations of the Frequency‐Conversion Approach -- B-7-1 Assumptions -- B-7-2 Conversion and Modulation Noise -- B-7-3 Properties of Modulation Noise -- B-7-4 Noise Analysis of Autonomous Circuits -- B-7-5 Conversion Noise Analysis Results -- B-7-6 Modulation Noise Analysis Results.
B-8 Summary of the Phase Noise Spectrum of the Oscillator -- B-9 Verification Examples for the Calculation of Phase Noise in Oscillators Using Nonlinear Techniques -- B-9-1 Example 1: High‐Q Case Microstrip DRO -- B-9-2 Example 2: 10 MHz Crystal Oscillator -- B-9-3 Example 3: The 1‐GHz Ceramic Resonator VCO -- B-9-4 Example 4: Low Phase Noise FET Oscillator -- B-9-5 Example 5: Millimeter‐Wave Applications -- B-9-6 Example 6: Discriminator Stabilized DRO -- B-10 Summary -- B-10 References -- Chapter C EXAMPLE OF WIRELESS SYNTHESIZERS USING COMMERCIAL ICs -- Chapter D MMIC‐BASED SYNTHESIZERS -- D-1 INTRODUCTION -- BIBLIOGRAPHY -- Chapter E ARTICLES ON DESIGN OF DIELECTRIC RESONATOR OSCILLATORS -- E-1 THE DESIGN OF AN ULTRA‐LOW PHASE NOISE DRO -- E-1-1 Basic Considerations and Component Selection -- E-1-2 Component Selection -- E-1-3 DRO Topologies -- E-1-4 Small Signal Design Approach for the Parallel Feedback Type DRO -- E-1-5 Simulated Versus Measured Results -- E-1-6 Physical Embodiment -- E-1-7 Acknowledgments -- E-1-8 Final Remarks -- REFERENCES -- BIBLIOGRAPHY -- E-2 A NOVEL OSCILLATOR DESIGN WITH METAMATERIAL‐MÖBIUS COUPLING TO A DIELECTRIC RESONATOR -- E-2-1 Abstract -- E-2-2 Introduction -- REFERENCES -- Chapter F OPTO‐ELECTRONICALLY STABILIZED RF OSCILLATORS -- F-1 INTRODUCTION -- F-1-1 Oscillator Basics -- F-1-2 Resonator Technologies -- F-1-3 Motivation for OEO -- F-1-4 Operation Principle of the OEO -- F-2 EXPERIMENTAL EVALUATION AND THERMAL STABILITY OF OEO -- F-2-1 Experimental Setup -- F-2-2 Phase Noise Measurements -- F-2-3 Thermal Sensitivity Analysis of Standard Fibers -- F-2-4 Temperature Sensitivity Measurements -- F-2-5 Temperature Sensitivity Improvement with HC‐PCF -- F-2-6 Improve Thermal Stability Versus Phase Noise Degradation -- F-2-7 Passive Temperature Compensation -- F-2-8 Improving Effective Q with Raman Amplification.
F-3 FORCED OSCILLATION TECHNIQUES OF OEO.
Record Nr. UNINA-9910555149603321
Rohde Ulrich L.  
Hoboken, NJ : , : Wiley, , 2021
Materiale a stampa
Lo trovi qui: Univ. Federico II
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Microwave and wireless synthesizers : theory and design / / Ulrich L. Rohde, Enrico Rubiola, Jerry C. Whitaker
Microwave and wireless synthesizers : theory and design / / Ulrich L. Rohde, Enrico Rubiola, Jerry C. Whitaker
Autore Rohde Ulrich L.
Edizione [Second edition.]
Pubbl/distr/stampa Hoboken, NJ : , : Wiley, , 2021
Descrizione fisica 1 online resource (xxii, 794 pages) : illustrations
Disciplina 621.3815486
Soggetto topico Frequency synthesizers - Design and construction
Phase-locked loops
Digital electronics
Microwave circuits - Design and construction
Radio frequency
ISBN 1-5231-4359-2
1-119-66611-2
1-119-66609-0
1-119-66612-0
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Cover -- Title Page -- Copyright -- Contents -- Author Biography -- Preface -- Important Notations -- Chapter 1 Loop Fundamentals -- 1-1 Introduction to Linear Loops -- 1-2 Characteristics of a Loop -- 1-3 Digital Loops -- 1-4 Type 1 First‐Order Loop -- 1-5 Type 1 Second‐Order Loop -- 1-6 Type 2 Second‐Order Loop -- 1-6-1 Transient Behavior of Digital Loops Using Tri‐state Phase Detectors -- 1-7 Type 2 Third‐Order Loop -- 1-7-1 Transfer Function of Type 2 Third‐Order Loop -- 1-7-2 FM Noise Suppression -- 1-8 Higher‐Order Loops -- 1-8-1 Fifth‐Order Loop Transient Response -- 1-9 Digital Loops with Mixers -- 1-10 Acquisition -- 1-10-0 Example 1 -- 1-10-1 Pull‐in Performance of the Digital Loop -- 1-10-2 Coarse Steering of the VCO as an Acquisition Aid -- 1-10-3 Loop Stability -- References -- Suggested Reading -- Chapter 2 ALMOST ALL ABOUT PHASE NOISE -- 2-1 INTRODUCTION TO PHASE NOISE -- 2-1-1 The Clock Signal -- 2-1-2 The Power Spectral Density (PSD) -- 2-1-3 Basics of Noise -- 2-1-4 Phase and Frequency Noise -- 2-2 THE ALLAN VARIANCE AND OTHER TWO‐SAMPLE VARIANCES -- 2-2-1 Frequency Counters -- 2-2-2 The Two‐Sample Variances AVAR, MVAR, and PVAR -- 2-2-3 Conversion from Spectra to Two‐Sample Variances -- 2-3 PHASE NOISE IN COMPONENTS -- 2-3-1 Amplifiers -- 2-3-2 Frequency Dividers -- 2-3-3 Frequency Multipliers -- 2-3-4 Direct Digital Synthesizer (DDS) -- 2-3-5 Phase Detectors -- 2-3-6 Noise Contribution from Power Supplies -- 2-4 PHASE NOISE IN OSCILLATORS -- 2-4-1 Modern View of the Leeson Model -- 2-4-2 Circumventing the Resonator's Thermal Noise -- 2-4-3 Oscillator Hacking -- 2-5 THE MEASUREMENT OF PHASE NOISE -- 2-5-1 Double‐Balanced Mixer Instruments -- 2-5-2 The Cross‐Spectrum Method -- 2-5-3 Digital Instruments -- 2-5-4 Pitfalls and Limitations of the Cross‐Spectrum Measurements -- 2-5-5 The Bridge (Interferometric) Method.
2-5-6 Artifacts and Oddities Often Found in the Real World -- 2-5 References -- 2-5 SUGGESTED READINGS -- 2-5-6 Power spectra and Fourier transform -- 2-5-6 Electromagnetic Compatibility -- 2-5-6 General Aspects of Noise -- 2-5-6 Phase Noise, Frequency Stability, and Measurements -- 2-5-6 Amplifiers -- 2-5-6 Frequency Dividers -- 2-5-6 Frequency Multipliers -- 2-5-6 DDS -- 2-5-6 Phase‐Frequency Detectors -- 2-5-6 Oscillators -- 2-5-6 Resonators -- 2-5-6 Double‐Balanced Mixer -- Chapter 3 Special Loops -- 3-1 Introduction -- 3-2 Direct Digital Synthesis Techniques -- 3-2-1 A First Look at Fractional N -- 3-2-2 Digital Waveform Synthesizers -- 3-2-3 Signal Quality -- 3-2-4 Future Prospects -- 3-3 Loops with Delay Line as Phase Comparators -- 3-4 Fractional Division N Synthesizers -- 3-4-1 Example Implementation -- 3-4-2 Some Special Past Patents for Fractional Division N Synthesizers -- References -- Bibliography -- FRACTIONAL DIVISION N READINGS -- Chapter 4 LOOP COMPONENTS -- 4-1 INTRODUCTION TO OSCILLATORS AND THEIR MATHEMATICAL TREATMENT -- 4-2 THE COLPITTS OSCILLATOR -- 4-2-1 Linear Approach -- 4-2-2 Design Example for a 350 MHz Fixed‐Frequency Colpitts Oscillator -- 4-2-3 Validation Circuits -- 4-2-4 Series Feedback Oscillator [5, Appendix A, pp. 384-388] -- 4-2-5 2400 MHz MOSFET‐Based Push-Pull Oscillator -- 4-2-6 Oscillators for IC Applications -- 4-2-7 Noise in Semiconductors and Circuits -- 4-2-8 Summary -- 4-3 USE OF TUNING DIODES -- 4-3-1 Diode Tuned Resonant Circuits -- 4-3-2 Practical Circuits -- 4-4 USE OF DIODE SWITCHES -- 4-4-1 Diode Switches for Electronic Band Selection -- 4-4-2 Use of Diodes for Frequency Multiplication -- 4-5 REFERENCE FREQUENCY STANDARDS -- 4-5-1 Specifying Oscillators -- 4-5-2 Typical Examples of Crystal Oscillator Specifications -- 4-6 MIXER APPLICATIONS -- 4-7 PHASE/FREQUENCY COMPARATORS -- 4-7-1 Diode Rings.
4-7-2 Exclusive ORs -- 4-7-3 Sample/Hold Detectors -- 4-7-4 Edge‐Triggered JK Master/Slave Flip‐Flops -- 4-7-5 Digital Tri‐State Comparators -- 4-8 WIDEBAND HIGH‐GAIN AMPLIFIERS -- 4-8-1 Summation Amplifiers -- 4-8-2 Differential Limiters -- 4-8-3 Isolation Amplifiers -- 4-8-4 Example Implementations -- 4-9 PROGRAMMABLE DIVIDERS -- 4-9-1 Asynchronous Counters -- 4-9-2 Programmable Synchronous Up‐/Down‐Counters -- 4-9-3 Advanced Implementation Example -- 4-9-4 Swallow Counters/Dual‐Modulus Counters -- 4-9-5 Look‐Ahead and Delay Compensation -- 4-10 LOOP FILTERS -- 4-10-1 Passive RC Filters -- 4-10-2 Active RC Filters -- 4-10-3 Active Second‐Order Low‐Pass Filters -- 4-10-4 Passive LC Filters -- 4-10-5 Spur‐Suppression Techniques -- 4-11 MICROWAVE OSCILLATOR DESIGN -- 4-11-1 The Compressed Smith Chart -- 4-11-2 Series or Parallel Resonance -- 4-11-3 Two‐Port Oscillator Design -- 4-12 MICROWAVE RESONATORS -- 4-12-1 SAW Oscillators -- 4-12-2 Dielectric Resonators -- 4-12-3 YIG Oscillators -- 4-12-4 Varactor Resonators -- 4-12-5 Ceramic Resonators -- 4-12 REFERENCES -- 4-12 SUGGESTED READINGS -- 4-12-5 Section 4‐3 Documents -- 4-12-5 Section 4‐5 Documents -- 4-12-5 Section 4‐6 Documents -- 4-12-5 Section 4‐7 Documents -- 4-12-5 Section 4‐8 Documents -- 4-12-5 Section 4.9 Documents -- 4-12-5 Section 4.10 Documents -- 4-12-5 Section 4.11 Documents -- 4-12-5 Section 4.12 Documents -- Chapter 5 Digital PLL Synthesizers -- 5-1 Multiloop Synthesizers Using Different Techniques -- 5-1-1 Direct Frequency Synthesis -- 5-1-2 Multiple Loops -- 5-2 System Analysis -- 5-3 Low‐Noise Microwave Synthesizers -- 5-3-1 Building Blocks -- 5-3-2 Output Loop Response -- 5-3-3 Low Phase Noise References: Frequency Standards -- 5-3-4 Critical Stage -- 5-3-5 Time Domain Analysis -- 5-3-6 Summary -- 5-3-7 Two Commercial Synthesizer Examples.
5-4 Microprocessor Applications in Synthesizers -- 5-5 Transceiver Applications -- 5-6 About Bits, Symbols, and Waveforms -- 5-6-1 Representation of a Modulated RF Carrier -- 5-6-2 Generation of the Modulated Carrier -- 5-6-3 Putting It all Together -- 5-6-4 Combination of Techniques -- 5-6 Acknowledgments -- 5-6 References -- 5-6 Bibliography and Suggested Reading -- Chapter 6 A High‐Performance Hybrid Synthesizer -- 6-1 Introduction -- 6-2 Basic Synthesizer Approach -- 6-3 Loop Filter Design -- 6-4 Summary -- Bibliography -- Chapter A Mathematical Review -- A-1 FUNCTIONS OF A COMPLEX VARIABLE -- A-2 COMPLEX PLANES -- A-2-1 Functions in the Complex Frequency Plane -- A-3 BODE DIAGRAM -- A-4 LAPLACE TRANSFORM -- A-4-1 The Step Function -- A-4-2 The Ramp -- A-4-3 Linearity Theorem -- A-4-4 Differentiation and Integration -- A-4-5 Initial Value Theorem -- A-4-6 Final Value Theorem -- A-4-7 The Active Integrator -- A-4-8 Locking Behavior of the PLL -- A-5 LOW‐NOISE OSCILLATOR DESIGN -- A-5-1 Example Implementation -- A-6 OSCILLATOR AMPLITUDE STABILIZATION -- A-7 VERY LOW PHASE NOISE VCO FOR 800 MHZ -- REFERENCES -- Chapter B A General‐Purpose Nonlinear Approach to the Computation of Sideband Phase Noise in Free‐Running Microwave and RF Oscillators -- B-1 Introduction -- B-2 Noise Generation in Oscillators -- B-3 Bias‐Dependent Noise Model -- B-3-1 Bias‐Dependent Model -- B-3-2 Derivation of the Model -- B-4 General Concept of Noisy Circuits -- B-4-1 Noise from Linear Elements -- B-5 Noise Figure of Mixer Circuits -- B-6 Oscillator Noise Analysis -- B-7 Limitations of the Frequency‐Conversion Approach -- B-7-1 Assumptions -- B-7-2 Conversion and Modulation Noise -- B-7-3 Properties of Modulation Noise -- B-7-4 Noise Analysis of Autonomous Circuits -- B-7-5 Conversion Noise Analysis Results -- B-7-6 Modulation Noise Analysis Results.
B-8 Summary of the Phase Noise Spectrum of the Oscillator -- B-9 Verification Examples for the Calculation of Phase Noise in Oscillators Using Nonlinear Techniques -- B-9-1 Example 1: High‐Q Case Microstrip DRO -- B-9-2 Example 2: 10 MHz Crystal Oscillator -- B-9-3 Example 3: The 1‐GHz Ceramic Resonator VCO -- B-9-4 Example 4: Low Phase Noise FET Oscillator -- B-9-5 Example 5: Millimeter‐Wave Applications -- B-9-6 Example 6: Discriminator Stabilized DRO -- B-10 Summary -- B-10 References -- Chapter C EXAMPLE OF WIRELESS SYNTHESIZERS USING COMMERCIAL ICs -- Chapter D MMIC‐BASED SYNTHESIZERS -- D-1 INTRODUCTION -- BIBLIOGRAPHY -- Chapter E ARTICLES ON DESIGN OF DIELECTRIC RESONATOR OSCILLATORS -- E-1 THE DESIGN OF AN ULTRA‐LOW PHASE NOISE DRO -- E-1-1 Basic Considerations and Component Selection -- E-1-2 Component Selection -- E-1-3 DRO Topologies -- E-1-4 Small Signal Design Approach for the Parallel Feedback Type DRO -- E-1-5 Simulated Versus Measured Results -- E-1-6 Physical Embodiment -- E-1-7 Acknowledgments -- E-1-8 Final Remarks -- REFERENCES -- BIBLIOGRAPHY -- E-2 A NOVEL OSCILLATOR DESIGN WITH METAMATERIAL‐MÖBIUS COUPLING TO A DIELECTRIC RESONATOR -- E-2-1 Abstract -- E-2-2 Introduction -- REFERENCES -- Chapter F OPTO‐ELECTRONICALLY STABILIZED RF OSCILLATORS -- F-1 INTRODUCTION -- F-1-1 Oscillator Basics -- F-1-2 Resonator Technologies -- F-1-3 Motivation for OEO -- F-1-4 Operation Principle of the OEO -- F-2 EXPERIMENTAL EVALUATION AND THERMAL STABILITY OF OEO -- F-2-1 Experimental Setup -- F-2-2 Phase Noise Measurements -- F-2-3 Thermal Sensitivity Analysis of Standard Fibers -- F-2-4 Temperature Sensitivity Measurements -- F-2-5 Temperature Sensitivity Improvement with HC‐PCF -- F-2-6 Improve Thermal Stability Versus Phase Noise Degradation -- F-2-7 Passive Temperature Compensation -- F-2-8 Improving Effective Q with Raman Amplification.
F-3 FORCED OSCILLATION TECHNIQUES OF OEO.
Record Nr. UNINA-9910830471603321
Rohde Ulrich L.  
Hoboken, NJ : , : Wiley, , 2021
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Microwave and wireless synthesizers : theory and design / / Ulrich L. Rohde [[electronic resource]]
Microwave and wireless synthesizers : theory and design / / Ulrich L. Rohde [[electronic resource]]
Autore Rohde Ulrich L
Edizione [1st edition]
Pubbl/distr/stampa New York, : Wiley, c1997
Descrizione fisica 1 online resource (xvii, 638 p. ) : ill. ;
Disciplina 621.3815/486
Soggetto topico Frequency synthesizers - Design and construction
Phase-locked loops
Digital electronics
Microwave circuits - Design and construction
Radio frequency
Phase-locked loops - Design and construction
Microwave circuits
Electrical & Computer Engineering
Engineering & Applied Sciences
Electrical Engineering
ISBN 1-280-55642-0
9786610556427
0-470-35835-1
0-471-22431-6
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Loop fundamentals -- Noise and spurious response of loops -- Special loops -- Loop components -- Digital PLL synthesizers -- High-performance hybrid synthesizer.
Record Nr. UNINA-9910146248503321
Rohde Ulrich L  
New York, : Wiley, c1997
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Noise-shaping all-digital phase-locked loops : modeling, simulation, analysis and design / / Francesco Brandonisio, Michael Peter Kennedy
Noise-shaping all-digital phase-locked loops : modeling, simulation, analysis and design / / Francesco Brandonisio, Michael Peter Kennedy
Autore Brandonisio Francesco
Edizione [1st ed. 2014.]
Pubbl/distr/stampa Cham, Switzerland : , : Springer, , 2014
Descrizione fisica 1 online resource (xiii, 177 pages) : illustrations (some color)
Disciplina 621.3815364
Collana Analog Circuits and Signal Processing
Soggetto topico Phase-locked loops
Electronic digital computers - Circuits - Design and construction
ISBN 3-319-03659-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction -- Phase Digitization in All-Digital PLLs -- A Unifying Framework for TDC Architectures -- Analytical Predictions of Phase Noise in ADPLLs -- Advantages of Noise Shaping and Dither -- Efficient Modeling and Simulation of Accumulator-Based ADPLLs -- Modelling and Estimating Phase Noise with Matlab.
Record Nr. UNINA-9910299495603321
Brandonisio Francesco  
Cham, Switzerland : , : Springer, , 2014
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Phase lock loops and frequency synthesis [[electronic resource] /] / Věnceslav F. Kroupa
Phase lock loops and frequency synthesis [[electronic resource] /] / Věnceslav F. Kroupa
Autore Kroupa Věnceslav F. <1923->
Pubbl/distr/stampa New York, : J. Wiley, 2003
Descrizione fisica 1 online resource (336 p.)
Disciplina 621.3815/364
621.3815364
621.382
Soggetto topico Phase-locked loops
Frequency synthesizers
Soggetto genere / forma Electronic books.
ISBN 1-280-27201-5
9786610272013
0-470-29946-0
0-470-86512-1
0-470-01410-5
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Phase Lock Loops and Frequency Synthesis; Contents; Preface; 1 Basic Equations of the PLLs; 1.1 Introduction; 1.2 Basic Equations of the PLLs; 1.3 Solution of the Basic PLL Equation in the Time Domain; 1.3.1 Solution in the Closed Form; 1.3.2 Linearized Solution; 1.4 Solution of Basic PLL Equations in the Frequency Domain; 1.5 Order and Type of PLLs; 1.5.1 Order of PLLs; 1.5.2 Type of PLLs; 1.5.3 Steady State Errors; 1.6 Block Diagram Algebra; References; 2 PLLs of the First and Second Order; 2.1 PLLs of the First Order; 2.2 PLLs of the Second Order; 2.2.1 A Simple RC Filter
2.2.2 Phase Lag-lead RRC or RCC Filter2.3 PLLs of the Second Order of Type 2; 2.3.1 PLLs of the Second Order of Type 2 with Voltage Output PD; 2.3.2 PLLs of the Second Order of Type 2 with Current Output Phase Detector; 2.4 Second-order PLLs with Frequency Dividers in the Feedback Path; References; 3 PLLs of the Third and Higher Orders; 3.1 General Open-loop Transfer Function G(s); 3.1.1 Additional RC Section; 3.1.2 Two RC Sections; 3.1.3 Active Second-order Low-pass Filter; 3.1.4 Twin-T RC Filter; 3.1.5 PLLs with a Selective Filter in the Feedback Path; 3.1.6 Time Delays in PLLs
3.2 Higher-order Type 2 PLLs3.2.1 Third-order Loops: Lag-lead Filter with Additional RC Section; 3.2.2 Third-order Loop: Second-order Lag Filter Plus RC Section; 3.2.3 Fourth-order Loops; 3.2.4 Fifth-order Loops; 3.3 PLLs with Transmission Blocks in the Feedback Path; 3.3.1 Divider in the Feedback Path; 3.3.2 IF Filter in the Feedback Path; 3.3.3 IF Filter and Divider in the Feedback Path; 3.4 Sampled Higher-order Loops; 3.4.1 Third-order Loops with the Current Output Phase Detector; 3.5 Higher-order Loops of Type 3; 3.6 Computer Design of a Higher-order PLL; References
4 Stability of the PLL Systems4.1 Hurwitz Criterion of Stability; 4.2 Computation of the Roots of the Polynomial P(s); 4.3 Expansion of the Function 1/[1 + G(s)] into a Sum of Simple Fractions; 4.3.1 Polynomial S(s) Contains Simple Roots Only; 4.3.2 Polynomial S(s) Contains a Pair of Complex Roots; 4.3.3 Polynomial S(s) Contains Multiple-order Roots; 4.4 The Root-locus Method; 4.5 Frequency Analysis of the Transfer Functions - Bode Plots; 4.5.1 Bode Plots; 4.5.2 Polar Diagrams; 4.6 Nyquist Criterion of Stability; 4.7 The Effective Damping Factor; 4.8 Appendix; References; 5 Tracking
5.1 Transients in PLLs5.1.1 Transients in First-order PLLs; 5.1.2 Transients in Second-order PLLs; 5.1.3 Transients in Higher-order Loops; 5.2 Periodic Changes; 5.2.1 Phase Modulation of the Input Signal; 5.2.2 Frequency Modulation of the Input Signal; 5.3 Discrete Spurious Signals; 5.3.1 Small Discrete Spurious Signals at the Input; 5.3.2 Small Spurious Signals at the Output of the Phase Detector; 5.3.3 Small Spurious Signals at the Output of the PLLs; References; 6 Working Ranges of PLLs; 6.1 Hold-in Range; 6.1.1 Phase Detector with the Sine Wave Output; 6.1.2 The PD with Triangular Output
6.1.3 The PD with a Sawtooth Wave Output
Record Nr. UNINA-9910143229003321
Kroupa Věnceslav F. <1923->  
New York, : J. Wiley, 2003
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Phase lock loops and frequency synthesis [[electronic resource] /] / Věnceslav F. Kroupa
Phase lock loops and frequency synthesis [[electronic resource] /] / Věnceslav F. Kroupa
Autore Kroupa Věnceslav F. <1923->
Pubbl/distr/stampa New York, : J. Wiley, 2003
Descrizione fisica 1 online resource (336 p.)
Disciplina 621.3815/364
621.3815364
621.382
Soggetto topico Phase-locked loops
Frequency synthesizers
ISBN 1-280-27201-5
9786610272013
0-470-29946-0
0-470-86512-1
0-470-01410-5
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Phase Lock Loops and Frequency Synthesis; Contents; Preface; 1 Basic Equations of the PLLs; 1.1 Introduction; 1.2 Basic Equations of the PLLs; 1.3 Solution of the Basic PLL Equation in the Time Domain; 1.3.1 Solution in the Closed Form; 1.3.2 Linearized Solution; 1.4 Solution of Basic PLL Equations in the Frequency Domain; 1.5 Order and Type of PLLs; 1.5.1 Order of PLLs; 1.5.2 Type of PLLs; 1.5.3 Steady State Errors; 1.6 Block Diagram Algebra; References; 2 PLLs of the First and Second Order; 2.1 PLLs of the First Order; 2.2 PLLs of the Second Order; 2.2.1 A Simple RC Filter
2.2.2 Phase Lag-lead RRC or RCC Filter2.3 PLLs of the Second Order of Type 2; 2.3.1 PLLs of the Second Order of Type 2 with Voltage Output PD; 2.3.2 PLLs of the Second Order of Type 2 with Current Output Phase Detector; 2.4 Second-order PLLs with Frequency Dividers in the Feedback Path; References; 3 PLLs of the Third and Higher Orders; 3.1 General Open-loop Transfer Function G(s); 3.1.1 Additional RC Section; 3.1.2 Two RC Sections; 3.1.3 Active Second-order Low-pass Filter; 3.1.4 Twin-T RC Filter; 3.1.5 PLLs with a Selective Filter in the Feedback Path; 3.1.6 Time Delays in PLLs
3.2 Higher-order Type 2 PLLs3.2.1 Third-order Loops: Lag-lead Filter with Additional RC Section; 3.2.2 Third-order Loop: Second-order Lag Filter Plus RC Section; 3.2.3 Fourth-order Loops; 3.2.4 Fifth-order Loops; 3.3 PLLs with Transmission Blocks in the Feedback Path; 3.3.1 Divider in the Feedback Path; 3.3.2 IF Filter in the Feedback Path; 3.3.3 IF Filter and Divider in the Feedback Path; 3.4 Sampled Higher-order Loops; 3.4.1 Third-order Loops with the Current Output Phase Detector; 3.5 Higher-order Loops of Type 3; 3.6 Computer Design of a Higher-order PLL; References
4 Stability of the PLL Systems4.1 Hurwitz Criterion of Stability; 4.2 Computation of the Roots of the Polynomial P(s); 4.3 Expansion of the Function 1/[1 + G(s)] into a Sum of Simple Fractions; 4.3.1 Polynomial S(s) Contains Simple Roots Only; 4.3.2 Polynomial S(s) Contains a Pair of Complex Roots; 4.3.3 Polynomial S(s) Contains Multiple-order Roots; 4.4 The Root-locus Method; 4.5 Frequency Analysis of the Transfer Functions - Bode Plots; 4.5.1 Bode Plots; 4.5.2 Polar Diagrams; 4.6 Nyquist Criterion of Stability; 4.7 The Effective Damping Factor; 4.8 Appendix; References; 5 Tracking
5.1 Transients in PLLs5.1.1 Transients in First-order PLLs; 5.1.2 Transients in Second-order PLLs; 5.1.3 Transients in Higher-order Loops; 5.2 Periodic Changes; 5.2.1 Phase Modulation of the Input Signal; 5.2.2 Frequency Modulation of the Input Signal; 5.3 Discrete Spurious Signals; 5.3.1 Small Discrete Spurious Signals at the Input; 5.3.2 Small Spurious Signals at the Output of the Phase Detector; 5.3.3 Small Spurious Signals at the Output of the PLLs; References; 6 Working Ranges of PLLs; 6.1 Hold-in Range; 6.1.1 Phase Detector with the Sine Wave Output; 6.1.2 The PD with Triangular Output
6.1.3 The PD with a Sawtooth Wave Output
Record Nr. UNINA-9910829852303321
Kroupa Věnceslav F. <1923->  
New York, : J. Wiley, 2003
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