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Metamodeling-driven IP reuse for SoC integration and microprocessor design / / Deepak A. Mathaikutty, Sandeep K. Shukla
| Metamodeling-driven IP reuse for SoC integration and microprocessor design / / Deepak A. Mathaikutty, Sandeep K. Shukla |
| Autore | Mathaikutty Deepak A. |
| Pubbl/distr/stampa | Boston : , : Artech House, , ©2009 |
| Descrizione fisica | 1 online resource (310 p.) |
| Disciplina |
621.39
621.3916 |
| Altri autori (Persone) | ShuklaSandeep K |
| Soggetto topico |
Computer software - Reusability
Computer software - Verification Intellectual property Microprocessors - Design and construction System design Systems on a chip - Design and construction |
| Soggetto genere / forma | Electronic books. |
| ISBN | 1-59693-425-5 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Metamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design; Contents; Preface; References; Acknowledgments; Chapter 1 Introduction; Design IP; Verification IP; Design Reuse; Verification Reuse; 1.1 ONGOING EFFORTS IN DESIGN IP REUSE; 1.2 ONGOING EFFORTS IN VERIFICATION IP REUSE; 1.3 ESSENTIAL ISSUES WITH IP REUSE; Essential Issues with Design IP Reuse; (1) IP Provider; IP Library; Documentation; Quality Assurance; Standardization; (2) IP Integrator; Exploration; Integration; Methodology and Environment; (3) Tool Developer for IP Reuse; Support for IP Provider
Support for IP IntegratorEssential Issues with Verification IP Reuse; (1) Modeling Language; (2) Generation Algorithms; 1.4 METAMODELING APPROACH TO REUSE; 1.5 PROBLEM STATEMENT; 1.6 RESEARCH CONTRIBUTIONS; 1.7 TOOLS AND TECHNIQUES DEVELOPED; References; Chapter 2 Background; 2.1 METAMODELING; 2.1.1 Implicit Metamodeling Versus Explicit Metamodeling; 2.1.2 Generic Modeling Environment; 2.2 COMPONENT COMPOSITION FRAMEWORK; 2.3 REFLECTION AND INTROSPECTION (R-I); 2.4 SYSTEMC; 2.5 MODEL-DRIVEN VALIDATION; 2.5.1 Microprocessor Validation Flow; 2.5.2 Simulation-Based Functional Validation 2.6 TEST GENERATION2.6.1 Constraint Programming; 2.6.2 Esterel Studio; 2.7 COVERAGE-DIRECTED TEST GENERATION; 2.7.1 Structural Coverage; 2.7.2 Functional Coverage; 2.7.3 Property Specification Language (PSL); 2.7.4 Fault Classification; References; Chapter 3 Related Work; 3.1 COMPONENT COMPOSITION FRAMEWORK; 3.1.1 The BALBOA Framework; 3.1.2 Liberty Simulation Environment (LSE); 3.1.3 EWD; 3.1.4 Ptolemy II; 3.1.5 Metropolis; 3.2 COMPONENT-BASED SOFTWARE DESIGN ENVIRONMENTS; 3.3 IP INTERFACING STANDARDS; 3.3.1 SPIRIT; 3.4 EXISTING TOOLS FOR STRUCTURAL REFLECTION 3.5 ARCHITECTURE DESCRIPTION LANGUAGES3.6 TEST GENERATION; References; Part I Design Reuse; Chapter 4 A Metamodel for Component Composition; 4.1 CC LANGUAGE, METAMODEL, AND MODEL; 4.1.1 Component Composition Language (CCL); 4.1.2 Component Composition Metamodel (CCMM); 4.1.3 Component Composition Model (CCM); 4.2 CC ANALYSIS AND TRANSLATION; 4.2.1 Consistency Checking; 4.2.2 Type Inference; 4.2.3 XML Translation; 4.3 CASE STUDIES; 4.3.1 AMBA AHB RTL Bus Model; 4.3.2 Simple Bus TL Model; 4.4 DESIGN EXPERIENCE AND SUMMARY; References; Chapter 5 IP Reflection and Selection 5.1 METADATA FOR IP COMPOSITION5.2 METADATA ON A SYSTEMC IP SPECIFICATION; 5.3 TOOLS AND METHODOLOGY; 5.3.1 Stage 1: SystemC Parsing; 5.3.2 Stage 2: AST Parsing and DOM Population; 5.3.3 Stage 3: Processing and Constraining DOM; 5.4 IP SELECTION; 5.4.1 Illustrative Example; 5.5 CASE STUDY; 5.6 SUMMARY; References; Chapter 6 Typing Problems in IP Composition; 6.1 MCF TYPE DEFINITIONS; 6.1.1 Component Composition Language; 6.1.2 IP Library; 6.2 TYPE RESOLUTION IN MCF; 6.2.1 Type Inference on Architectural Template; 6.2.2 Type Substitution Using IP Library; 6.3 COMPARATIVE STUDY; 6.4 CASE STUDY 6.5 SUMMARY |
| Record Nr. | UNINA-9910456628003321 |
Mathaikutty Deepak A.
|
||
| Boston : , : Artech House, , ©2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Metamodeling-driven IP reuse for SoC integration and microprocessor design / / Deepak A. Mathaikutty, Sandeep K. Shukla
| Metamodeling-driven IP reuse for SoC integration and microprocessor design / / Deepak A. Mathaikutty, Sandeep K. Shukla |
| Autore | Mathaikutty Deepak A. |
| Pubbl/distr/stampa | Boston : , : Artech House, , ©2009 |
| Descrizione fisica | 1 online resource (310 p.) |
| Disciplina |
621.39
621.3916 |
| Altri autori (Persone) | ShuklaSandeep K |
| Soggetto topico |
Computer software - Reusability
Computer software - Verification Intellectual property Microprocessors - Design and construction System design Systems on a chip - Design and construction |
| ISBN | 1-59693-425-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Metamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design; Contents; Preface; References; Acknowledgments; Chapter 1 Introduction; Design IP; Verification IP; Design Reuse; Verification Reuse; 1.1 ONGOING EFFORTS IN DESIGN IP REUSE; 1.2 ONGOING EFFORTS IN VERIFICATION IP REUSE; 1.3 ESSENTIAL ISSUES WITH IP REUSE; Essential Issues with Design IP Reuse; (1) IP Provider; IP Library; Documentation; Quality Assurance; Standardization; (2) IP Integrator; Exploration; Integration; Methodology and Environment; (3) Tool Developer for IP Reuse; Support for IP Provider
Support for IP IntegratorEssential Issues with Verification IP Reuse; (1) Modeling Language; (2) Generation Algorithms; 1.4 METAMODELING APPROACH TO REUSE; 1.5 PROBLEM STATEMENT; 1.6 RESEARCH CONTRIBUTIONS; 1.7 TOOLS AND TECHNIQUES DEVELOPED; References; Chapter 2 Background; 2.1 METAMODELING; 2.1.1 Implicit Metamodeling Versus Explicit Metamodeling; 2.1.2 Generic Modeling Environment; 2.2 COMPONENT COMPOSITION FRAMEWORK; 2.3 REFLECTION AND INTROSPECTION (R-I); 2.4 SYSTEMC; 2.5 MODEL-DRIVEN VALIDATION; 2.5.1 Microprocessor Validation Flow; 2.5.2 Simulation-Based Functional Validation 2.6 TEST GENERATION2.6.1 Constraint Programming; 2.6.2 Esterel Studio; 2.7 COVERAGE-DIRECTED TEST GENERATION; 2.7.1 Structural Coverage; 2.7.2 Functional Coverage; 2.7.3 Property Specification Language (PSL); 2.7.4 Fault Classification; References; Chapter 3 Related Work; 3.1 COMPONENT COMPOSITION FRAMEWORK; 3.1.1 The BALBOA Framework; 3.1.2 Liberty Simulation Environment (LSE); 3.1.3 EWD; 3.1.4 Ptolemy II; 3.1.5 Metropolis; 3.2 COMPONENT-BASED SOFTWARE DESIGN ENVIRONMENTS; 3.3 IP INTERFACING STANDARDS; 3.3.1 SPIRIT; 3.4 EXISTING TOOLS FOR STRUCTURAL REFLECTION 3.5 ARCHITECTURE DESCRIPTION LANGUAGES3.6 TEST GENERATION; References; Part I Design Reuse; Chapter 4 A Metamodel for Component Composition; 4.1 CC LANGUAGE, METAMODEL, AND MODEL; 4.1.1 Component Composition Language (CCL); 4.1.2 Component Composition Metamodel (CCMM); 4.1.3 Component Composition Model (CCM); 4.2 CC ANALYSIS AND TRANSLATION; 4.2.1 Consistency Checking; 4.2.2 Type Inference; 4.2.3 XML Translation; 4.3 CASE STUDIES; 4.3.1 AMBA AHB RTL Bus Model; 4.3.2 Simple Bus TL Model; 4.4 DESIGN EXPERIENCE AND SUMMARY; References; Chapter 5 IP Reflection and Selection 5.1 METADATA FOR IP COMPOSITION5.2 METADATA ON A SYSTEMC IP SPECIFICATION; 5.3 TOOLS AND METHODOLOGY; 5.3.1 Stage 1: SystemC Parsing; 5.3.2 Stage 2: AST Parsing and DOM Population; 5.3.3 Stage 3: Processing and Constraining DOM; 5.4 IP SELECTION; 5.4.1 Illustrative Example; 5.5 CASE STUDY; 5.6 SUMMARY; References; Chapter 6 Typing Problems in IP Composition; 6.1 MCF TYPE DEFINITIONS; 6.1.1 Component Composition Language; 6.1.2 IP Library; 6.2 TYPE RESOLUTION IN MCF; 6.2.1 Type Inference on Architectural Template; 6.2.2 Type Substitution Using IP Library; 6.3 COMPARATIVE STUDY; 6.4 CASE STUDY 6.5 SUMMARY |
| Record Nr. | UNINA-9910780935303321 |
|
Mathaikutty Deepak A.
|
||
| Boston : , : Artech House, , ©2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Metamodeling-driven IP reuse for SoC integration and microprocessor design / / Deepak A. Mathaikutty, Sandeep K. Shukla
| Metamodeling-driven IP reuse for SoC integration and microprocessor design / / Deepak A. Mathaikutty, Sandeep K. Shukla |
| Autore | Mathaikutty Deepak A. |
| Pubbl/distr/stampa | Boston : , : Artech House, , ©2009 |
| Descrizione fisica | 1 online resource (310 p.) |
| Disciplina |
621.39
621.3916 |
| Altri autori (Persone) | ShuklaSandeep K |
| Soggetto topico |
Computer software - Reusability
Computer software - Verification Intellectual property Microprocessors - Design and construction System design Systems on a chip - Design and construction |
| ISBN | 1-59693-425-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Metamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design; Contents; Preface; References; Acknowledgments; Chapter 1 Introduction; Design IP; Verification IP; Design Reuse; Verification Reuse; 1.1 ONGOING EFFORTS IN DESIGN IP REUSE; 1.2 ONGOING EFFORTS IN VERIFICATION IP REUSE; 1.3 ESSENTIAL ISSUES WITH IP REUSE; Essential Issues with Design IP Reuse; (1) IP Provider; IP Library; Documentation; Quality Assurance; Standardization; (2) IP Integrator; Exploration; Integration; Methodology and Environment; (3) Tool Developer for IP Reuse; Support for IP Provider
Support for IP IntegratorEssential Issues with Verification IP Reuse; (1) Modeling Language; (2) Generation Algorithms; 1.4 METAMODELING APPROACH TO REUSE; 1.5 PROBLEM STATEMENT; 1.6 RESEARCH CONTRIBUTIONS; 1.7 TOOLS AND TECHNIQUES DEVELOPED; References; Chapter 2 Background; 2.1 METAMODELING; 2.1.1 Implicit Metamodeling Versus Explicit Metamodeling; 2.1.2 Generic Modeling Environment; 2.2 COMPONENT COMPOSITION FRAMEWORK; 2.3 REFLECTION AND INTROSPECTION (R-I); 2.4 SYSTEMC; 2.5 MODEL-DRIVEN VALIDATION; 2.5.1 Microprocessor Validation Flow; 2.5.2 Simulation-Based Functional Validation 2.6 TEST GENERATION2.6.1 Constraint Programming; 2.6.2 Esterel Studio; 2.7 COVERAGE-DIRECTED TEST GENERATION; 2.7.1 Structural Coverage; 2.7.2 Functional Coverage; 2.7.3 Property Specification Language (PSL); 2.7.4 Fault Classification; References; Chapter 3 Related Work; 3.1 COMPONENT COMPOSITION FRAMEWORK; 3.1.1 The BALBOA Framework; 3.1.2 Liberty Simulation Environment (LSE); 3.1.3 EWD; 3.1.4 Ptolemy II; 3.1.5 Metropolis; 3.2 COMPONENT-BASED SOFTWARE DESIGN ENVIRONMENTS; 3.3 IP INTERFACING STANDARDS; 3.3.1 SPIRIT; 3.4 EXISTING TOOLS FOR STRUCTURAL REFLECTION 3.5 ARCHITECTURE DESCRIPTION LANGUAGES3.6 TEST GENERATION; References; Part I Design Reuse; Chapter 4 A Metamodel for Component Composition; 4.1 CC LANGUAGE, METAMODEL, AND MODEL; 4.1.1 Component Composition Language (CCL); 4.1.2 Component Composition Metamodel (CCMM); 4.1.3 Component Composition Model (CCM); 4.2 CC ANALYSIS AND TRANSLATION; 4.2.1 Consistency Checking; 4.2.2 Type Inference; 4.2.3 XML Translation; 4.3 CASE STUDIES; 4.3.1 AMBA AHB RTL Bus Model; 4.3.2 Simple Bus TL Model; 4.4 DESIGN EXPERIENCE AND SUMMARY; References; Chapter 5 IP Reflection and Selection 5.1 METADATA FOR IP COMPOSITION5.2 METADATA ON A SYSTEMC IP SPECIFICATION; 5.3 TOOLS AND METHODOLOGY; 5.3.1 Stage 1: SystemC Parsing; 5.3.2 Stage 2: AST Parsing and DOM Population; 5.3.3 Stage 3: Processing and Constraining DOM; 5.4 IP SELECTION; 5.4.1 Illustrative Example; 5.5 CASE STUDY; 5.6 SUMMARY; References; Chapter 6 Typing Problems in IP Composition; 6.1 MCF TYPE DEFINITIONS; 6.1.1 Component Composition Language; 6.1.2 IP Library; 6.2 TYPE RESOLUTION IN MCF; 6.2.1 Type Inference on Architectural Template; 6.2.2 Type Substitution Using IP Library; 6.3 COMPARATIVE STUDY; 6.4 CASE STUDY 6.5 SUMMARY |
| Record Nr. | UNINA-9910825013703321 |
|
Mathaikutty Deepak A.
|
||
| Boston : , : Artech House, , ©2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Microprocessor . 1 Prolegomena - calculation and storage functions - models of computation and computer architecture / / Philippe Darche
| Microprocessor . 1 Prolegomena - calculation and storage functions - models of computation and computer architecture / / Philippe Darche |
| Autore | Darche Philippe |
| Pubbl/distr/stampa | London, England ; ; Hoboken, New Jersey : , : ISTE : , : Wiley, , [2020] |
| Descrizione fisica | 1 online resource (218 pages) |
| Disciplina | 621.3916 |
| Collana | Computer engineering series |
| Soggetto topico | Microprocessors - Design and construction |
| ISBN |
1-119-77966-9
1-119-77965-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910555129803321 |
|
Darche Philippe
|
||
| London, England ; ; Hoboken, New Jersey : , : ISTE : , : Wiley, , [2020] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Microprocessor . 1 Prolegomena - calculation and storage functions - models of computation and computer architecture / / Philippe Darche
| Microprocessor . 1 Prolegomena - calculation and storage functions - models of computation and computer architecture / / Philippe Darche |
| Autore | Darche Philippe |
| Pubbl/distr/stampa | London, England ; ; Hoboken, New Jersey : , : ISTE : , : Wiley, , [2020] |
| Descrizione fisica | 1 online resource (218 pages) |
| Disciplina | 621.3916 |
| Collana | Computer engineering series |
| Soggetto topico | Microprocessors - Design and construction |
| ISBN |
1-119-77966-9
1-119-77965-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910830069603321 |
|
Darche Philippe
|
||
| London, England ; ; Hoboken, New Jersey : , : ISTE : , : Wiley, , [2020] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Proceedings of 5th International Workshop on Hardware/Software Co Design : 24-26 March 1997, Braunschweig, Germany / / IEEE Computer Society
| Proceedings of 5th International Workshop on Hardware/Software Co Design : 24-26 March 1997, Braunschweig, Germany / / IEEE Computer Society |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 1997 |
| Descrizione fisica | 1 online resource (157 pages) |
| Disciplina | 621.3916 |
| Soggetto topico |
Computer-aided design - Equipment and supplies
Microprocessors - Design and construction Integrated circuits - Very large scale integration - Design and construction - Data processing |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996204383403316 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 1997 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Proceedings of 5th International Workshop on Hardware/Software Co Design : 24-26 March 1997, Braunschweig, Germany / / IEEE Computer Society
| Proceedings of 5th International Workshop on Hardware/Software Co Design : 24-26 March 1997, Braunschweig, Germany / / IEEE Computer Society |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 1997 |
| Descrizione fisica | 1 online resource (157 pages) |
| Disciplina | 621.3916 |
| Soggetto topico |
Computer-aided design - Equipment and supplies
Microprocessors - Design and construction Integrated circuits - Very large scale integration - Design and construction - Data processing |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910146682603321 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 1997 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
