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Low power VLSI design : fundamentals / / Angsuman Sarkar [and three others]
Low power VLSI design : fundamentals / / Angsuman Sarkar [and three others]
Autore Sarkar Angsuman
Pubbl/distr/stampa Berlin, [Germany] ; ; Boston, [Massachusetts] : , : De Gruyter Oldenbourg, , 2016
Descrizione fisica 1 online resource (xiv, 310 pages) : illustrations
Disciplina 621.39/5
Soggetto topico Integrated circuits - Very large scale integration
Low voltage integrated circuits
ISBN 3-11-045545-5
3-11-045529-3
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Frontmatter -- Preface -- Contents -- 1. Introduction to Low Power Issues in VLSI -- 2. Scaling and Short Channel Effects in MOSFET -- 3. Advanced Energy-reduced CMOS Inverter Design -- 4. Advanced Combinational Circuit Design -- 5. Advanced Energy-reduced Sequential Circuit Design -- 6. Introduction to Memory Design -- 7. Analog Low Power VLSI Circuit Design -- Index
Record Nr. UNINA-9910826862003321
Sarkar Angsuman  
Berlin, [Germany] ; ; Boston, [Massachusetts] : , : De Gruyter Oldenbourg, , 2016
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Low-voltage SOI CMOS VLSI devices and circuits / / James B. Kuo, Shih-Chia Lin
Low-voltage SOI CMOS VLSI devices and circuits / / James B. Kuo, Shih-Chia Lin
Autore Kuo James B. <1956->
Edizione [1st edition]
Pubbl/distr/stampa New York, : Wiley, c2001
Descrizione fisica 1 online resource (424 p.)
Disciplina 621.39
621.39/5
621.395
Altri autori (Persone) LinShih-Chia
Soggetto topico Low voltage integrated circuits
Integrated circuits - Very large scale integration
Metal oxide semiconductors, Complementary
ISBN 1-280-26478-0
9786610264780
0-470-32128-8
0-471-46417-1
0-471-22156-2
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Contents; Preface; Acknowledgments; 1 Introduction; 1.1 Evolution of CMOS VLSI; 1.2 SOI versus Bulk; 1.3 Low-Voltage SOI VLSI; 1.4 Objectives; References; 2 SOI CMOS Devices-Part I; 2.1 Basic SOI Technology; 2.1.1 SOI Wafers; 2.1.2 Shallow Trench Isolation; 2.1.3 SOI Device Structure; 2.2 Back Gate Bias Effects; 2.2.1 PD versus FD; 2.2.2 Inversion versus Accumulation; 2.3 Short Channel Effects; 2.3.1 Biasing Dependence; 2.3.2 Structure Dependence; 2.3.3 Processing Dependence; 2.3.4 Subthreshold; 2.4 Narrow Channel Effects; 2.4.1 Structure Dependence; 2.4.2 Subthreshold
2.4.3 Back Gate Bias Dependence2.4.4 Isolation Dependence; 2.5 Mobility; 2.5.1 Vertical Field Dependence; 2.5.2 Lateral Field Dependence; 2.6 Floating Body Effects; 2.6.1 Strong Inversion Kink Effects; 2.6.2 Body Contact; 2.6.3 Various Techniques to Reduce Kink Effects; 2.7 Subthreshold Behavior; 2.7.1 FD versus PD; 2.7.2 PD; 2.7.3 DIBL Dependence; 2.7.4 Latch/GIDL Behavior; 2.8 Impact lonization; 2.8.1 Basic Analysis; 2.8.2 Body Current; 2.8.3 Monitoring Techniques; 2.9 Breakdown; 2.9.1 Structure Dependence; 2.9.2 Bipolar Induced Effects; 2.9.3 LDD; 2.10 Transient-Induced Leakage
2.11 History Effects2.12 Self-Heating; 2.12.1 Drain Current; 2.12.2 Thermal Resistance; 2.12.3 Thermal Coupling; 2.12.4 AC Behavior; 2.13 Transient Behaviors; 2.13.1 Floating-Body Induced; 2.13.2 History Effect; 2.14 Summary; References; Problems; 3 SOI CMOS Devices-Part II; 3.1 Hot Carriers; 3.1.1 NMOS; 3.1.2 PMOS; 3.1.3 Substrate Current; 3.1.4 Back Gate Bias; 3.1.5 Device Structure Dependence; 3.1.6 Stress Time; 3.1.7 Isolation Structure; 3.1.8 SOI Wafers; 3.1.9 Lifetime; 3.2 Accumulation-Mode Devices; 3.2.1 DC Behavior; 3.2.2 AC Behavior; 3.2.3 Thin-Film Thickness
3.2.4 Accumulation versus Inversion3.3 Double Gate; 3.4 DTMOS; 3.4.1 Basic Performance; 3.4.2 Second-Order Effects; 3.5 Scaling Trends; 3.6 Single Electron Transistors (SET); 3.7 Electrostatic Discharge (ESD); 3.8 Temperature Dependence; 3.8.1 Noise; 3.9 Sensitivity; 3.10 Radiation Effects; 3.11 Summary; References; Problems; 4 Fundamentals of SOI CMOS Circuits; 4.1 Basic Circuit Issues; 4.1.1 Layout; 4.1.2 High Speed and Low Power; 4.1.3 Floating Body; 4.1.4 Self-Heating; 4.2 Floating Body Effects; 4.2.1 Static Logic Circuits; 4.2.2 Pass Gate Transistors; 4.2.3 Switch Network Logic (SNL)
4.2.4 Hysteresis4.2.5 Analog Circuits; 4.3 Low-Voltage Circuit Techniques; 4.3.1 Low-Voltage Technology; 4.3.2 Dynamic Body Control; 4.3.3 Sense Amp; 4.4 DTMOS Circuits; 4.4.1 DTMOS Device; 4.4.2 DTMOS Inverter; 4.4.3 DTMOS Buffer; 4.4.4 Advanced DTMOS Devices; 4.4.5 Active Body Control; 4.5 MTCMOS Circuits; 4.6 Noise; 4.7 Self-Heating; 4.8 ESD Circuits; 4.9 System-on-a Chip (SOC) Technology; 4.10 Summary; References; Problems; 5 SOI CMOS Digital Circuits; 5.1 Static Logic Circuits; 5.1.1 SOI CPL; 5.1.2 DTPT; 5.1.3 SOI CVSL; 5.1.4 SOI Adiabatic CVSL; 5.2 Dynamic Logic Circuits
5.2.1 SOI DTMOS Dynamic Logic Circuit
Record Nr. UNINA-9910143174803321
Kuo James B. <1956->  
New York, : Wiley, c2001
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
MOS devices for low-voltage and low-energy applications / / Yasuhisa Omura, Abhijit Mallik, and Naoto Matsuo
MOS devices for low-voltage and low-energy applications / / Yasuhisa Omura, Abhijit Mallik, and Naoto Matsuo
Autore Omura Y (Yasuhisa)
Pubbl/distr/stampa Singapore ; ; Hoboken, NJ : , : John Wiley & Sons, , 2017
Descrizione fisica 1 online resource (758 pages) : illustrations, tables, graphs
Disciplina 621.3815/284
Soggetto topico Metal oxide semiconductors
Metal oxide semiconductor field-effect transistors
Low voltage integrated circuits
Low voltage systems - Industrial applications
ISBN 1-5231-1527-0
1-119-10738-5
1-119-10736-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Preface XV -- Acknowledgments Xvi -- Part I Introduction To Low Voltage And Low Energy Devices 1 -- 1 Why Are Low Voltage And Low Energy Devices Desired? 3 -- References 4 -- 2 History Of Low Voltage And Low Power Devices 5 -- 2.1 Scaling Scheme And Low Voltage Requests 5 -- 2.2 Silicon On Insulator Devices And Real History 8 -- References 10 -- 3 Performance Prospects Of Subthreshold Logic Circuits 12 -- 3.1 Introduction 12 -- 3.2 Subthreshold Logic And Its Issues 12 -- 3.3 Is Subthreshold Logic The Best Solution? 13 -- References 13 -- Part Ii Summary Of Physics Of Modern Semiconductor Devices 15 -- 4 Overview 17 -- References 18 -- 5 Bulk Mosfet 19 -- 5.1 Theoretical Basis Of Bulk Mosfet Operation 19 -- 5.2 Subthreshold Characteristics: "Boff State" 19 -- 5.2.1 Fundamental Theory 19 -- 5.2.2 Influence Of Btbt Current 23 -- 5.2.3 Points To Be Remarked 24 -- 5.3 Post Threshold Characteristics: "Bon State" 24 -- 5.3.1 Fundamental Theory 24 -- 5.3.2 Self Heating Effects 26 -- 5.3.3 Parasitic Bipolar Effects 27 -- 5.4 Comprehensive Summary Of Short Channel Effects 27 -- References 28 -- 6 Soi Mosfet 29 -- 6.1 Partially Depleted Silicon On Insulator Metal Oxide Semiconductor Field Effect Transistors 29 -- 6.2 Fully Depleted (Fd) Soi Mosfet 30 -- 6.2.1 Subthreshold Characteristics 30 -- 6.2.2 Post Threshold Characteristics 36 -- 6.2.3 Comprehensive Summary Of Short Channel Effects 41 -- 6.3 Accumulation Mode (Am) Soi Mosfet 41 -- 6.3.1 Aspects Of Device Structure 41 -- 6.3.2 Subthreshold Characteristics 42 -- 6.3.3 Drain Current Component (I) Body Current (Id,Body) 43 -- 6.3.4 Drain Current Component (Ii) Surface Accumulation -- Layer Current (Id,Acc) 45 -- 6.3.5 Optional Discussions On The Accumulation Mode Soi Mosfet 45 -- 6.4 Finfet And Triple Gate Fet 46 -- 6.4.1 Introduction 46 -- 6.4.2 Device Structures And Simulations 46 -- 6.4.3 Results And Discussion 47 -- 6.4.4 Summary 49 -- 6.5 Gate All Around Mosfet 50 -- References 51 -- 7 Tunnel Field Effect Transistors (Tfets) 53.
7.1 Overview 53 -- 7.2 Model of Double‐Gate Lateral Tunnel FET and Device Performance Perspective 53 -- 7.2.1 Introduction 53 -- 7.2.2 Device Modeling 54 -- 7.2.3 Numerical Calculation Results and Discussion 61 -- 7.2.4 Summary 65 -- 7.3 Model of Vertical Tunnel FET and Aspects of its Characteristics 65 -- 7.3.1 Introduction 65 -- 7.3.2 Device Structure and Model Concept 65 -- 7.3.3 Comparing Model Results with TCAD Results 69 -- 7.3.4 Consideration of the Impact of Tunnel Dimensionality on Drivability 72 -- 7.3.5 Summary 75 -- 7.4 Appendix Integration of Eqs. (7.14) / (7.16) 76 -- References 78 -- Part III POTENTIAL OF CONVENTIONAL BULK MOSFETs 81 -- 8 Performance Evaluation of Analog Circuits with Deep Submicrometer MOSFETs in the Subthreshold Regime of Operation 83 -- 8.1 Introduction 83 -- 8.2 Subthreshold Operation and Device Simulation 84 -- 8.3 Model Description 85 -- 8.4 Results 86 -- 8.5 Summary 90 -- References 90 -- 9 Impact of Halo Doping on the Subthreshold Performance of Deep‐Submicrometer CMOS Devices and Circuits for Ultralow Power Analog/Mixed‐Signal Applications 91 -- 9.1 Introduction 91 -- 9.2 Device Structures and Simulation 92 -- 9.3 Subthreshold Operation 93 -- 9.4 Device Optimization for Subthreshold Analog Operation 95 -- 9.5 Subthreshold Analog Circuit Performance 98 -- 9.6 CMOS Amplifiers with Large Geometry Devices 105 -- 9.7 Summary 106 -- References 107 -- 10 Study of the Subthreshold Performance and the Effect of Channel Engineering on Deep Submicron Single‐Stage CMOS Amplifiers 108 -- 10.1 Introduction 108 -- 10.2 Circuit Description 108 -- 10.3 Device Structure and Simulation 110 -- 10.4 Results and Discussion 110 -- 10.5 PTAT as a Temperature Sensor 116 -- 10.6 Summary 116 -- References 116 -- 11 Subthreshold Performance of Dual‐Material Gate CMOS Devices and Circuits for Ultralow Power Analog/Mixed‐Signal Applications 117 -- 11.1 Introduction 117 -- 11.2 Device Structure and Simulation 118 -- 11.3 Results and Discussion 120 -- 11.4 Summary 126.
References 127 -- 12 Performance Prospect of Low‐Power Bulk MOSFETs 128 -- Reference 129 -- Part IV POTENTIAL OF FULLY‐DEPLETED SOI MOSFETs 131 -- 13 Demand for High‐Performance SOI Devices 133 -- 14 Demonstration of 100 nm Gate SOI CMOS with a Thin Buried Oxide Layer and its Impact on Device Technology 134 -- 14.1 Introduction 134 -- 14.2 Device Design Concept for 100 nm Gate SOI CMOS 134 -- 14.3 Device Fabrication 136 -- 14.4 Performance of 100‐nm‐ and 85‐nm Gate Devices 137 -- 14.4.1 Threshold and Subthreshold Characteristics 137 -- 14.4.2 Drain Current (ID)‐Drain Voltage (VD) and ID‐Gate Voltage (VG) Characteristics of 100‐nm‐Gate MOSFET/SIMOX 138 -- 14.4.3 ID / VD and ID / VG Characteristics of 85‐nm‐Gate MOSFET/SIMOX 142 -- 14.4.4 Switching Performance 142 -- 14.5 Discussion 142 -- 14.5.1 Threshold Voltage Balance in Ultrathin CMOS/SOI Devices 142 -- 14.6 Summary 144 -- References 145 -- 15 Discussion on Design Feasibility and Prospect of High‐Performance Sub‐50 nm Channel Single‐Gate SOI MOSFET Based on the ITRS Roadmap 147 -- 15.1 Introduction 147 -- 15.2 Device Structure and Simulations 148 -- 15.3 Proposed Model for Minimum Channel Length 149 -- 15.3.1 Minimum Channel Length Model Constructed using Extract A 149 -- 15.3.2 Minimum Channel Length Model Constructed using Extract B 150 -- 15.4 Performance Prospects of Scaled SOI MOSFETs 152 -- 15.4.1 Dynamic Operation Characteristics of Scaled SG SOI MOSFETs 152 -- 15.4.2 Tradeoff and Optimization of Standby Power Consumption and Dynamic Operation 157 -- 15.5 Summary 162 -- References 162 -- 16 Performance Prospects of Fully Depleted SOI MOSFET‐Based Diodes Applied to Schenkel Circuits for RF‐ID Chips 164 -- 16.1 Introduction 164 -- 16.2 Remaining Issues with Conventional Schenkel Circuits and an Advanced Proposal 165 -- 16.3 Simulation‐Based Consideration of RF Performance of SOI‐QD 172 -- 16.4 Summary 176 -- 16.5 Appendix: A Simulation Model for Minority Carrier Lifetime 177 -- 16.6 Appendix: Design Guideline for SOI‐QDs 177.
References 178 -- 17 The Potential and the Drawbacks of Underlap Single‐Gate Ultrathin SOI MOSFET 180 -- 17.1 Introduction 180 -- 17.2 Simulations 181 -- 17.3 Results and Discussion 183 -- 17.3.1 DC Characteristics and Switching Performance: Device A 183 -- 17.3.2 RF Analog Characteristics: Device A 184 -- 17.3.3 Impact of High‐κ Gate Dielectric on Performance of USU SOI MOSFET Devices: Devices B and C 185 -- 17.3.4 Impact of Simulation Model on Simulation Results 189 -- 17.4 Summary 192 -- References 192 -- 18 Practical Source/Drain Diffusion and Body Doping Layouts for High‐Performance and Low‐Energy Triple‐Gate SOI MOSFETs 194 -- 18.1 Introduction 194 -- 18.2 Device Structures and Simulation Model 195 -- 18.3 Results and Discussion 196 -- 18.3.1 Impact of S/D‐Underlying Layer on ION, IOFF, and Subthreshold Swing 196 -- 18.3.2 Tradeoff of Short‐Channel Effects and Drivability 196 -- 18.4 Summary 201 -- References 201 -- 19 Gate Field Engineering and Source/Drain Diffusion Engineering for High‐Performance Si Wire Gate‐All‐Around MOSFET and Low‐Power Strategy in a Sub‐30 nm‐Channel Regime 203 -- 19.1 Introduction 203 -- 19.2 Device Structures Assumed and Physical Parameters 204 -- 19.3 Simulation Results and Discussion 206 -- 19.3.1 Performance of Sub‐30 nm‐Channel Devices and Aspects of Device Characteristics 206 -- 19.3.2 Impact of Cross‐Section of Si Wire on Short‐Channel Effects and Drivability 212 -- 19.3.3 Minimizing Standby Power Consumption of GAA SOI MOSFET 216 -- 19.3.4 Prospective Switching Speed Performance of GAA SOI MOSFET 217 -- 19.3.5 Parasitic Resistance Issues of GAA Wire MOSFETs 218 -- 19.3.6 Proposal for Possible GAA Wire MOSFET Structure 220 -- 19.4 Summary 221 -- 19.5 Appendix: Brief Description of Physical Models in Simulations 221 -- References 225 -- 20 Impact of Local High‐κ Insulator on Drivability and Standby Power of Gate‐All‐Around SOI MOSFET 228 -- 20.1 Introduction 228 -- 20.2 Device Structure and Simulations 229 -- 20.3 Results and Discussion 230.
20.3.1 Device Characteristics of GAA Devices with Graded‐Profile Junctions 230 -- 20.3.2 Device Characteristics of GAA Devices with Abrupt Junctions 235 -- 20.3.3 Behaviors of Drivability and Off‐Current 237 -- 20.3.4 Dynamic Performance of Devices with Graded‐Profile Junctions 239 -- 20.4 Summary 239 -- References 240 -- Part V POTENTIAL OF PARTIALLY DEPLETED SOI MOSFETs 241 -- 21 Proposal for Cross‐Current Tetrode (XCT) SOI MOSFETs: A 60 dB Single‐Stage CMOS Amplifier Using High‐Gain Cross‐Current Tetrode MOSFET/SIMOX 243 -- 21.1 Introduction 243 -- 21.2 Device Fabrication 244 -- 21.3 Device Characteristics 245 -- 21.4 Performance of CMOS Amplifier 247 -- 21.5 Summary 249 -- References 249 -- 22 Device Model of the XCT‐SOI MOSFET and Scaling Scheme 250 -- 22.1 Introduction 250 -- 22.2 Device Structure and Assumptions for Modeling 251 -- 22.2.1 Device Structure and Features of XCT Device 251 -- 22.2.2 Basic Assumptions for Device Modeling 253 -- 22.2.3 Derivation of Model Equations 254 -- 22.3 Results and Discussion 258 -- 22.3.1 Measured Characteristics of XCT Devices 258 -- 22.4 Design Guidelines 261 -- 22.4.1 Drivability Control 261 -- 22.4.2 Scaling Issues 262 -- 22.4.3 Potentiality of Low‐Energy Operation of XCT CMOS Devices 265 -- 22.5 Summary 267 -- 22.6 Appendix: Calculation of MOSFET Channel Current 267 -- 22.7 Appendix: Basic Condition for Drivability Control 271 -- References 271 -- 23 Low‐Power Multivoltage Reference Circuit Using XCT‐SOI MOSFET 274 -- 23.1 Introduction 274 -- 23.2 Device Structure and Assumptions for Simulations 274 -- 23.2.1 Device Structure and Features 274 -- 23.2.2 Assumptions for Simulations 277 -- 23.3 Proposal for Voltage Reference Circuits and Simulation Results 278 -- 23.3.1 Two‐Reference Voltage Circuit 278 -- 23.3.2 Three‐Reference Voltage Circuit 283 -- 23.4 Summary 283 -- References 284 -- 24 Low‐Energy Operation Mechanisms for XCT‐SOI CMOS Devices: Prospects for a Sub‐20 nm Regime 285 -- 24.1 Introduction 285 -- 24.2 Device Structure and Assumptions for Modeling 286.
24.3 Circuit Simulation Results of SOI CMOS and XCT‐SOI CMOS 288 -- 24.4 Further Scaling Potential of XCT‐SOI MOSFET 291 -- 24.5 Performance Expected from the Scaled XCT‐SOI MOSFET 292 -- 24.6 Summary 296 -- References 296 -- Part VI QUANTUM EFFECTS AND APPLICATIONS / 1 297 -- 25 Overview 299 -- References 299 -- 26 Si Resonant Tunneling MOS Transistor 301 -- 26.1 Introduction 301 -- 26.2 Configuration of SRTMOST 302 -- 26.2.1 Structure and Electrostatic Potential 302 -- 26.2.2 Operation Principle and Subthreshold Characteristics 304 -- 26.3 Device Performance of SRTMOST 307 -- 26.3.1 Transistor Characteristics of SRTMOST 307 -- 26.3.2 Logic Circuit Using SRTMOST 310 -- 26.4 Summary 312 -- References 312 -- 27 Tunneling Dielectric Thin‐Film Transistor 314 -- 27.1 Introduction 314 -- 27.2 Fundamental Device Structure 315 -- 27.3 Experiment 315 -- 27.3.1 Experimental Method 315 -- 27.3.2 Calculation Method 317 -- 27.4 Results and Discussion 320 -- 27.4.1 Evaluation of SiNx Film 320 -- 27.4.2 Characteristics of the TDTFT 320 -- 27.4.3 TFT Performance at Low Temperatures 324 -- 27.4.4 TFT Performance at High Temperatures 324 -- 27.4.5 Suppression of the Hump Effect by the TDTFT 330 -- 27.5 Summary 336 -- References 336 -- 28 Proposal for a Tunnel‐Barrier Junction (TBJ) MOSFET 339 -- 28.1 Introduction 339 -- 28.2 Device Structure and Model 339 -- 28.3 Calculation Results 340 -- 28.4 Summary 343 -- References 343 -- 29 Performance Prediction of SOI Tunneling‐Barrier‐Junction MOSFET 344 -- 29.1 Introduction 344 -- 29.2 Simulation Model 345 -- 29.3 Simulation Results and Discussion 349 -- 29.3.1 Fundamental Properties of TBJ MOSFET 349 -- 29.3.2 Optimization of Device Parameters and Materials 349 -- 29.4 Summary 357 -- References 357 -- 30 Physics‐Based Model for TBJ‐MOSFETs and High‐Frequency Performance Prospects 358 -- 30.1 Introduction 358 -- 30.2 Device Structure and Device Model for Simulations 359 -- 30.3 Simulation Results and Discussion 360 -- 30.3.1 Current Drivability 361.
30.3.2 Threshold Voltage Issue 362 -- 30.3.3 Subthreshold Characteristics 363 -- 30.3.4 Radio‐Frequency Characteristics 363 -- 30.4 Summary 365 -- References 365 -- 31 Low‐Power High‐Temperature‐Operation‐Tolerant (HTOT) SOI MOSFET 367 -- 31.1 Introduction 367 -- 31.2 Device Structure and Simulations 368 -- 31.3 Results and Discussion 371 -- 31.3.1 Room‐Temperature Characteristics 371 -- 31.3.2 High‐Temperature Characteristics 373 -- 31.4 Summary 377 -- References 379 -- Part VII QUANTUM EFFECTS AND APPLICATIONS / 2 381 -- 32 Overview of Tunnel Field‐Effect Transistor 383 -- References 385 -- 33 Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field‐Effect Transistor 386 -- 33.1 Introduction 386 -- 33.2 Device Structure and Simulation 387 -- 33.3 Results and Discussion 387 -- 33.3.1 Effects of Variation in the Spacer Dielectric Constant 387 -- 33.3.2 Effects of Variation in the Spacer Width 391 -- 33.3.3 Effects of Variation in the Source Doping Concentration 392 -- 33.3.4 Effects of a Gate‐Source Overlap 394 -- 33.3.5 Effects of a Gate‐Channel Underlap 394 -- 33.4 Summary 397 -- References 397 -- 34 The Impact of a Fringing Field on the Device Performance of a P‐Channel Tunnel Field‐Effect Transistor with a High‐κ Gate Dielectric 399 -- 34.1 Introduction 399 -- 34.2 Device Structure and Simulation 399 -- 34.3 Results and Discussion 400 -- 34.3.1 Effects of Variation in the Gate Dielectric Constant 400 -- 34.3.2 Effects of Variation in the Spacer Dielectric Constant 408 -- 34.4 Summary 410 -- References 410 -- 35 Impact of a Spacer‐Drain Overlap on the Characteristics of a Silicon Tunnel Field‐Effect Transistor Based on Vertical Tunneling 412 -- 35.1 Introduction 412 -- 35.2 Device Structure and Process Steps 413 -- 35.3 Simulation Setup 414 -- 35.4 Results and Discussion 416 -- 35.4.1 Impact of Variation in the Spacer‐Drain Overlap 416 -- 35.4.2 Influence of Drain on the Device Characteristics 424 -- 35.4.3 Impact of Scaling 426.
35.5 Summary 429 -- References 430 -- 36 Gate‐on‐Germanium Source Tunnel Field‐Effect Transistor Enabling Sub‐0.5‐V Operation 431 -- 36.1 Introduction 431 -- 36.2 Proposed Device Structure 431 -- 36.3 Simulation Setup 432 -- 36.4 Results and Discussion 434 -- 36.4.1 Device Characteristics 434 -- 36.4.2 Effects of Different Structural Parameters 435 -- 36.4.3 Optimization of Different Structural Parameters 436 -- 36.5 Summary 445 -- References 445 -- Part VIII PROSPECTS OF LOW‐ENERGY DEVICE TECHNOLOLGY AND APPLICATIONS 447 -- 37 Performance Comparison of Modern Devices 449 -- References 450 -- 38 Emerging Device Technology and the Future of MOSFET 452 -- 38.1 Studies to Realize High‐Performance MOSFETs based on Unconventional Materials 452 -- 38.2 Challenging Studies to Realize High‐Performance MOSFETs based on the Nonconventional Doctrine 453 -- References 454 -- 39 How Devices Are and Should Be Applied to Circuits 456 -- 39.1 Past Approach 456 -- 39.2 Latest Studies 456 -- References 457 -- 40 Prospects for Low‐Energy Device Technology and Applications 458 -- References 459 -- Bibliography 460 -- Index 463.
Record Nr. UNINA-9910157536603321
Omura Y (Yasuhisa)  
Singapore ; ; Hoboken, NJ : , : John Wiley & Sons, , 2017
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
MOS devices for low-voltage and low-energy applications / / Yasuhisa Omura, Abhijit Mallik, and Naoto Matsuo
MOS devices for low-voltage and low-energy applications / / Yasuhisa Omura, Abhijit Mallik, and Naoto Matsuo
Autore Omura Y (Yasuhisa)
Pubbl/distr/stampa Singapore ; ; Hoboken, NJ : , : John Wiley & Sons, , 2017
Descrizione fisica 1 online resource (758 pages) : illustrations, tables, graphs
Disciplina 621.3815/284
Soggetto topico Metal oxide semiconductors
Metal oxide semiconductor field-effect transistors
Low voltage integrated circuits
Low voltage systems - Industrial applications
ISBN 1-5231-1527-0
1-119-10738-5
1-119-10736-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Preface XV -- Acknowledgments Xvi -- Part I Introduction To Low Voltage And Low Energy Devices 1 -- 1 Why Are Low Voltage And Low Energy Devices Desired? 3 -- References 4 -- 2 History Of Low Voltage And Low Power Devices 5 -- 2.1 Scaling Scheme And Low Voltage Requests 5 -- 2.2 Silicon On Insulator Devices And Real History 8 -- References 10 -- 3 Performance Prospects Of Subthreshold Logic Circuits 12 -- 3.1 Introduction 12 -- 3.2 Subthreshold Logic And Its Issues 12 -- 3.3 Is Subthreshold Logic The Best Solution? 13 -- References 13 -- Part Ii Summary Of Physics Of Modern Semiconductor Devices 15 -- 4 Overview 17 -- References 18 -- 5 Bulk Mosfet 19 -- 5.1 Theoretical Basis Of Bulk Mosfet Operation 19 -- 5.2 Subthreshold Characteristics: "Boff State" 19 -- 5.2.1 Fundamental Theory 19 -- 5.2.2 Influence Of Btbt Current 23 -- 5.2.3 Points To Be Remarked 24 -- 5.3 Post Threshold Characteristics: "Bon State" 24 -- 5.3.1 Fundamental Theory 24 -- 5.3.2 Self Heating Effects 26 -- 5.3.3 Parasitic Bipolar Effects 27 -- 5.4 Comprehensive Summary Of Short Channel Effects 27 -- References 28 -- 6 Soi Mosfet 29 -- 6.1 Partially Depleted Silicon On Insulator Metal Oxide Semiconductor Field Effect Transistors 29 -- 6.2 Fully Depleted (Fd) Soi Mosfet 30 -- 6.2.1 Subthreshold Characteristics 30 -- 6.2.2 Post Threshold Characteristics 36 -- 6.2.3 Comprehensive Summary Of Short Channel Effects 41 -- 6.3 Accumulation Mode (Am) Soi Mosfet 41 -- 6.3.1 Aspects Of Device Structure 41 -- 6.3.2 Subthreshold Characteristics 42 -- 6.3.3 Drain Current Component (I) Body Current (Id,Body) 43 -- 6.3.4 Drain Current Component (Ii) Surface Accumulation -- Layer Current (Id,Acc) 45 -- 6.3.5 Optional Discussions On The Accumulation Mode Soi Mosfet 45 -- 6.4 Finfet And Triple Gate Fet 46 -- 6.4.1 Introduction 46 -- 6.4.2 Device Structures And Simulations 46 -- 6.4.3 Results And Discussion 47 -- 6.4.4 Summary 49 -- 6.5 Gate All Around Mosfet 50 -- References 51 -- 7 Tunnel Field Effect Transistors (Tfets) 53.
7.1 Overview 53 -- 7.2 Model of Double‐Gate Lateral Tunnel FET and Device Performance Perspective 53 -- 7.2.1 Introduction 53 -- 7.2.2 Device Modeling 54 -- 7.2.3 Numerical Calculation Results and Discussion 61 -- 7.2.4 Summary 65 -- 7.3 Model of Vertical Tunnel FET and Aspects of its Characteristics 65 -- 7.3.1 Introduction 65 -- 7.3.2 Device Structure and Model Concept 65 -- 7.3.3 Comparing Model Results with TCAD Results 69 -- 7.3.4 Consideration of the Impact of Tunnel Dimensionality on Drivability 72 -- 7.3.5 Summary 75 -- 7.4 Appendix Integration of Eqs. (7.14) / (7.16) 76 -- References 78 -- Part III POTENTIAL OF CONVENTIONAL BULK MOSFETs 81 -- 8 Performance Evaluation of Analog Circuits with Deep Submicrometer MOSFETs in the Subthreshold Regime of Operation 83 -- 8.1 Introduction 83 -- 8.2 Subthreshold Operation and Device Simulation 84 -- 8.3 Model Description 85 -- 8.4 Results 86 -- 8.5 Summary 90 -- References 90 -- 9 Impact of Halo Doping on the Subthreshold Performance of Deep‐Submicrometer CMOS Devices and Circuits for Ultralow Power Analog/Mixed‐Signal Applications 91 -- 9.1 Introduction 91 -- 9.2 Device Structures and Simulation 92 -- 9.3 Subthreshold Operation 93 -- 9.4 Device Optimization for Subthreshold Analog Operation 95 -- 9.5 Subthreshold Analog Circuit Performance 98 -- 9.6 CMOS Amplifiers with Large Geometry Devices 105 -- 9.7 Summary 106 -- References 107 -- 10 Study of the Subthreshold Performance and the Effect of Channel Engineering on Deep Submicron Single‐Stage CMOS Amplifiers 108 -- 10.1 Introduction 108 -- 10.2 Circuit Description 108 -- 10.3 Device Structure and Simulation 110 -- 10.4 Results and Discussion 110 -- 10.5 PTAT as a Temperature Sensor 116 -- 10.6 Summary 116 -- References 116 -- 11 Subthreshold Performance of Dual‐Material Gate CMOS Devices and Circuits for Ultralow Power Analog/Mixed‐Signal Applications 117 -- 11.1 Introduction 117 -- 11.2 Device Structure and Simulation 118 -- 11.3 Results and Discussion 120 -- 11.4 Summary 126.
References 127 -- 12 Performance Prospect of Low‐Power Bulk MOSFETs 128 -- Reference 129 -- Part IV POTENTIAL OF FULLY‐DEPLETED SOI MOSFETs 131 -- 13 Demand for High‐Performance SOI Devices 133 -- 14 Demonstration of 100 nm Gate SOI CMOS with a Thin Buried Oxide Layer and its Impact on Device Technology 134 -- 14.1 Introduction 134 -- 14.2 Device Design Concept for 100 nm Gate SOI CMOS 134 -- 14.3 Device Fabrication 136 -- 14.4 Performance of 100‐nm‐ and 85‐nm Gate Devices 137 -- 14.4.1 Threshold and Subthreshold Characteristics 137 -- 14.4.2 Drain Current (ID)‐Drain Voltage (VD) and ID‐Gate Voltage (VG) Characteristics of 100‐nm‐Gate MOSFET/SIMOX 138 -- 14.4.3 ID / VD and ID / VG Characteristics of 85‐nm‐Gate MOSFET/SIMOX 142 -- 14.4.4 Switching Performance 142 -- 14.5 Discussion 142 -- 14.5.1 Threshold Voltage Balance in Ultrathin CMOS/SOI Devices 142 -- 14.6 Summary 144 -- References 145 -- 15 Discussion on Design Feasibility and Prospect of High‐Performance Sub‐50 nm Channel Single‐Gate SOI MOSFET Based on the ITRS Roadmap 147 -- 15.1 Introduction 147 -- 15.2 Device Structure and Simulations 148 -- 15.3 Proposed Model for Minimum Channel Length 149 -- 15.3.1 Minimum Channel Length Model Constructed using Extract A 149 -- 15.3.2 Minimum Channel Length Model Constructed using Extract B 150 -- 15.4 Performance Prospects of Scaled SOI MOSFETs 152 -- 15.4.1 Dynamic Operation Characteristics of Scaled SG SOI MOSFETs 152 -- 15.4.2 Tradeoff and Optimization of Standby Power Consumption and Dynamic Operation 157 -- 15.5 Summary 162 -- References 162 -- 16 Performance Prospects of Fully Depleted SOI MOSFET‐Based Diodes Applied to Schenkel Circuits for RF‐ID Chips 164 -- 16.1 Introduction 164 -- 16.2 Remaining Issues with Conventional Schenkel Circuits and an Advanced Proposal 165 -- 16.3 Simulation‐Based Consideration of RF Performance of SOI‐QD 172 -- 16.4 Summary 176 -- 16.5 Appendix: A Simulation Model for Minority Carrier Lifetime 177 -- 16.6 Appendix: Design Guideline for SOI‐QDs 177.
References 178 -- 17 The Potential and the Drawbacks of Underlap Single‐Gate Ultrathin SOI MOSFET 180 -- 17.1 Introduction 180 -- 17.2 Simulations 181 -- 17.3 Results and Discussion 183 -- 17.3.1 DC Characteristics and Switching Performance: Device A 183 -- 17.3.2 RF Analog Characteristics: Device A 184 -- 17.3.3 Impact of High‐κ Gate Dielectric on Performance of USU SOI MOSFET Devices: Devices B and C 185 -- 17.3.4 Impact of Simulation Model on Simulation Results 189 -- 17.4 Summary 192 -- References 192 -- 18 Practical Source/Drain Diffusion and Body Doping Layouts for High‐Performance and Low‐Energy Triple‐Gate SOI MOSFETs 194 -- 18.1 Introduction 194 -- 18.2 Device Structures and Simulation Model 195 -- 18.3 Results and Discussion 196 -- 18.3.1 Impact of S/D‐Underlying Layer on ION, IOFF, and Subthreshold Swing 196 -- 18.3.2 Tradeoff of Short‐Channel Effects and Drivability 196 -- 18.4 Summary 201 -- References 201 -- 19 Gate Field Engineering and Source/Drain Diffusion Engineering for High‐Performance Si Wire Gate‐All‐Around MOSFET and Low‐Power Strategy in a Sub‐30 nm‐Channel Regime 203 -- 19.1 Introduction 203 -- 19.2 Device Structures Assumed and Physical Parameters 204 -- 19.3 Simulation Results and Discussion 206 -- 19.3.1 Performance of Sub‐30 nm‐Channel Devices and Aspects of Device Characteristics 206 -- 19.3.2 Impact of Cross‐Section of Si Wire on Short‐Channel Effects and Drivability 212 -- 19.3.3 Minimizing Standby Power Consumption of GAA SOI MOSFET 216 -- 19.3.4 Prospective Switching Speed Performance of GAA SOI MOSFET 217 -- 19.3.5 Parasitic Resistance Issues of GAA Wire MOSFETs 218 -- 19.3.6 Proposal for Possible GAA Wire MOSFET Structure 220 -- 19.4 Summary 221 -- 19.5 Appendix: Brief Description of Physical Models in Simulations 221 -- References 225 -- 20 Impact of Local High‐κ Insulator on Drivability and Standby Power of Gate‐All‐Around SOI MOSFET 228 -- 20.1 Introduction 228 -- 20.2 Device Structure and Simulations 229 -- 20.3 Results and Discussion 230.
20.3.1 Device Characteristics of GAA Devices with Graded‐Profile Junctions 230 -- 20.3.2 Device Characteristics of GAA Devices with Abrupt Junctions 235 -- 20.3.3 Behaviors of Drivability and Off‐Current 237 -- 20.3.4 Dynamic Performance of Devices with Graded‐Profile Junctions 239 -- 20.4 Summary 239 -- References 240 -- Part V POTENTIAL OF PARTIALLY DEPLETED SOI MOSFETs 241 -- 21 Proposal for Cross‐Current Tetrode (XCT) SOI MOSFETs: A 60 dB Single‐Stage CMOS Amplifier Using High‐Gain Cross‐Current Tetrode MOSFET/SIMOX 243 -- 21.1 Introduction 243 -- 21.2 Device Fabrication 244 -- 21.3 Device Characteristics 245 -- 21.4 Performance of CMOS Amplifier 247 -- 21.5 Summary 249 -- References 249 -- 22 Device Model of the XCT‐SOI MOSFET and Scaling Scheme 250 -- 22.1 Introduction 250 -- 22.2 Device Structure and Assumptions for Modeling 251 -- 22.2.1 Device Structure and Features of XCT Device 251 -- 22.2.2 Basic Assumptions for Device Modeling 253 -- 22.2.3 Derivation of Model Equations 254 -- 22.3 Results and Discussion 258 -- 22.3.1 Measured Characteristics of XCT Devices 258 -- 22.4 Design Guidelines 261 -- 22.4.1 Drivability Control 261 -- 22.4.2 Scaling Issues 262 -- 22.4.3 Potentiality of Low‐Energy Operation of XCT CMOS Devices 265 -- 22.5 Summary 267 -- 22.6 Appendix: Calculation of MOSFET Channel Current 267 -- 22.7 Appendix: Basic Condition for Drivability Control 271 -- References 271 -- 23 Low‐Power Multivoltage Reference Circuit Using XCT‐SOI MOSFET 274 -- 23.1 Introduction 274 -- 23.2 Device Structure and Assumptions for Simulations 274 -- 23.2.1 Device Structure and Features 274 -- 23.2.2 Assumptions for Simulations 277 -- 23.3 Proposal for Voltage Reference Circuits and Simulation Results 278 -- 23.3.1 Two‐Reference Voltage Circuit 278 -- 23.3.2 Three‐Reference Voltage Circuit 283 -- 23.4 Summary 283 -- References 284 -- 24 Low‐Energy Operation Mechanisms for XCT‐SOI CMOS Devices: Prospects for a Sub‐20 nm Regime 285 -- 24.1 Introduction 285 -- 24.2 Device Structure and Assumptions for Modeling 286.
24.3 Circuit Simulation Results of SOI CMOS and XCT‐SOI CMOS 288 -- 24.4 Further Scaling Potential of XCT‐SOI MOSFET 291 -- 24.5 Performance Expected from the Scaled XCT‐SOI MOSFET 292 -- 24.6 Summary 296 -- References 296 -- Part VI QUANTUM EFFECTS AND APPLICATIONS / 1 297 -- 25 Overview 299 -- References 299 -- 26 Si Resonant Tunneling MOS Transistor 301 -- 26.1 Introduction 301 -- 26.2 Configuration of SRTMOST 302 -- 26.2.1 Structure and Electrostatic Potential 302 -- 26.2.2 Operation Principle and Subthreshold Characteristics 304 -- 26.3 Device Performance of SRTMOST 307 -- 26.3.1 Transistor Characteristics of SRTMOST 307 -- 26.3.2 Logic Circuit Using SRTMOST 310 -- 26.4 Summary 312 -- References 312 -- 27 Tunneling Dielectric Thin‐Film Transistor 314 -- 27.1 Introduction 314 -- 27.2 Fundamental Device Structure 315 -- 27.3 Experiment 315 -- 27.3.1 Experimental Method 315 -- 27.3.2 Calculation Method 317 -- 27.4 Results and Discussion 320 -- 27.4.1 Evaluation of SiNx Film 320 -- 27.4.2 Characteristics of the TDTFT 320 -- 27.4.3 TFT Performance at Low Temperatures 324 -- 27.4.4 TFT Performance at High Temperatures 324 -- 27.4.5 Suppression of the Hump Effect by the TDTFT 330 -- 27.5 Summary 336 -- References 336 -- 28 Proposal for a Tunnel‐Barrier Junction (TBJ) MOSFET 339 -- 28.1 Introduction 339 -- 28.2 Device Structure and Model 339 -- 28.3 Calculation Results 340 -- 28.4 Summary 343 -- References 343 -- 29 Performance Prediction of SOI Tunneling‐Barrier‐Junction MOSFET 344 -- 29.1 Introduction 344 -- 29.2 Simulation Model 345 -- 29.3 Simulation Results and Discussion 349 -- 29.3.1 Fundamental Properties of TBJ MOSFET 349 -- 29.3.2 Optimization of Device Parameters and Materials 349 -- 29.4 Summary 357 -- References 357 -- 30 Physics‐Based Model for TBJ‐MOSFETs and High‐Frequency Performance Prospects 358 -- 30.1 Introduction 358 -- 30.2 Device Structure and Device Model for Simulations 359 -- 30.3 Simulation Results and Discussion 360 -- 30.3.1 Current Drivability 361.
30.3.2 Threshold Voltage Issue 362 -- 30.3.3 Subthreshold Characteristics 363 -- 30.3.4 Radio‐Frequency Characteristics 363 -- 30.4 Summary 365 -- References 365 -- 31 Low‐Power High‐Temperature‐Operation‐Tolerant (HTOT) SOI MOSFET 367 -- 31.1 Introduction 367 -- 31.2 Device Structure and Simulations 368 -- 31.3 Results and Discussion 371 -- 31.3.1 Room‐Temperature Characteristics 371 -- 31.3.2 High‐Temperature Characteristics 373 -- 31.4 Summary 377 -- References 379 -- Part VII QUANTUM EFFECTS AND APPLICATIONS / 2 381 -- 32 Overview of Tunnel Field‐Effect Transistor 383 -- References 385 -- 33 Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field‐Effect Transistor 386 -- 33.1 Introduction 386 -- 33.2 Device Structure and Simulation 387 -- 33.3 Results and Discussion 387 -- 33.3.1 Effects of Variation in the Spacer Dielectric Constant 387 -- 33.3.2 Effects of Variation in the Spacer Width 391 -- 33.3.3 Effects of Variation in the Source Doping Concentration 392 -- 33.3.4 Effects of a Gate‐Source Overlap 394 -- 33.3.5 Effects of a Gate‐Channel Underlap 394 -- 33.4 Summary 397 -- References 397 -- 34 The Impact of a Fringing Field on the Device Performance of a P‐Channel Tunnel Field‐Effect Transistor with a High‐κ Gate Dielectric 399 -- 34.1 Introduction 399 -- 34.2 Device Structure and Simulation 399 -- 34.3 Results and Discussion 400 -- 34.3.1 Effects of Variation in the Gate Dielectric Constant 400 -- 34.3.2 Effects of Variation in the Spacer Dielectric Constant 408 -- 34.4 Summary 410 -- References 410 -- 35 Impact of a Spacer‐Drain Overlap on the Characteristics of a Silicon Tunnel Field‐Effect Transistor Based on Vertical Tunneling 412 -- 35.1 Introduction 412 -- 35.2 Device Structure and Process Steps 413 -- 35.3 Simulation Setup 414 -- 35.4 Results and Discussion 416 -- 35.4.1 Impact of Variation in the Spacer‐Drain Overlap 416 -- 35.4.2 Influence of Drain on the Device Characteristics 424 -- 35.4.3 Impact of Scaling 426.
35.5 Summary 429 -- References 430 -- 36 Gate‐on‐Germanium Source Tunnel Field‐Effect Transistor Enabling Sub‐0.5‐V Operation 431 -- 36.1 Introduction 431 -- 36.2 Proposed Device Structure 431 -- 36.3 Simulation Setup 432 -- 36.4 Results and Discussion 434 -- 36.4.1 Device Characteristics 434 -- 36.4.2 Effects of Different Structural Parameters 435 -- 36.4.3 Optimization of Different Structural Parameters 436 -- 36.5 Summary 445 -- References 445 -- Part VIII PROSPECTS OF LOW‐ENERGY DEVICE TECHNOLOLGY AND APPLICATIONS 447 -- 37 Performance Comparison of Modern Devices 449 -- References 450 -- 38 Emerging Device Technology and the Future of MOSFET 452 -- 38.1 Studies to Realize High‐Performance MOSFETs based on Unconventional Materials 452 -- 38.2 Challenging Studies to Realize High‐Performance MOSFETs based on the Nonconventional Doctrine 453 -- References 454 -- 39 How Devices Are and Should Be Applied to Circuits 456 -- 39.1 Past Approach 456 -- 39.2 Latest Studies 456 -- References 457 -- 40 Prospects for Low‐Energy Device Technology and Applications 458 -- References 459 -- Bibliography 460 -- Index 463.
Record Nr. UNINA-9910830903103321
Omura Y (Yasuhisa)  
Singapore ; ; Hoboken, NJ : , : John Wiley & Sons, , 2017
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Proceedings of the IEEE 2nd Dallas CAS Workshop on Low Power/Low Voltage Mixed-Signal Circuits & Systems (DCAS-01) : OMNI Hotel, Plano/Richardson, Texas, 26 March 2001
Proceedings of the IEEE 2nd Dallas CAS Workshop on Low Power/Low Voltage Mixed-Signal Circuits & Systems (DCAS-01) : OMNI Hotel, Plano/Richardson, Texas, 26 March 2001
Pubbl/distr/stampa [Place of publication not identified], : IEEE, 2001
Disciplina 621.3815
Soggetto topico Low voltage integrated circuits
Mixed signal circuits
Low voltage systems
Electrical & Computer Engineering
Engineering & Applied Sciences
Electrical Engineering
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNISA-996213532303316
[Place of publication not identified], : IEEE, 2001
Materiale a stampa
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Proceedings of the IEEE 2nd Dallas CAS Workshop on Low Power/Low Voltage Mixed-Signal Circuits & Systems (DCAS-01) : OMNI Hotel, Plano/Richardson, Texas, 26 March 2001
Proceedings of the IEEE 2nd Dallas CAS Workshop on Low Power/Low Voltage Mixed-Signal Circuits & Systems (DCAS-01) : OMNI Hotel, Plano/Richardson, Texas, 26 March 2001
Pubbl/distr/stampa [Place of publication not identified], : IEEE, 2001
Disciplina 621.3815
Soggetto topico Low voltage integrated circuits
Mixed signal circuits
Low voltage systems
Electrical & Computer Engineering
Engineering & Applied Sciences
Electrical Engineering
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNINA-9910872995203321
[Place of publication not identified], : IEEE, 2001
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Tunnel field-effect transistors (TFET) : modelling and simulations / / Jagadesh Kumar Mamidala, Rajat Vishnoi, Pratyush Pandey
Tunnel field-effect transistors (TFET) : modelling and simulations / / Jagadesh Kumar Mamidala, Rajat Vishnoi, Pratyush Pandey
Autore Kumar Mamidala Jagadesh
Edizione [1]
Pubbl/distr/stampa Hoboken : , : Wiley, , 2017
Descrizione fisica 1 online resource (208 p.)
Disciplina 621.3815/284
Soggetto topico Tunnel field-effect transistors
Integrated circuits - Design and construction
Nanostructured materials
Low voltage integrated circuits
ISBN 1-119-24630-X
1-119-24628-8
1-119-24631-8
Classificazione TEC008090
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Title Page ; Copyright; Contents; Preface; Chapter 1 Quantum mechanics ; 1.1 Introduction to quantum mechanics; 1.1.1 The double slit experiment; 1.1.2 Basic concepts of quantum mechanics; 1.1.3 Schrodingerś equation; 1.2 Basic quantum physics problems; 1.2.1 Free particle; 1.2.2 Particle in a one-dimensional box; Reference; Chapter 2 Basics of tunnelling ; 2.1 Understanding tunnelling; 2.1.1 Qualitative description; 2.1.2 Rectangular barrier; 2.2 WKB approximation; 2.3 Landauerś tunnelling formula; 2.4 Advanced tunnelling models; 2.4.1 Non-local tunnelling models
2.4.2 Local tunnelling modelsReferences; Chapter 3 The tunnel FET ; 3.1 Device structure; 3.1.1 The need for tunnel FETs; 3.1.2 Basic TFET structure; 3.2 Qualitative behaviour; 3.2.1 Band diagram; 3.2.2 Device characteristics; 3.2.3 Performance dependence on device parameters; 3.3 Types of TFETs; 3.3.1 Planar TFETs; 3.3.2 Three-dimensional TFETs; 3.3.3 Carbon nanotube and graphene TFETs; 3.3.4 Point versus line tunnelling in TFETs; 3.4 Other steep subthreshold transistors; References; Chapter 4 Drain current modelling of tunnel FET: the task and its challenges ; 4.1 Introduction
4.2 TFETmodelling approach4.2.1 Finding the value of ψC; 4.2.2 Modelling the surface potential in the source-channel junction; 4.2.3 Finding the tunnelling current; 4.3 MOSFETmodelling approach; References; Chapter 5 Modelling the surface potential in TFETs ; 5.1 The pseudo-2D method; 5.1.1 Parabolic approximation of potential distribution; 5.1.2 Solving the 2D Poisson equation using parabolic approximation; 5.1.3 Solution for the surface potential; 5.2 The variational approach; 5.2.1 The variational form of Poissonś equation
5.2.2 Solution of the variational form of Poissonś equation in a TFET5.3 The infinite series solution; 5.3.1 Solving the 2D Poisson equation using separation of variables; 5.3.2 Solution of the homogeneous boundary value problem; 5.3.3 The solution to the 2D Poisson equation in a TFET; 5.3.4 The infinite series solution to Poissonś equation in a TFET; 5.4 Extension of surface potential models to differentTFETstructures; 5.4.1 DG TFET; 5.4.2 GAA TFET; 5.4.3 Dual material gate TFET; 5.5 The effect of localised charges on the surface potential; 5.6 Surface potential in the depletion regions
5.7 Use of smoothing functions in the surface potential modelsReferences; Chapter 6 Modelling the drain current ; 6.1 Non-local methods; 6.1.1 Landauerś tunnelling formula in TFETs; 6.1.2 WKB approximation in TFETs; 6.1.3 Obtaining the drain current; 6.2 Local methods; 6.2.1 Numerical integration; 6.2.2 Shortest tunnelling length; 6.2.3 Constant polynomial term assumption; 6.2.4 Tangent line approximation; 6.3 Threshold voltage models; 6.3.1 Constant current method; 6.3.2 Constant tunnelling length; 6.3.3 Transconductance change (TC) method; References
Chapter 7 Device simulation using ATLAS
Record Nr. UNINA-9910135029103321
Kumar Mamidala Jagadesh  
Hoboken : , : Wiley, , 2017
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Tunnel field-effect transistors (TFET) : modelling and simulations / / Jagadesh Kumar Mamidala, Rajat Vishnoi, Pratyush Pandey
Tunnel field-effect transistors (TFET) : modelling and simulations / / Jagadesh Kumar Mamidala, Rajat Vishnoi, Pratyush Pandey
Autore Kumar Mamidala Jagadesh
Edizione [1]
Pubbl/distr/stampa Hoboken : , : Wiley, , 2017
Descrizione fisica 1 online resource (208 p.)
Disciplina 621.3815/284
Soggetto topico Tunnel field-effect transistors
Integrated circuits - Design and construction
Nanostructured materials
Low voltage integrated circuits
ISBN 1-119-24630-X
1-119-24628-8
1-119-24631-8
Classificazione TEC008090
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Title Page ; Copyright; Contents; Preface; Chapter 1 Quantum mechanics ; 1.1 Introduction to quantum mechanics; 1.1.1 The double slit experiment; 1.1.2 Basic concepts of quantum mechanics; 1.1.3 Schrodingerś equation; 1.2 Basic quantum physics problems; 1.2.1 Free particle; 1.2.2 Particle in a one-dimensional box; Reference; Chapter 2 Basics of tunnelling ; 2.1 Understanding tunnelling; 2.1.1 Qualitative description; 2.1.2 Rectangular barrier; 2.2 WKB approximation; 2.3 Landauerś tunnelling formula; 2.4 Advanced tunnelling models; 2.4.1 Non-local tunnelling models
2.4.2 Local tunnelling modelsReferences; Chapter 3 The tunnel FET ; 3.1 Device structure; 3.1.1 The need for tunnel FETs; 3.1.2 Basic TFET structure; 3.2 Qualitative behaviour; 3.2.1 Band diagram; 3.2.2 Device characteristics; 3.2.3 Performance dependence on device parameters; 3.3 Types of TFETs; 3.3.1 Planar TFETs; 3.3.2 Three-dimensional TFETs; 3.3.3 Carbon nanotube and graphene TFETs; 3.3.4 Point versus line tunnelling in TFETs; 3.4 Other steep subthreshold transistors; References; Chapter 4 Drain current modelling of tunnel FET: the task and its challenges ; 4.1 Introduction
4.2 TFETmodelling approach4.2.1 Finding the value of ψC; 4.2.2 Modelling the surface potential in the source-channel junction; 4.2.3 Finding the tunnelling current; 4.3 MOSFETmodelling approach; References; Chapter 5 Modelling the surface potential in TFETs ; 5.1 The pseudo-2D method; 5.1.1 Parabolic approximation of potential distribution; 5.1.2 Solving the 2D Poisson equation using parabolic approximation; 5.1.3 Solution for the surface potential; 5.2 The variational approach; 5.2.1 The variational form of Poissonś equation
5.2.2 Solution of the variational form of Poissonś equation in a TFET5.3 The infinite series solution; 5.3.1 Solving the 2D Poisson equation using separation of variables; 5.3.2 Solution of the homogeneous boundary value problem; 5.3.3 The solution to the 2D Poisson equation in a TFET; 5.3.4 The infinite series solution to Poissonś equation in a TFET; 5.4 Extension of surface potential models to differentTFETstructures; 5.4.1 DG TFET; 5.4.2 GAA TFET; 5.4.3 Dual material gate TFET; 5.5 The effect of localised charges on the surface potential; 5.6 Surface potential in the depletion regions
5.7 Use of smoothing functions in the surface potential modelsReferences; Chapter 6 Modelling the drain current ; 6.1 Non-local methods; 6.1.1 Landauerś tunnelling formula in TFETs; 6.1.2 WKB approximation in TFETs; 6.1.3 Obtaining the drain current; 6.2 Local methods; 6.2.1 Numerical integration; 6.2.2 Shortest tunnelling length; 6.2.3 Constant polynomial term assumption; 6.2.4 Tangent line approximation; 6.3 Threshold voltage models; 6.3.1 Constant current method; 6.3.2 Constant tunnelling length; 6.3.3 Transconductance change (TC) method; References
Chapter 7 Device simulation using ATLAS
Record Nr. UNINA-9910817038703321
Kumar Mamidala Jagadesh  
Hoboken : , : Wiley, , 2017
Materiale a stampa
Lo trovi qui: Univ. Federico II
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Ultra low power transceiver for wireless body area networks / / Jens Masuch, Manuel Delgado-Restituto
Ultra low power transceiver for wireless body area networks / / Jens Masuch, Manuel Delgado-Restituto
Autore Masuch Jens
Edizione [1st ed. 2013.]
Pubbl/distr/stampa New York, : Springer, 2013
Descrizione fisica 1 online resource (122 p.)
Disciplina 621.3845
Altri autori (Persone) Delgado-RestitutoManuel
Collana Analog circuits and signal processing
Soggetto topico Low voltage integrated circuits
Radio - Transmitter-receivers
ISBN 3-319-00098-5
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction -- Review of the state of the art -- Low power strategies -- Implementation of the low power transceiver -- Co-integration of RF energy harvesting -- Conclusions.
Record Nr. UNINA-9910437769303321
Masuch Jens  
New York, : Springer, 2013
Materiale a stampa
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Ultra-low input power conversion circuits based on tunnel FETs / / David Cavalheiro, Francesc Moll, Stanimir Valtchev
Ultra-low input power conversion circuits based on tunnel FETs / / David Cavalheiro, Francesc Moll, Stanimir Valtchev
Autore Cavalheiro David
Pubbl/distr/stampa Gistrup, Denmark : , : River Publishers, , [2018]
Descrizione fisica 1 online resource (198 pages)
Disciplina 621.381
Collana River Publishers Series in Circuits and Systems
Soggetto topico Digital electronics - Design and construction
Low voltage integrated circuits
Soggetto genere / forma Electronic books.
ISBN 87-93609-75-2
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNINA-9910480373503321
Cavalheiro David  
Gistrup, Denmark : , : River Publishers, , [2018]
Materiale a stampa
Lo trovi qui: Univ. Federico II
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