Info
- Utilizzare la checkbox di selezione a fianco di ciascun documento per attivare le funzionalità di stampa, invio email, download nei formati disponibili del (i) record.
Proceedings / / International Conference on Innovative Systems in Silicon
| Proceedings / / International Conference on Innovative Systems in Silicon |
| Pubbl/distr/stampa | [New York, N.Y.], : Institute of Electrical and Electronics Engineers, c1996- |
| Descrizione fisica | 1 online resource |
| Disciplina | 621.39/5 |
| Soggetto topico |
Integrated circuits - Very large scale integration
Integrated circuits - Wafer-scale integration Semiconductors |
| Soggetto genere / forma |
Conference papers and proceedings.
Congresses. |
| Formato | Materiale a stampa  |
| Livello bibliografico | Periodico |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
IEEE International Conference on Innovative Systems in Silicon
IEEE Innovative systems in Silicon Innovative Systems in Silicon |
| Record Nr. | UNINA-9910626012503321 |
| [New York, N.Y.], : Institute of Electrical and Electronics Engineers, c1996- | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Proceedings / / International Conference on Wafer Scale Integration
| Proceedings / / International Conference on Wafer Scale Integration |
| Pubbl/distr/stampa | Washington, D.C., : IEEE Computer Society Press, ©1989-©1995 |
| Descrizione fisica | 1 online resource |
| Disciplina | 621.3815 |
| Soggetto topico | Integrated circuits - Wafer-scale integration |
| Soggetto genere / forma | Conference papers and proceedings. |
| Formato | Materiale a stampa |
| Livello bibliografico | Periodico |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996281128603316 |
| Washington, D.C., : IEEE Computer Society Press, ©1989-©1995 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Proceedings / / International Conference on Wafer Scale Integration
| Proceedings / / International Conference on Wafer Scale Integration |
| Pubbl/distr/stampa | Washington, D.C., : IEEE Computer Society Press, ©1989-©1995 |
| Descrizione fisica | 1 online resource |
| Disciplina | 621.3815 |
| Soggetto topico | Integrated circuits - Wafer-scale integration |
| Soggetto genere / forma | Conference papers and proceedings. |
| Formato | Materiale a stampa |
| Livello bibliografico | Periodico |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910626174303321 |
| Washington, D.C., : IEEE Computer Society Press, ©1989-©1995 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Wafer Scale Integration: Proceedings of the 1st International Conference , 1989
| Wafer Scale Integration: Proceedings of the 1st International Conference , 1989 |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society Press, 1989 |
| Descrizione fisica | 1 online resource (xiv, 412 pages) : illustrations |
| Disciplina | 621.3815 |
| Soggetto topico | Integrated circuits - Wafer-scale integration |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996211372803316 |
| [Place of publication not identified], : IEEE Computer Society Press, 1989 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Wafer Scale Integration: Proceedings of the 1st International Conference , 1989
| Wafer Scale Integration: Proceedings of the 1st International Conference , 1989 |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society Press, 1989 |
| Descrizione fisica | 1 online resource (xiv, 412 pages) : illustrations |
| Disciplina | 621.3815 |
| Soggetto topico | Integrated circuits - Wafer-scale integration |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910872662903321 |
| [Place of publication not identified], : IEEE Computer Society Press, 1989 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Wafer-level testing and test during burn-in for integrated circuits / / Sudarshan Bahukudumbi, Krishnendu Chakrabarty
| Wafer-level testing and test during burn-in for integrated circuits / / Sudarshan Bahukudumbi, Krishnendu Chakrabarty |
| Autore | Bahukudumbi Sudarshan |
| Pubbl/distr/stampa | Boston : , : Artech House, , 2010 |
| Descrizione fisica | 1 online resource (214 p.) |
| Disciplina | 621.38132 |
| Collana | Artech House integrated microsystems series |
| Soggetto topico |
Integrated circuits - Testing
Integrated circuits - Wafer-scale integration Semiconductors - Testing |
| Soggetto genere / forma | Electronic books. |
| ISBN | 1-59693-990-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Wafer-Level Test and Burn-In: Industry Practices and Trends -- Resource-Constrained Testing of Core-Based ScCs -- Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs -- Wafer-Level Test During Burn-In: Test Scheduling for Core-Based SoCs -- Wafer-Level Test During Burn-In: Power Management by Test-Pattern Ordering -- Wafer-Level Test During Burn-In: Power Management by Test-Pattern Manipulation. |
| Record Nr. | UNINA-9910460055803321 |
Bahukudumbi Sudarshan
|
||
| Boston : , : Artech House, , 2010 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Wafer-level testing and test during burn-in for integrated circuits / / Sudarshan Bahukudumbi, Krishnendu Chakrabarty
| Wafer-level testing and test during burn-in for integrated circuits / / Sudarshan Bahukudumbi, Krishnendu Chakrabarty |
| Autore | Bahukudumbi Sudarshan |
| Pubbl/distr/stampa | Boston : , : Artech House, , 2010 |
| Descrizione fisica | 1 online resource (214 p.) |
| Disciplina | 621.38132 |
| Collana | Artech House integrated microsystems series |
| Soggetto topico |
Integrated circuits - Testing
Integrated circuits - Wafer-scale integration Semiconductors - Testing |
| ISBN | 1-59693-990-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Wafer-Level Test and Burn-In: Industry Practices and Trends -- Resource-Constrained Testing of Core-Based ScCs -- Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs -- Wafer-Level Test During Burn-In: Test Scheduling for Core-Based SoCs -- Wafer-Level Test During Burn-In: Power Management by Test-Pattern Ordering -- Wafer-Level Test During Burn-In: Power Management by Test-Pattern Manipulation. |
| Record Nr. | UNINA-9910785154803321 |
|
Bahukudumbi Sudarshan
|
||
| Boston : , : Artech House, , 2010 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Wafer-level testing and test during burn-in for integrated circuits / / Sudarshan Bahukudumbi, Krishnendu Chakrabarty
| Wafer-level testing and test during burn-in for integrated circuits / / Sudarshan Bahukudumbi, Krishnendu Chakrabarty |
| Autore | Bahukudumbi Sudarshan |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Boston, : Artech House, 2010 |
| Descrizione fisica | 1 online resource (214 p.) |
| Disciplina | 621.38132 |
| Altri autori (Persone) | ChakrabartyKrishnendu |
| Collana | Artech House integrated microsystems series |
| Soggetto topico |
Integrated circuits - Testing
Integrated circuits - Wafer-scale integration Semiconductors - Testing |
| ISBN | 1-59693-990-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Wafer-Level Test and Burn-In: Industry Practices and Trends -- Resource-Constrained Testing of Core-Based ScCs -- Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs -- Wafer-Level Test During Burn-In: Test Scheduling for Core-Based SoCs -- Wafer-Level Test During Burn-In: Power Management by Test-Pattern Ordering -- Wafer-Level Test During Burn-In: Power Management by Test-Pattern Manipulation. |
| Record Nr. | UNINA-9910821427203321 |
|
Bahukudumbi Sudarshan
|
||
| Boston, : Artech House, 2010 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
