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Proceedings of Technical Program of ... International Symposium on VLSI Design, Automation and Test
| Proceedings of Technical Program of ... International Symposium on VLSI Design, Automation and Test |
| Pubbl/distr/stampa | Piscataway, NJ : , : IEEE |
| Disciplina | 621 |
| Soggetto topico |
Integrated circuits - Very large scale integration - Design and construction
Integrated circuits - Very large scale integration - Testing Integrated circuits - Very large scale integration |
| Soggetto genere / forma | Conference papers and proceedings. |
| ISSN | 2472-9124 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Periodico |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
Proceedings of Technical Program of ... International Symposium on VLSI Design, Automation & Test
VLSI-DAT .. International Symposium on VLSI Design, Automation & Test IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test (VLSI-TSA-DAT) |
| Record Nr. | UNINA-9910626138603321 |
| Piscataway, NJ : , : IEEE | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Proceedings of Technical Program of ... International Symposium on VLSI Design, Automation and Test
| Proceedings of Technical Program of ... International Symposium on VLSI Design, Automation and Test |
| Pubbl/distr/stampa | Piscataway, NJ : , : IEEE |
| Disciplina | 621 |
| Soggetto topico |
Integrated circuits - Very large scale integration - Design and construction
Integrated circuits - Very large scale integration - Testing Integrated circuits - Very large scale integration |
| Soggetto genere / forma | Conference papers and proceedings. |
| ISSN | 2472-9124 |
| Formato | Materiale a stampa |
| Livello bibliografico | Periodico |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
Proceedings of Technical Program of ... International Symposium on VLSI Design, Automation & Test
VLSI-DAT .. International Symposium on VLSI Design, Automation & Test IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test (VLSI-TSA-DAT) |
| Record Nr. | UNISA-996581528103316 |
| Piscataway, NJ : , : IEEE | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Proceedings of the ... IEEE VLSI Test Symposium : VTS
| Proceedings of the ... IEEE VLSI Test Symposium : VTS |
| Pubbl/distr/stampa | [Los Alamitos, Calif.], : [IEEE Computer Society Press] |
| Disciplina | 621 |
| Soggetto topico | Integrated circuits - Very large scale integration - Testing |
| Soggetto genere / forma | Conference papers and proceedings. |
| ISSN | 2375-1053 |
| Formato | Materiale a stampa |
| Livello bibliografico | Periodico |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
IEEE VLSI Test Symposium
IEEE Very Large Scale Integration Test Symposium VLSI Test Symposium Very Large Scale Integration Test Symposium VTS Proceedings ... IEEE ... VLSI Test Symposium |
| Record Nr. | UNINA-9910625192803321 |
| [Los Alamitos, Calif.], : [IEEE Computer Society Press] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Proceedings of the ... IEEE VLSI Test Symposium : VTS
| Proceedings of the ... IEEE VLSI Test Symposium : VTS |
| Pubbl/distr/stampa | [Los Alamitos, Calif.], : [IEEE Computer Society Press] |
| Disciplina | 621 |
| Soggetto topico | Integrated circuits - Very large scale integration - Testing |
| Soggetto genere / forma | Conference papers and proceedings. |
| ISSN | 2375-1053 |
| Formato | Materiale a stampa |
| Livello bibliografico | Periodico |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
IEEE VLSI Test Symposium
IEEE Very Large Scale Integration Test Symposium VLSI Test Symposium Very Large Scale Integration Test Symposium VTS Proceedings ... IEEE ... VLSI Test Symposium |
| Record Nr. | UNISA-996280005703316 |
| [Los Alamitos, Calif.], : [IEEE Computer Society Press] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
System-on-chip test architectures [[electronic resource] ] : nanometer design for testability / / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba
| System-on-chip test architectures [[electronic resource] ] : nanometer design for testability / / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 |
| Descrizione fisica | 1 online resource (893 p.) |
| Disciplina | 621.39/5 |
| Altri autori (Persone) |
WangLaung-Terng
StroudCharles E ToubaNur A |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Systems on a chip - Testing
Integrated circuits - Very large scale integration - Testing Integrated circuits - Very large scale integration - Design |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-281-10004-8
9786611100049 0-08-055680-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; System-on-Chip Test Architectures; Copyright Page; Table of Contents; Preface; In the Classroom; Acknowledgments; Contributors; About the Editors; Chapter 1 Introduction; 1.1 Importance of System-on-Chip Testing; 1.1.1 Yield and Reject Rate; 1.1.2 Reliability and System Availability; 1.2 Basics of SOC Testing; 1.2.1 Boundary Scan (IEEE 1149.1 Standard); 1.2.2 Boundary Scan Extension (IEEE 1149.6 Standard); 1.2.3 Boundary-Scan Accessible Embedded Instruments (IEEE P1687); 1.2.4 Core-Based Testing (IEEE 1500 Standard); 1.2.5 Analog Boundary Scan (IEEE 1149.4 Standard)
1.3 Basics of Memory Testing1.4 SOC Design Examples; 1.4.1 BioMEMS Sensor; 1.4.2 Network-on-Chip Processor; 1.5 About This Book; 1.5.1 DFT Architectures; 1.5.2 New Fault Models and Advanced Techniques; 1.5.3 Yield and Reliability Enhancement; 1.5.4 Nanotechnology Testing Aspects; 1.6 Exercises; Acknowledgments; References; Chapter 2 Digital Test Architectures; 2.1 Introduction; 2.2 Scan Design; 2.2.1 Scan Architectures; 2.2.1.1 Muxed-D Scan Design; 2.2.1.2 Clocked-Scan Design; 2.2.1.3 LSSD Scan Design; 2.2.1.4 Enhanced-Scan Design; 2.2.2 Low-Power Scan Architectures 2.2.2.1 Reduced-Voltage Low-Power Scan Design2.2.2.2 Reduced-Frequency Low-Power Scan Design; 2.2.2.3 Multi-Phase or Multi-Duty Low-Power Scan Design; 2.2.2.4 Bandwidth-Matching Low-Power Scan Design; 2.2.2.5 Hybrid Low-Power Scan Design; 2.2.3 At-Speed Scan Architectures; 2.3 Logic Built-In Self-Test; 2.3.1 Logic BIST Architectures; 2.3.1.1 Self-Testing Using MISR and Parallel SRSG (STUMPS); 2.3.1.2 Concurrent Built-In Logic Block Observer (CBILBO); 2.3.2 Coverage-Driven Logic BIST Architectures; 2.3.2.1 Weighted Pattern Generation; 2.3.2.2 Test Point Insertion; 2.3.2.3 Mixed-Mode BIST 2.3.2.4 Hybrid BIST2.3.3 Low-Power Logic BIST Architectures; 2.3.3.1 Low-Transition BIST Design; 2.3.3.2 Test-Vector-Inhibiting BIST Design; 2.3.3.3 Modified LFSR Low-Power BIST Design; 2.3.4 At-Speed Logic BIST Architectures; 2.3.4.1 Single-Capture; 2.3.4.2 Skewed-Load; 2.3.4.3 Double-Capture; 2.3.5 Industry Practices; 2.4 Test Compression; 2.4.1 Circuits for Test Stimulus Compression; 2.4.1.1 Linear-Decompression-Based Schemes; 2.4.1.2 Broadcast-Scan-Based Schemes; 2.4.1.3 Comparison; 2.4.2 Circuits for Test Response Compaction; 2.4.2.1 Space Compaction; 2.4.2.2 Time Compaction 2.4.2.3 Mixed Time and Space Compaction2.4.3 Low-Power Test Compression Architectures; 2.4.4 Industry Practices; 2.5 Random-Access Scan Design; 2.5.1 Random-Access Scan Architectures; 2.5.1.1 Progressive Random-Access Scan Design; 2.5.1.2 Shift-Addressable Random-Access Scan Design; 2.5.2 Test Compression RAS Architectures; 2.5.3 At-Speed RAS Architectures; 2.6 Concluding Remarks; 2.7 Exercises; Acknowledgments; References; Chapter 3 Fault-Tolerant Design; 3.1 Introduction; 3.2 Fundamentals of Fault Tolerance; 3.2.1 Reliability; 3.2.2 Mean Time to Failure (MTTF); 3.2.3 Maintainability 3.2.4 Availability |
| Record Nr. | UNINA-9910451492103321 |
| Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
System-on-chip test architectures [[electronic resource] ] : nanometer design for testability / / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba
| System-on-chip test architectures [[electronic resource] ] : nanometer design for testability / / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 |
| Descrizione fisica | 1 online resource (893 p.) |
| Disciplina | 621.39/5 |
| Altri autori (Persone) |
WangLaung-Terng
StroudCharles E ToubaNur A |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Systems on a chip - Testing
Integrated circuits - Very large scale integration - Testing Integrated circuits - Very large scale integration - Design |
| ISBN |
1-281-10004-8
9786611100049 0-08-055680-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; System-on-Chip Test Architectures; Copyright Page; Table of Contents; Preface; In the Classroom; Acknowledgments; Contributors; About the Editors; Chapter 1 Introduction; 1.1 Importance of System-on-Chip Testing; 1.1.1 Yield and Reject Rate; 1.1.2 Reliability and System Availability; 1.2 Basics of SOC Testing; 1.2.1 Boundary Scan (IEEE 1149.1 Standard); 1.2.2 Boundary Scan Extension (IEEE 1149.6 Standard); 1.2.3 Boundary-Scan Accessible Embedded Instruments (IEEE P1687); 1.2.4 Core-Based Testing (IEEE 1500 Standard); 1.2.5 Analog Boundary Scan (IEEE 1149.4 Standard)
1.3 Basics of Memory Testing1.4 SOC Design Examples; 1.4.1 BioMEMS Sensor; 1.4.2 Network-on-Chip Processor; 1.5 About This Book; 1.5.1 DFT Architectures; 1.5.2 New Fault Models and Advanced Techniques; 1.5.3 Yield and Reliability Enhancement; 1.5.4 Nanotechnology Testing Aspects; 1.6 Exercises; Acknowledgments; References; Chapter 2 Digital Test Architectures; 2.1 Introduction; 2.2 Scan Design; 2.2.1 Scan Architectures; 2.2.1.1 Muxed-D Scan Design; 2.2.1.2 Clocked-Scan Design; 2.2.1.3 LSSD Scan Design; 2.2.1.4 Enhanced-Scan Design; 2.2.2 Low-Power Scan Architectures 2.2.2.1 Reduced-Voltage Low-Power Scan Design2.2.2.2 Reduced-Frequency Low-Power Scan Design; 2.2.2.3 Multi-Phase or Multi-Duty Low-Power Scan Design; 2.2.2.4 Bandwidth-Matching Low-Power Scan Design; 2.2.2.5 Hybrid Low-Power Scan Design; 2.2.3 At-Speed Scan Architectures; 2.3 Logic Built-In Self-Test; 2.3.1 Logic BIST Architectures; 2.3.1.1 Self-Testing Using MISR and Parallel SRSG (STUMPS); 2.3.1.2 Concurrent Built-In Logic Block Observer (CBILBO); 2.3.2 Coverage-Driven Logic BIST Architectures; 2.3.2.1 Weighted Pattern Generation; 2.3.2.2 Test Point Insertion; 2.3.2.3 Mixed-Mode BIST 2.3.2.4 Hybrid BIST2.3.3 Low-Power Logic BIST Architectures; 2.3.3.1 Low-Transition BIST Design; 2.3.3.2 Test-Vector-Inhibiting BIST Design; 2.3.3.3 Modified LFSR Low-Power BIST Design; 2.3.4 At-Speed Logic BIST Architectures; 2.3.4.1 Single-Capture; 2.3.4.2 Skewed-Load; 2.3.4.3 Double-Capture; 2.3.5 Industry Practices; 2.4 Test Compression; 2.4.1 Circuits for Test Stimulus Compression; 2.4.1.1 Linear-Decompression-Based Schemes; 2.4.1.2 Broadcast-Scan-Based Schemes; 2.4.1.3 Comparison; 2.4.2 Circuits for Test Response Compaction; 2.4.2.1 Space Compaction; 2.4.2.2 Time Compaction 2.4.2.3 Mixed Time and Space Compaction2.4.3 Low-Power Test Compression Architectures; 2.4.4 Industry Practices; 2.5 Random-Access Scan Design; 2.5.1 Random-Access Scan Architectures; 2.5.1.1 Progressive Random-Access Scan Design; 2.5.1.2 Shift-Addressable Random-Access Scan Design; 2.5.2 Test Compression RAS Architectures; 2.5.3 At-Speed RAS Architectures; 2.6 Concluding Remarks; 2.7 Exercises; Acknowledgments; References; Chapter 3 Fault-Tolerant Design; 3.1 Introduction; 3.2 Fundamentals of Fault Tolerance; 3.2.1 Reliability; 3.2.2 Mean Time to Failure (MTTF); 3.2.3 Maintainability 3.2.4 Availability |
| Record Nr. | UNINA-9910785095503321 |
| Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
System-on-chip test architectures : nanometer design for testability / / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba
| System-on-chip test architectures : nanometer design for testability / / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 |
| Descrizione fisica | 1 online resource (893 p.) |
| Disciplina | 621.39/5 |
| Altri autori (Persone) |
WangLaung-Terng
StroudCharles E ToubaNur A |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Systems on a chip - Testing
Integrated circuits - Very large scale integration - Testing Integrated circuits - Very large scale integration - Design |
| ISBN |
1-281-10004-8
9786611100049 0-08-055680-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; System-on-Chip Test Architectures; Copyright Page; Table of Contents; Preface; In the Classroom; Acknowledgments; Contributors; About the Editors; Chapter 1 Introduction; 1.1 Importance of System-on-Chip Testing; 1.1.1 Yield and Reject Rate; 1.1.2 Reliability and System Availability; 1.2 Basics of SOC Testing; 1.2.1 Boundary Scan (IEEE 1149.1 Standard); 1.2.2 Boundary Scan Extension (IEEE 1149.6 Standard); 1.2.3 Boundary-Scan Accessible Embedded Instruments (IEEE P1687); 1.2.4 Core-Based Testing (IEEE 1500 Standard); 1.2.5 Analog Boundary Scan (IEEE 1149.4 Standard)
1.3 Basics of Memory Testing1.4 SOC Design Examples; 1.4.1 BioMEMS Sensor; 1.4.2 Network-on-Chip Processor; 1.5 About This Book; 1.5.1 DFT Architectures; 1.5.2 New Fault Models and Advanced Techniques; 1.5.3 Yield and Reliability Enhancement; 1.5.4 Nanotechnology Testing Aspects; 1.6 Exercises; Acknowledgments; References; Chapter 2 Digital Test Architectures; 2.1 Introduction; 2.2 Scan Design; 2.2.1 Scan Architectures; 2.2.1.1 Muxed-D Scan Design; 2.2.1.2 Clocked-Scan Design; 2.2.1.3 LSSD Scan Design; 2.2.1.4 Enhanced-Scan Design; 2.2.2 Low-Power Scan Architectures 2.2.2.1 Reduced-Voltage Low-Power Scan Design2.2.2.2 Reduced-Frequency Low-Power Scan Design; 2.2.2.3 Multi-Phase or Multi-Duty Low-Power Scan Design; 2.2.2.4 Bandwidth-Matching Low-Power Scan Design; 2.2.2.5 Hybrid Low-Power Scan Design; 2.2.3 At-Speed Scan Architectures; 2.3 Logic Built-In Self-Test; 2.3.1 Logic BIST Architectures; 2.3.1.1 Self-Testing Using MISR and Parallel SRSG (STUMPS); 2.3.1.2 Concurrent Built-In Logic Block Observer (CBILBO); 2.3.2 Coverage-Driven Logic BIST Architectures; 2.3.2.1 Weighted Pattern Generation; 2.3.2.2 Test Point Insertion; 2.3.2.3 Mixed-Mode BIST 2.3.2.4 Hybrid BIST2.3.3 Low-Power Logic BIST Architectures; 2.3.3.1 Low-Transition BIST Design; 2.3.3.2 Test-Vector-Inhibiting BIST Design; 2.3.3.3 Modified LFSR Low-Power BIST Design; 2.3.4 At-Speed Logic BIST Architectures; 2.3.4.1 Single-Capture; 2.3.4.2 Skewed-Load; 2.3.4.3 Double-Capture; 2.3.5 Industry Practices; 2.4 Test Compression; 2.4.1 Circuits for Test Stimulus Compression; 2.4.1.1 Linear-Decompression-Based Schemes; 2.4.1.2 Broadcast-Scan-Based Schemes; 2.4.1.3 Comparison; 2.4.2 Circuits for Test Response Compaction; 2.4.2.1 Space Compaction; 2.4.2.2 Time Compaction 2.4.2.3 Mixed Time and Space Compaction2.4.3 Low-Power Test Compression Architectures; 2.4.4 Industry Practices; 2.5 Random-Access Scan Design; 2.5.1 Random-Access Scan Architectures; 2.5.1.1 Progressive Random-Access Scan Design; 2.5.1.2 Shift-Addressable Random-Access Scan Design; 2.5.2 Test Compression RAS Architectures; 2.5.3 At-Speed RAS Architectures; 2.6 Concluding Remarks; 2.7 Exercises; Acknowledgments; References; Chapter 3 Fault-Tolerant Design; 3.1 Introduction; 3.2 Fundamentals of Fault Tolerance; 3.2.1 Reliability; 3.2.2 Mean Time to Failure (MTTF); 3.2.3 Maintainability 3.2.4 Availability |
| Record Nr. | UNINA-9910820907503321 |
| Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Systems on Silicon - Design, Test, and Application: Proceedings of the Eleventh VLSI Test Symposium
| Systems on Silicon - Design, Test, and Application: Proceedings of the Eleventh VLSI Test Symposium |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society Press, 1993 |
| Descrizione fisica | 1 online resource (384 pages) |
| Disciplina | 621 |
| Soggetto topico | Integrated circuits - Very large scale integration - Testing |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996206164603316 |
| [Place of publication not identified], : IEEE Computer Society Press, 1993 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Systems on Silicon - Design, Test, and Application: Proceedings of the Eleventh VLSI Test Symposium
| Systems on Silicon - Design, Test, and Application: Proceedings of the Eleventh VLSI Test Symposium |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society Press, 1993 |
| Descrizione fisica | 1 online resource (384 pages) |
| Disciplina | 621 |
| Soggetto topico | Integrated circuits - Very large scale integration - Testing |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910872672303321 |
| [Place of publication not identified], : IEEE Computer Society Press, 1993 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
VLSI test principles and architectures [[electronic resource] ] : design for testability / / edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen
| VLSI test principles and architectures [[electronic resource] ] : design for testability / / edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006 |
| Descrizione fisica | 1 online resource (809 p.) |
| Disciplina | 621.39/5 |
| Altri autori (Persone) |
WangLaung-Terng
WuCheng-Wen, EE Ph. D. WenXiaoqing |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Integrated circuits - Very large scale integration - Testing
Integrated circuits - Very large scale integration - Design |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-280-96684-X
9786610966844 0-08-047479-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front cover; Title page; Copyright page; Table of contents; Preface; In the Classroom; Acknowledgments; Contributors; About the Editors; 1 Introduction; Importance of Testing; Testing During the VLSI Lifecycle; VLSI Development Process; Design Verification; Yield and Reject Rate; Electronic System Manufacturing Process; System-Level Operation; Challenges in VLSI Testing; Test Generation; Fault Models; Stuck-At Faults; Transistor Faults; Open and Short Faults; Delay Faults and Crosstalk; Pattern Sensitivity and Coupling Faults; Analog Fault Models; Levels of Abstraction in VLSI Testing
Register-Transfer Level and Behavioral Level Gate Level; Switch Level; Physical Level; Historical Review of VLSI Test Technology; Automatic Test Equipment; Automatic Test Pattern Generation; Fault Simulation; Digital Circuit Testing; Analog and Mixed-Signal Circuit Testing; Design for Testability; Board Testing; Boundary Scan Testing; Concluding Remarks; Exercises; Acknowledgments; References; 2 Design for Testability; Introduction; Testability Analysis; SCOAP Testability Analysis; Combinational Controllability and Observability Calculation Sequential Controllability and Observability Calculation Probability-Based Testability Analysis; Simulation-Based Testability Analysis; RTL Testability Analysis; Design for Testability Basics; Ad Hoc Approach; Test Point Insertion; Structured Approach; Scan Cell Designs; Muxed-D Scan Cell; Clocked-Scan Cell; LSSD Scan Cell; Scan Architectures; Full-Scan Design; Muxed-D Full-Scan Design; Clocked Full-Scan Design; LSSD Full-Scan Design; Partial-Scan Design; Random-Access Scan Design; Scan Design Rules; Tristate Buses; Bidirectional I/O Ports; Gated Clocks; Derived Clocks Combinational Feedback Loops Asynchronous Set/Reset Signals; Scan Design Flow; Scan Design Rule Checking and Repair; Scan Synthesis; Scan Configuration; Scan Replacement; Scan Reordering; Scan Stitching; Scan Extraction; Scan Verification; Verifying the Scan Shift Operation; Verifying the Scan Capture Operation; Scan Design Costs; Special-Purpose Scan Designs; Enhanced Scan; Snapshot Scan; Error-Resilient Scan; RTL Design for Testability; RTL Scan Design Rule Checking and Repair; RTL Scan Synthesis; RTL Scan Extraction and Scan Verification; Concluding Remarks; Exercises; Acknowledgments References 3 Logic and Fault Simulation; Introduction; Logic Simulation for Design Verification; Fault Simulation for Test and Diagnosis; Simulation Models; Gate-Level Network; Sequential Circuits; Logic Symbols; Unknown State u; High-Impedance State Z; Intermediate Logic States; Logic Element Evaluation; Truth Tables; Input Scanning; Input Counting; Parallel Gate Evaluation; Timing Models; Transport Delay; Inertial Delay; Wire Delay; Functional Element Delay Model; Logic Simulation; Compiled-Code Simulation; Logic Optimization; Logic Levelization; Code Generation; Event-Driven Simulation Nominal-Delay Event-Driven Simulation |
| Record Nr. | UNINA-9910458608703321 |
| Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
