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Mixed analog-digital VLSI devices and technology [[electronic resource] /] / Yannis Tsividis
| Mixed analog-digital VLSI devices and technology [[electronic resource] /] / Yannis Tsividis |
| Autore | Tsividis Yannis |
| Pubbl/distr/stampa | Singapore ; ; River Edge, N.J., : World Scientific, c2002 |
| Descrizione fisica | x, 284 p. : ill |
| Disciplina | 621.39/5 |
| Soggetto topico |
Integrated circuits - Very large scale integration - Design and construction
Integrated circuits - Very large scale integration - Mathematical models Mixed signal circuits |
| ISBN | 981-270-384-5 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | ch. 1. Introduction: mixed analog-digital chips. 1.1. The role and place of modern mixed analog-digital chips. 1.2. Advantages of mixing analog and digital circuits on the same chip. 1.3. Applications of MAD chips. 1.4. Obstacles in the design of MAD chips. 1.5. The aim and contents of this book -- ch. 2. The MOSFET: introduction and qualitative view. 2.1. Introduction. 2.2. MOS transistor structure. 2.3. Assumptions about terminal voltages, currents, and temperature. 2.4. A qualitative description of MOSFET operation. 2.5. A fluid dynamical analog. 2.6. Complete set of characteristics. 2.7. Form of functional [symbol] dependence: practical limits for regions of inversion. 2.8. Factors affecting the extrapolated threshold voltage. 2.9. Other factors affecting the drain current -- ch. 3. MOSFET DC modeling. 3.1. Introduction. 3.2. DC model for weak and for strong inversion. 3.3. Drain versus source. 3.4. Symmetric models. 3.5. General models and moderate inversion. 3.6. Mobility dependence on gate and substrate bias. 3.7. Temperature effects. 3.8. Small-dimension effects. 3.9. Breakdown. 3.10. The pMOS transistor. 3.11. Device symbols. 3.12. Model accuracy, parameter extraction, and computer simulation -- ch. 4. MOSFET small-signal modeling. 4.1. Introduction. 4.2. Small-signal conductance parameters. 4.3. Expressions for small-signal conductance parameters in weak and in strong inversion. 4.4. Capacitance parameters. 4.5. Intrinsic cutoff frequency and limits of model validity. 4.6. The transistor at very high frequencies. 4.7. Noise. 4.8. General models and moderate inversion. 4.9. Parameter extraction for accurate small-signal modeling. 4.10. Requirements for good CAD models -- ch. 5. Technology and available circuit components. 5.1. Introduction. 5.2. The n-well CMOS process. 5.3. BiCMOS processes. 5.4. Other silicon processes. 5.5. Sensors. 5.6. Trimming. 5.7. Tolerance and matching of electrical parameters. 5.8. Chip size and yield. 5.9. The influence of pads and package -- ch. 6. Layout. 6.1. Introduction. 6.2. Relation of fabricated transistors to layout. 6.3. Transistor geometry and layout. 6.4. Layout for device matching and precision parameter ratios. 6.5. Layout for interference reduction. 6.6. Integrated-circuit design. |
| Record Nr. | UNINA-9910778263203321 |
Tsividis Yannis
|
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| Singapore ; ; River Edge, N.J., : World Scientific, c2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Mixed analog-digital VLSI devices and technology [[electronic resource] /] / Yannis Tsividis
| Mixed analog-digital VLSI devices and technology [[electronic resource] /] / Yannis Tsividis |
| Autore | Tsividis Yannis |
| Pubbl/distr/stampa | Singapore ; ; River Edge, N.J., : World Scientific, c2002 |
| Descrizione fisica | x, 284 p. : ill |
| Disciplina | 621.39/5 |
| Soggetto topico |
Integrated circuits - Very large scale integration - Design and construction
Integrated circuits - Very large scale integration - Mathematical models Mixed signal circuits |
| ISBN | 981-270-384-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | ch. 1. Introduction: mixed analog-digital chips. 1.1. The role and place of modern mixed analog-digital chips. 1.2. Advantages of mixing analog and digital circuits on the same chip. 1.3. Applications of MAD chips. 1.4. Obstacles in the design of MAD chips. 1.5. The aim and contents of this book -- ch. 2. The MOSFET: introduction and qualitative view. 2.1. Introduction. 2.2. MOS transistor structure. 2.3. Assumptions about terminal voltages, currents, and temperature. 2.4. A qualitative description of MOSFET operation. 2.5. A fluid dynamical analog. 2.6. Complete set of characteristics. 2.7. Form of functional [symbol] dependence: practical limits for regions of inversion. 2.8. Factors affecting the extrapolated threshold voltage. 2.9. Other factors affecting the drain current -- ch. 3. MOSFET DC modeling. 3.1. Introduction. 3.2. DC model for weak and for strong inversion. 3.3. Drain versus source. 3.4. Symmetric models. 3.5. General models and moderate inversion. 3.6. Mobility dependence on gate and substrate bias. 3.7. Temperature effects. 3.8. Small-dimension effects. 3.9. Breakdown. 3.10. The pMOS transistor. 3.11. Device symbols. 3.12. Model accuracy, parameter extraction, and computer simulation -- ch. 4. MOSFET small-signal modeling. 4.1. Introduction. 4.2. Small-signal conductance parameters. 4.3. Expressions for small-signal conductance parameters in weak and in strong inversion. 4.4. Capacitance parameters. 4.5. Intrinsic cutoff frequency and limits of model validity. 4.6. The transistor at very high frequencies. 4.7. Noise. 4.8. General models and moderate inversion. 4.9. Parameter extraction for accurate small-signal modeling. 4.10. Requirements for good CAD models -- ch. 5. Technology and available circuit components. 5.1. Introduction. 5.2. The n-well CMOS process. 5.3. BiCMOS processes. 5.4. Other silicon processes. 5.5. Sensors. 5.6. Trimming. 5.7. Tolerance and matching of electrical parameters. 5.8. Chip size and yield. 5.9. The influence of pads and package -- ch. 6. Layout. 6.1. Introduction. 6.2. Relation of fabricated transistors to layout. 6.3. Transistor geometry and layout. 6.4. Layout for device matching and precision parameter ratios. 6.5. Layout for interference reduction. 6.6. Integrated-circuit design. |
| Record Nr. | UNINA-9910813214303321 |
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Tsividis Yannis
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| Singapore ; ; River Edge, N.J., : World Scientific, c2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Nanoscale VLSI : devices, circuits and applications / / Rohit Dhiman, Rajeevan Chandel
| Nanoscale VLSI : devices, circuits and applications / / Rohit Dhiman, Rajeevan Chandel |
| Edizione | [1st ed. 2020.] |
| Pubbl/distr/stampa | Gateway East, Singapore : , : Springer, , [2020] |
| Descrizione fisica | 1 online resource (XIII, 319 p. 208 illus., 133 illus. in color.) |
| Disciplina | 621.38173 |
| Collana | Energy Systems in Electrical Engineering |
| Soggetto topico |
Electronic circuits
Integrated circuits - Very large scale integration - Design and construction Integrated circuits |
| ISBN | 981-15-7937-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Orthogonally Controllable VQO for Low Voltage Applications -- Design Techniques for Low Power Integrated Circuits -- Gallium Nitride – Emerging Future Technology for Low Power Nanoscale IC Design -- Power and Area Efficient Architectural Design. . |
| Record Nr. | UNINA-9910423653803321 |
| Gateway East, Singapore : , : Springer, , [2020] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Power Distribution Network Design for VLSI
| Power Distribution Network Design for VLSI |
| Autore | Zhu Qing |
| Pubbl/distr/stampa | [Place of publication not identified], : Wiley Interscience Imprint, 2004 |
| Descrizione fisica | 1 online resource (211 pages) |
| Disciplina | 621.395 |
| Soggetto topico |
Integrated circuits - Very large scale integration - Design and construction
Electric power distribution |
| ISBN |
1-280-55675-7
9786610556755 0-470-35365-1 0-471-66029-9 0-471-66030-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Preface. -- 1. Introduction. -- 2. Design Perspectives. -- 3. Electromigration. -- 4. IR Voltage Drop. -- 5. Power Grid Analysis. -- 6. Microprocessor Design Examples. -- 7. Package and I/O Design for Power Delivery. -- Glossary. -- References. -- Index. |
| Record Nr. | UNINA-9910831100803321 |
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Zhu Qing
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| [Place of publication not identified], : Wiley Interscience Imprint, 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Power Distribution Network Design for VLSI
| Power Distribution Network Design for VLSI |
| Autore | Zhu Qing |
| Pubbl/distr/stampa | [Place of publication not identified], : Wiley Interscience Imprint, 2004 |
| Descrizione fisica | 1 online resource (211 pages) |
| Disciplina | 621.395 |
| Soggetto topico |
Integrated circuits - Very large scale integration - Design and construction
Electric power distribution |
| ISBN |
1-280-55675-7
9786610556755 0-470-35365-1 0-471-66029-9 0-471-66030-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Preface. -- 1. Introduction. -- 2. Design Perspectives. -- 3. Electromigration. -- 4. IR Voltage Drop. -- 5. Power Grid Analysis. -- 6. Microprocessor Design Examples. -- 7. Package and I/O Design for Power Delivery. -- Glossary. -- References. -- Index. |
| Record Nr. | UNINA-9910841491703321 |
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Zhu Qing
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||
| [Place of publication not identified], : Wiley Interscience Imprint, 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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A practical approach to VLSI System on Chip (SoC) design : a comprehensive guide / / Veena S. Chakravarthi
| A practical approach to VLSI System on Chip (SoC) design : a comprehensive guide / / Veena S. Chakravarthi |
| Autore | Chakravarthi Veena S. |
| Edizione | [Second edition.] |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer International Publishing, , [2022] |
| Descrizione fisica | 1 online resource (355 pages) : illustrations |
| Disciplina | 621.395 |
| Soggetto topico |
Integrated circuits - Very large scale integration - Design and construction
Systems on a chip |
| ISBN |
9783031183638
9783031183621 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Foreword to the First Edition by Faraj Aalaei -- Foreword to the First Edition by Ashok Soota -- Foreword to the First Edition by Walden C. Rhines -- Preface to the Second Edition -- Praise for the First Edition -- Preface to the First Edition -- About the Book -- Why read this book? -- What Problems Does It Solve? -- Who is the audience? -- What are the prerequisites to reading this book? -- Why become a VLSI designer? -- Contents -- Abbreviations -- Chapter 1: Introduction -- 1.1 Introduction to CMOS VLSI -- 1.2 Application Areas of SoC -- 1.3 Trends in VLSI -- 1.4 System on Chip Complexity -- 1.5 Integration Trend from Circuit to System on Chip -- 1.6 Speed of Operation -- 1.7 Die Size -- 1.8 Design Methodology -- 1.9 SoC Design and Development -- 1.10 Skill Set Required -- 1.11 EDA Environment -- 1.12 Challenges in All -- Reference -- Chapter 2: System on Chip (SoC) Design -- 2.1 Part 1 -- 2.1.1 System on Chip (SoC) -- 2.2 Constituents of SoC -- 2.2.1 Processor Subsystem Cores -- 2.3 Application-Specific Processors -- 2.4 Control Processors -- 2.5 Digital Signal Processors -- 2.6 Vector Processors -- 2.6.1 Embedded Memory Core -- 2.6.2 Analog Cores -- 2.6.3 Interface Cores -- 2.6.4 On-Chip Clock Generators, PLLs, and Sensors -- 2.7 Part 2 -- 2.7.1 SoC Development Life Cycle -- 2.8 SoC Design Requirements -- 2.9 Design Strategy -- 2.10 SoC Design Planning -- 2.11 System Modeling -- 2.12 System Module Development Feasibility Study -- 2.13 IP Design Decisions -- 2.14 Verification IPs -- 2.15 Target Technology Decision -- 2.16 Development Plan -- 2.17 EDA Tool Plan -- 2.18 Design Center Infrastructure -- 2.19 Computational Servers -- 2.20 Filers -- 2.21 Workstations -- 2.22 Backup Servers -- 2.23 Source Control Server -- 2.24 Firewalls -- 2.25 Resource Planning -- 2.26 SoC Design Flow -- 2.26.1 SoC Chip High-Level Design Methodology.
2.26.2 Digital SoC Core Development Flow -- 2.26.3 Processor Subsystem Core Design -- 2.26.4 SoC Integrated Design Flow -- 2.27 EVM Design Development Flow -- 2.28 Software Development Flow -- 2.29 Product Integration Flow -- Chapter 3: SoC Constituents -- 3.1 SoC Constituents -- 3.1.1 Embedded Processor Subsystem for System on Chip -- Choice of Embedded Processors for SoC -- Embedded General-Purpose RISC Processors -- 3.1.2 DSP Processors -- 3.2 Issues of Hw-Sw Co-Design -- 3.2.1 Processor Subsystems -- 3.2.2 Processor Configuration Tools -- 3.2.3 Processor Development Boards -- 3.3 Embedded Memories -- 3.3.1 Types of Memories -- 3.3.2 Choice of Memories -- 3.3.3 Memory Compiler and Compiled Memories -- 3.4 Protocol Blocks -- 3.5 Mixed Signal Blocks -- 3.6 Radio Frequency (RF) Control Blocks -- 3.7 Analog Blocks -- 3.8 Third-Party IP Cores -- 3.9 System Software -- 3.9.1 OSI System Model -- Physical Layer (Layer 1) -- Data Link Layer (Layer 2) -- Network Layer (Layer 3) -- Transport Layer (Layer 4) -- Session Layer (Layer 5) -- Presentation Layer (Layer 6) -- Application Layer (Layer 7) -- 3.10 GAMP Classification of Software -- 3.10.1 Hardware -- 3.10.2 Device Driver -- 3.10.3 Firmware -- 3.10.4 Middleware -- 3.10.5 Software -- 3.10.6 Cloud -- 3.11 Design-Specific Blocks -- Chapter 4: VLSI Logic Design and HDL -- 4.1 SoC Design Concepts -- 4.1.1 Logic Design Fundamentals -- 4.1.2 System Clock and Clock Domains -- 4.1.3 Asynchronous and Synchronous Resets -- Metastability -- Standard Cells and Compiled Logic Blocks -- Hard and Soft Macros -- Data Buffers and Buffer Managers -- Design Assertions -- 4.1.4 Synchronous Sequential Functional Blocks -- 4.2 Asynchronous Circuits -- 4.3 Speed Matching -- 4.4 Network on Chip Architecture -- 4.5 Hardware Accelerator -- 4.6 Hardware Description Languages (HDL) -- 4.7 Behavioral Modelling of the Hardware System. 4.8 Dataflow Modeling of the Hardware System -- 4.9 Structural Modeling of the Hardware System -- 4.10 Input-Output Pad Instantiation -- 4.10.1 Power Ground Corner Pad Instantiation (Fig. 4.17) -- Chapter 5: Synthesis and Static Timing Analysis (STA) -- 5.1 Part 1: SoC Synthesis -- 5.1.1 Set Synthesis Environment -- Read Library -- Read HDL Design Files -- Elaborate the Design Files -- Read Design Constraints -- Optimization Constraint -- Synthesis -- Analyze -- Generate Reports -- 5.1.2 SoC Design Constraints -- 5.2 Design Rule Constraints -- 5.3 SoC Design Synthesis -- 5.4 Low-Power Synthesis -- 5.4.1 Introduction to Low-Power SoCs -- 5.4.2 Universal Power Format (UPF) -- 5.5 Reports -- 5.5.1 Gate Level Netlist Verification -- 5.6 Part 2: Static Timing Analysis (STA) -- 5.7 Timing Definition -- 5.8 Timing Delay Calculation Concepts -- 5.9 Timing Analysis -- 5.10 Modeling Process, Voltage, and Temperature Variations -- 5.10.1 Equivalent Cells -- 5.11 Timing and Design Constraints -- 5.12 Organizing Paths to Groups -- 5.13 Design Corners -- 5.14 Challenges of STA During SoC Design -- Chapter 6: SoC Design for Testability (DFT) -- 6.1 Need for Testability -- 6.2 Guidelines for SoC Design for Testability -- 6.3 DFT Logic Insertion Techniques -- 6.3.1 Scan Insertion -- 6.3.2 Boundary Scan -- 6.4 Boundary Scan Insertion Flow -- 6.4.1 Memory Built-in Self-Test (MBIST) -- 6.4.2 Stuck-at Faults -- 6.4.3 Transition Faults -- 6.4.4 Coupling Faults -- 6.4.5 Neighborhood Pattern-Sensitive Faults -- 6.4.6 MBIST Algorithms -- 6.5 ROM Test Algorithm -- 6.6 Power Aware Test Module (PATM) Insertion -- 6.6.1 Logic BIST Insertion -- 6.6.2 Writing out DFT SDC -- 6.6.3 Compression Insertion -- 6.7 On-SoC Clock Generation (OSCG) Insertion -- 6.8 Challenges in SoC DFT -- 6.9 Memory Clustering -- 6.10 DFT Simulations -- 6.11 ATPG Pattern Generation. 6.12 Automatic Test Equipment Testing (ATE Testing) -- Chapter 7: SoC Design Verification -- 7.1 Importance of Verification -- 7.2 Verification Plan and Strategies -- 7.3 Verification Plan -- 7.4 Functional Verification -- 7.5 Verification Methods -- 7.5.1 Black Box Verification -- 7.5.2 White Box Verification -- 7.5.3 Gray Box Verification -- 7.6 Design for Verification -- 7.7 Verification Example -- 7.8 Verification Tools -- 7.9 Verification Language -- 7.10 Automation Scripts -- 7.11 Design for Verification -- 7.12 Assertions in Verification -- 7.13 Verification Reuse and Verification IPs -- 7.14 Universal Verification Methodology (UVM) -- 7.15 Bug and Debug -- 7.16 Bug Tracking Workflow -- 7.17 Formal Verification -- 7.18 FPGA Validation -- 7.19 Validation on Development Boards -- Chapter 8: SoC Physical Design -- 8.1 Re-convergent Model of VLSI SoC Design -- 8.2 File Formats -- 8.3 SoC Physical Design -- 8.4 Physical Design Theory -- 8.5 Stick Diagrams -- 8.6 Physical Design Setup and Floor Plan -- 8.7 Floor Planning -- 8.8 SoC Power Plan -- 8.9 Two-Step Synthesis of SoC Design -- 8.10 Placement -- 8.11 Physical Design Constraints -- 8.12 Clock Tree Synthesis (CTS) -- 8.13 Routing -- 8.14 ECO Implementation -- 8.15 Advanced Physical Design of SOCs -- 8.15.1 For Low-Power Consumption -- 8.15.2 For Advanced Technology -- 8.15.3 High Performance -- 8.16 Photolithography and Mask Pattern -- Chapter 9: SoC Physical Design Verification -- 9.1 SoC Design Verification by Formal Verification -- 9.2 Model Checking -- 9.3 Logic Equivalence Check (LEC) -- 9.4 Static Timing Analysis (STA) -- 9.5 ECO Checks -- 9.6 Electromigration (EM) -- 9.7 Simultaneous Switching Noise (SSN) -- 9.8 Electrostatic Discharge (ESD) Protection -- 9.9 IR and Cross Talk Analysis -- 9.10 Layout Verse Schematic (LVS) -- 9.11 Gate Level Simulation -- 9.12 Electrical Rule Check (ERC). 9.13 DRC Rule Check -- 9.14 Design Rule Violation (DRV) Checks -- 9.15 Design Tape Out -- Chapter 10: SoC Packaging -- 10.1 Introduction to VLSI SoC Packaging -- 10.2 Classification of Packages -- 10.3 Criteria for Selection of Packages -- 10.4 Package Components -- 10.5 Package Assembly Flow -- 10.6 Packaging Technology -- 10.7 Flip-Chip Packages -- 10.8 Typical Packages -- 10.9 Package Performance -- 10.10 System Integration -- 10.11 Packaging Trends -- 10.11.1 Stacked Die Integration -- 10.11.2 3D Integration Schemes -- Chapter 11: Reference Designs -- 11.1 Design for Trial -- 11.2 Prerequisites -- 11.3 User Guidelines -- 11.4 Design Directory -- 11.5 Part 1 -- 11.6 Design Examples -- 11.7 Part II -- 11.7.1 Design Flow -- 11.7.2 Logic Equivalence Check (LEC) -- 11.8 Part III -- 11.8.1 MINI-SoC Design -- IO Diagram -- Index. |
| Record Nr. | UNISA-996503565003316 |
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Chakravarthi Veena S.
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| Cham, Switzerland : , : Springer International Publishing, , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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A practical approach to VLSI System on Chip (SoC) design : a comprehensive guide / / Veena S. Chakravarthi
| A practical approach to VLSI System on Chip (SoC) design : a comprehensive guide / / Veena S. Chakravarthi |
| Autore | Chakravarthi Veena S. |
| Edizione | [Second edition.] |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer International Publishing, , [2022] |
| Descrizione fisica | 1 online resource (355 pages) : illustrations |
| Disciplina | 621.395 |
| Soggetto topico |
Integrated circuits - Very large scale integration - Design and construction
Systems on a chip |
| ISBN |
9783031183638
9783031183621 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Foreword to the First Edition by Faraj Aalaei -- Foreword to the First Edition by Ashok Soota -- Foreword to the First Edition by Walden C. Rhines -- Preface to the Second Edition -- Praise for the First Edition -- Preface to the First Edition -- About the Book -- Why read this book? -- What Problems Does It Solve? -- Who is the audience? -- What are the prerequisites to reading this book? -- Why become a VLSI designer? -- Contents -- Abbreviations -- Chapter 1: Introduction -- 1.1 Introduction to CMOS VLSI -- 1.2 Application Areas of SoC -- 1.3 Trends in VLSI -- 1.4 System on Chip Complexity -- 1.5 Integration Trend from Circuit to System on Chip -- 1.6 Speed of Operation -- 1.7 Die Size -- 1.8 Design Methodology -- 1.9 SoC Design and Development -- 1.10 Skill Set Required -- 1.11 EDA Environment -- 1.12 Challenges in All -- Reference -- Chapter 2: System on Chip (SoC) Design -- 2.1 Part 1 -- 2.1.1 System on Chip (SoC) -- 2.2 Constituents of SoC -- 2.2.1 Processor Subsystem Cores -- 2.3 Application-Specific Processors -- 2.4 Control Processors -- 2.5 Digital Signal Processors -- 2.6 Vector Processors -- 2.6.1 Embedded Memory Core -- 2.6.2 Analog Cores -- 2.6.3 Interface Cores -- 2.6.4 On-Chip Clock Generators, PLLs, and Sensors -- 2.7 Part 2 -- 2.7.1 SoC Development Life Cycle -- 2.8 SoC Design Requirements -- 2.9 Design Strategy -- 2.10 SoC Design Planning -- 2.11 System Modeling -- 2.12 System Module Development Feasibility Study -- 2.13 IP Design Decisions -- 2.14 Verification IPs -- 2.15 Target Technology Decision -- 2.16 Development Plan -- 2.17 EDA Tool Plan -- 2.18 Design Center Infrastructure -- 2.19 Computational Servers -- 2.20 Filers -- 2.21 Workstations -- 2.22 Backup Servers -- 2.23 Source Control Server -- 2.24 Firewalls -- 2.25 Resource Planning -- 2.26 SoC Design Flow -- 2.26.1 SoC Chip High-Level Design Methodology.
2.26.2 Digital SoC Core Development Flow -- 2.26.3 Processor Subsystem Core Design -- 2.26.4 SoC Integrated Design Flow -- 2.27 EVM Design Development Flow -- 2.28 Software Development Flow -- 2.29 Product Integration Flow -- Chapter 3: SoC Constituents -- 3.1 SoC Constituents -- 3.1.1 Embedded Processor Subsystem for System on Chip -- Choice of Embedded Processors for SoC -- Embedded General-Purpose RISC Processors -- 3.1.2 DSP Processors -- 3.2 Issues of Hw-Sw Co-Design -- 3.2.1 Processor Subsystems -- 3.2.2 Processor Configuration Tools -- 3.2.3 Processor Development Boards -- 3.3 Embedded Memories -- 3.3.1 Types of Memories -- 3.3.2 Choice of Memories -- 3.3.3 Memory Compiler and Compiled Memories -- 3.4 Protocol Blocks -- 3.5 Mixed Signal Blocks -- 3.6 Radio Frequency (RF) Control Blocks -- 3.7 Analog Blocks -- 3.8 Third-Party IP Cores -- 3.9 System Software -- 3.9.1 OSI System Model -- Physical Layer (Layer 1) -- Data Link Layer (Layer 2) -- Network Layer (Layer 3) -- Transport Layer (Layer 4) -- Session Layer (Layer 5) -- Presentation Layer (Layer 6) -- Application Layer (Layer 7) -- 3.10 GAMP Classification of Software -- 3.10.1 Hardware -- 3.10.2 Device Driver -- 3.10.3 Firmware -- 3.10.4 Middleware -- 3.10.5 Software -- 3.10.6 Cloud -- 3.11 Design-Specific Blocks -- Chapter 4: VLSI Logic Design and HDL -- 4.1 SoC Design Concepts -- 4.1.1 Logic Design Fundamentals -- 4.1.2 System Clock and Clock Domains -- 4.1.3 Asynchronous and Synchronous Resets -- Metastability -- Standard Cells and Compiled Logic Blocks -- Hard and Soft Macros -- Data Buffers and Buffer Managers -- Design Assertions -- 4.1.4 Synchronous Sequential Functional Blocks -- 4.2 Asynchronous Circuits -- 4.3 Speed Matching -- 4.4 Network on Chip Architecture -- 4.5 Hardware Accelerator -- 4.6 Hardware Description Languages (HDL) -- 4.7 Behavioral Modelling of the Hardware System. 4.8 Dataflow Modeling of the Hardware System -- 4.9 Structural Modeling of the Hardware System -- 4.10 Input-Output Pad Instantiation -- 4.10.1 Power Ground Corner Pad Instantiation (Fig. 4.17) -- Chapter 5: Synthesis and Static Timing Analysis (STA) -- 5.1 Part 1: SoC Synthesis -- 5.1.1 Set Synthesis Environment -- Read Library -- Read HDL Design Files -- Elaborate the Design Files -- Read Design Constraints -- Optimization Constraint -- Synthesis -- Analyze -- Generate Reports -- 5.1.2 SoC Design Constraints -- 5.2 Design Rule Constraints -- 5.3 SoC Design Synthesis -- 5.4 Low-Power Synthesis -- 5.4.1 Introduction to Low-Power SoCs -- 5.4.2 Universal Power Format (UPF) -- 5.5 Reports -- 5.5.1 Gate Level Netlist Verification -- 5.6 Part 2: Static Timing Analysis (STA) -- 5.7 Timing Definition -- 5.8 Timing Delay Calculation Concepts -- 5.9 Timing Analysis -- 5.10 Modeling Process, Voltage, and Temperature Variations -- 5.10.1 Equivalent Cells -- 5.11 Timing and Design Constraints -- 5.12 Organizing Paths to Groups -- 5.13 Design Corners -- 5.14 Challenges of STA During SoC Design -- Chapter 6: SoC Design for Testability (DFT) -- 6.1 Need for Testability -- 6.2 Guidelines for SoC Design for Testability -- 6.3 DFT Logic Insertion Techniques -- 6.3.1 Scan Insertion -- 6.3.2 Boundary Scan -- 6.4 Boundary Scan Insertion Flow -- 6.4.1 Memory Built-in Self-Test (MBIST) -- 6.4.2 Stuck-at Faults -- 6.4.3 Transition Faults -- 6.4.4 Coupling Faults -- 6.4.5 Neighborhood Pattern-Sensitive Faults -- 6.4.6 MBIST Algorithms -- 6.5 ROM Test Algorithm -- 6.6 Power Aware Test Module (PATM) Insertion -- 6.6.1 Logic BIST Insertion -- 6.6.2 Writing out DFT SDC -- 6.6.3 Compression Insertion -- 6.7 On-SoC Clock Generation (OSCG) Insertion -- 6.8 Challenges in SoC DFT -- 6.9 Memory Clustering -- 6.10 DFT Simulations -- 6.11 ATPG Pattern Generation. 6.12 Automatic Test Equipment Testing (ATE Testing) -- Chapter 7: SoC Design Verification -- 7.1 Importance of Verification -- 7.2 Verification Plan and Strategies -- 7.3 Verification Plan -- 7.4 Functional Verification -- 7.5 Verification Methods -- 7.5.1 Black Box Verification -- 7.5.2 White Box Verification -- 7.5.3 Gray Box Verification -- 7.6 Design for Verification -- 7.7 Verification Example -- 7.8 Verification Tools -- 7.9 Verification Language -- 7.10 Automation Scripts -- 7.11 Design for Verification -- 7.12 Assertions in Verification -- 7.13 Verification Reuse and Verification IPs -- 7.14 Universal Verification Methodology (UVM) -- 7.15 Bug and Debug -- 7.16 Bug Tracking Workflow -- 7.17 Formal Verification -- 7.18 FPGA Validation -- 7.19 Validation on Development Boards -- Chapter 8: SoC Physical Design -- 8.1 Re-convergent Model of VLSI SoC Design -- 8.2 File Formats -- 8.3 SoC Physical Design -- 8.4 Physical Design Theory -- 8.5 Stick Diagrams -- 8.6 Physical Design Setup and Floor Plan -- 8.7 Floor Planning -- 8.8 SoC Power Plan -- 8.9 Two-Step Synthesis of SoC Design -- 8.10 Placement -- 8.11 Physical Design Constraints -- 8.12 Clock Tree Synthesis (CTS) -- 8.13 Routing -- 8.14 ECO Implementation -- 8.15 Advanced Physical Design of SOCs -- 8.15.1 For Low-Power Consumption -- 8.15.2 For Advanced Technology -- 8.15.3 High Performance -- 8.16 Photolithography and Mask Pattern -- Chapter 9: SoC Physical Design Verification -- 9.1 SoC Design Verification by Formal Verification -- 9.2 Model Checking -- 9.3 Logic Equivalence Check (LEC) -- 9.4 Static Timing Analysis (STA) -- 9.5 ECO Checks -- 9.6 Electromigration (EM) -- 9.7 Simultaneous Switching Noise (SSN) -- 9.8 Electrostatic Discharge (ESD) Protection -- 9.9 IR and Cross Talk Analysis -- 9.10 Layout Verse Schematic (LVS) -- 9.11 Gate Level Simulation -- 9.12 Electrical Rule Check (ERC). 9.13 DRC Rule Check -- 9.14 Design Rule Violation (DRV) Checks -- 9.15 Design Tape Out -- Chapter 10: SoC Packaging -- 10.1 Introduction to VLSI SoC Packaging -- 10.2 Classification of Packages -- 10.3 Criteria for Selection of Packages -- 10.4 Package Components -- 10.5 Package Assembly Flow -- 10.6 Packaging Technology -- 10.7 Flip-Chip Packages -- 10.8 Typical Packages -- 10.9 Package Performance -- 10.10 System Integration -- 10.11 Packaging Trends -- 10.11.1 Stacked Die Integration -- 10.11.2 3D Integration Schemes -- Chapter 11: Reference Designs -- 11.1 Design for Trial -- 11.2 Prerequisites -- 11.3 User Guidelines -- 11.4 Design Directory -- 11.5 Part 1 -- 11.6 Design Examples -- 11.7 Part II -- 11.7.1 Design Flow -- 11.7.2 Logic Equivalence Check (LEC) -- 11.8 Part III -- 11.8.1 MINI-SoC Design -- IO Diagram -- Index. |
| Record Nr. | UNINA-9910635398003321 |
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Chakravarthi Veena S.
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| Cham, Switzerland : , : Springer International Publishing, , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Proceedings : ... IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
| Proceedings : ... IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems |
| Pubbl/distr/stampa | Los Alamitos, California : , : CPS, Conference Publishing Services, IEEE Computer Society, , [2011]- |
| Disciplina | 621 |
| Soggetto topico |
Integrated circuits - Very large scale integration - Design and construction
Integrated circuits - Fault tolerance Nanotechnology Circuits intégrés - Tolérance aux fautes Nanotechnologie |
| Soggetto genere / forma | Conference papers and proceedings. |
| Formato | Materiale a stampa |
| Livello bibliografico | Periodico |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
.. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
DFT .. Proceedings of the ... IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Proceedings of the ... IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) DFTS Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ... IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) ... IEEE International Symposium on |
| Record Nr. | UNISA-996564470003316 |
| Los Alamitos, California : , : CPS, Conference Publishing Services, IEEE Computer Society, , [2011]- | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Proceedings / / IEEE International SOC Conference
| Proceedings / / IEEE International SOC Conference |
| Pubbl/distr/stampa | Piscataway, NJ, : IEEE, ©2003- |
| Descrizione fisica | volumes : illustrations ; ; 28 cm |
| Disciplina | 621.39 |
| Soggetto topico |
Application-specific integrated circuits
Electronic digital computers - Circuits Integrated circuits - Very large scale integration - Design and construction Systems on a chip |
| Soggetto genere / forma |
Conference papers and proceedings.
Periodicals. |
| ISSN | 2164-1706 |
| Formato | Materiale a stampa |
| Livello bibliografico | Periodico |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
Digest of technical papers
Proceedings of the IEEE International SOC Conference IEEE International SOC Conference Systems on Chip Conference |
| Record Nr. | UNINA-9910625190803321 |
| Piscataway, NJ, : IEEE, ©2003- | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Proceedings / / IEEE International SOC Conference
| Proceedings / / IEEE International SOC Conference |
| Pubbl/distr/stampa | Piscataway, NJ, : IEEE, ©2003- |
| Descrizione fisica | volumes : illustrations ; ; 28 cm |
| Disciplina | 621.39 |
| Soggetto topico |
Application-specific integrated circuits
Electronic digital computers - Circuits Integrated circuits - Very large scale integration - Design and construction Systems on a chip |
| Soggetto genere / forma |
Conference papers and proceedings.
Periodicals. |
| ISSN | 2164-1706 |
| Formato | Materiale a stampa |
| Livello bibliografico | Periodico |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
Digest of technical papers
Proceedings of the IEEE International SOC Conference IEEE International SOC Conference Systems on Chip Conference |
| Record Nr. | UNISA-996279266603316 |
| Piscataway, NJ, : IEEE, ©2003- | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
