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The IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems : proceedings : Chicago, Illinois, 7-9 October 2009 / / edited by Dimitris Gizopoulos, Mohammad Tehranipoor, and Spyros Tragoudas ; sponsored by the IEEE Computer Society Technical Committee on Fault-Tolerant Computing, the IEEE Test Technology Technical Council
| The IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems : proceedings : Chicago, Illinois, 7-9 October 2009 / / edited by Dimitris Gizopoulos, Mohammad Tehranipoor, and Spyros Tragoudas ; sponsored by the IEEE Computer Society Technical Committee on Fault-Tolerant Computing, the IEEE Test Technology Technical Council |
| Pubbl/distr/stampa | New York : , : IEEE, , 2009 |
| Descrizione fisica | 1 online resource (xxxi, 455 pages) |
| Soggetto topico |
Fault-tolerant computing
Integrated circuits - Very large scale integration - Design and construction |
| ISBN | 1-5090-7533-X |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996203025203316 |
| New York : , : IEEE, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
The IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems : proceedings : Chicago, Illinois, 7-9 October 2009 / / edited by Dimitris Gizopoulos, Mohammad Tehranipoor, and Spyros Tragoudas ; sponsored by the IEEE Computer Society Technical Committee on Fault-Tolerant Computing, the IEEE Test Technology Technical Council
| The IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems : proceedings : Chicago, Illinois, 7-9 October 2009 / / edited by Dimitris Gizopoulos, Mohammad Tehranipoor, and Spyros Tragoudas ; sponsored by the IEEE Computer Society Technical Committee on Fault-Tolerant Computing, the IEEE Test Technology Technical Council |
| Pubbl/distr/stampa | New York : , : IEEE, , 2009 |
| Descrizione fisica | 1 online resource (xxxi, 455 pages) |
| Soggetto topico |
Fault-tolerant computing
Integrated circuits - Very large scale integration - Design and construction |
| ISBN | 1-5090-7533-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910138783103321 |
| New York : , : IEEE, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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IEEE transactions on very large scale integration (VLSI) systems
| IEEE transactions on very large scale integration (VLSI) systems |
| Pubbl/distr/stampa | New York, NY, : Institute of Electrical and Electronics Engineers, c1993- |
| Disciplina | 621.3 |
| Soggetto topico |
Integrated circuits - Very large scale integration - Design and construction
Circuits intégrés à très grande échelle - Conception et construction |
| ISSN | 1557-9999 |
| Formato | Materiale a stampa |
| Livello bibliografico | Periodico |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996204655303316 |
| New York, NY, : Institute of Electrical and Electronics Engineers, c1993- | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
IEEE transactions on very large scale integration (VLSI) systems
| IEEE transactions on very large scale integration (VLSI) systems |
| Pubbl/distr/stampa | New York, NY, : Institute of Electrical and Electronics Engineers, c1993- |
| Disciplina | 621.3 |
| Soggetto topico |
Integrated circuits - Very large scale integration - Design and construction
Circuits intégrés à très grande échelle - Conception et construction |
| ISSN | 1557-9999 |
| Formato | Materiale a stampa |
| Livello bibliografico | Periodico |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910626005703321 |
| New York, NY, : Institute of Electrical and Electronics Engineers, c1993- | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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ISOCC 2018 : International SoC Design Conference : proceedings of technical papers : November 12-15, 2018, Hotel Inter-Burgo Daegu, Daegu, Korea. / / Institute of Electrical and Electronics Engineers
| ISOCC 2018 : International SoC Design Conference : proceedings of technical papers : November 12-15, 2018, Hotel Inter-Burgo Daegu, Daegu, Korea. / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018 |
| Descrizione fisica | 1 online resource (150 pages) |
| Disciplina | 621 |
| Soggetto topico |
Systems on a chip - Design and construction
Electronic digital computers - Circuits Integrated circuits - Very large scale integration - Design and construction Smart materials |
| ISBN | 1-5386-7960-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910312657803321 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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ISOCC 2018 : International SoC Design Conference : proceedings of technical papers : November 12-15, 2018, Hotel Inter-Burgo Daegu, Daegu, Korea. / / Institute of Electrical and Electronics Engineers
| ISOCC 2018 : International SoC Design Conference : proceedings of technical papers : November 12-15, 2018, Hotel Inter-Burgo Daegu, Daegu, Korea. / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018 |
| Descrizione fisica | 1 online resource (150 pages) |
| Disciplina | 621 |
| Soggetto topico |
Systems on a chip - Design and construction
Electronic digital computers - Circuits Integrated circuits - Very large scale integration - Design and construction Smart materials |
| ISBN | 1-5386-7960-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996577944503316 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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IWJT 2018 : 2018 18th International Workshop on Junction Technology (IWJT) extended abstracts : March 8-9, 2018, Shanghai, China / / Institute of Electrical and Electronics Engineers
| IWJT 2018 : 2018 18th International Workshop on Junction Technology (IWJT) extended abstracts : March 8-9, 2018, Shanghai, China / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018 |
| Descrizione fisica | 1 online resource (278 pages) |
| Disciplina | 621.38152 |
| Soggetto topico |
Semiconductors - Design and construction
Integrated circuits - Very large scale integration - Design and construction |
| ISBN | 1-5386-4513-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996279509703316 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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IWJT 2018 : 2018 18th International Workshop on Junction Technology (IWJT) extended abstracts : March 8-9, 2018, Shanghai, China / / Institute of Electrical and Electronics Engineers
| IWJT 2018 : 2018 18th International Workshop on Junction Technology (IWJT) extended abstracts : March 8-9, 2018, Shanghai, China / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018 |
| Descrizione fisica | 1 online resource (278 pages) |
| Disciplina | 621.38152 |
| Soggetto topico |
Semiconductors - Design and construction
Integrated circuits - Very large scale integration - Design and construction |
| ISBN | 1-5386-4513-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910265257503321 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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MAM '97, abstracts booklet : European Workshop: Materials for Advanced Metallization, Villard-de-Lans, France, March 16-19, 1997 / / Société Française du Vide
| MAM '97, abstracts booklet : European Workshop: Materials for Advanced Metallization, Villard-de-Lans, France, March 16-19, 1997 / / Société Française du Vide |
| Pubbl/distr/stampa | Paris, France : , : Société française du vide, , 1997 |
| Descrizione fisica | 1 online resource (221 pages) : illustrations |
| Disciplina | 621.38152 |
| Soggetto topico |
Semiconductor-metal boundaries
Integrated circuits - Very large scale integration - Design and construction |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996278348003316 |
| Paris, France : , : Société française du vide, , 1997 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Mixed analog-digital VLSI devices and technology [[electronic resource] /] / Yannis Tsividis
| Mixed analog-digital VLSI devices and technology [[electronic resource] /] / Yannis Tsividis |
| Autore | Tsividis Yannis |
| Pubbl/distr/stampa | Singapore ; ; River Edge, N.J., : World Scientific, c2002 |
| Descrizione fisica | x, 284 p. : ill |
| Disciplina | 621.39/5 |
| Soggetto topico |
Integrated circuits - Very large scale integration - Design and construction
Integrated circuits - Very large scale integration - Mathematical models Mixed signal circuits |
| Soggetto genere / forma | Electronic books. |
| ISBN | 981-270-384-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | ch. 1. Introduction: mixed analog-digital chips. 1.1. The role and place of modern mixed analog-digital chips. 1.2. Advantages of mixing analog and digital circuits on the same chip. 1.3. Applications of MAD chips. 1.4. Obstacles in the design of MAD chips. 1.5. The aim and contents of this book -- ch. 2. The MOSFET: introduction and qualitative view. 2.1. Introduction. 2.2. MOS transistor structure. 2.3. Assumptions about terminal voltages, currents, and temperature. 2.4. A qualitative description of MOSFET operation. 2.5. A fluid dynamical analog. 2.6. Complete set of characteristics. 2.7. Form of functional [symbol] dependence: practical limits for regions of inversion. 2.8. Factors affecting the extrapolated threshold voltage. 2.9. Other factors affecting the drain current -- ch. 3. MOSFET DC modeling. 3.1. Introduction. 3.2. DC model for weak and for strong inversion. 3.3. Drain versus source. 3.4. Symmetric models. 3.5. General models and moderate inversion. 3.6. Mobility dependence on gate and substrate bias. 3.7. Temperature effects. 3.8. Small-dimension effects. 3.9. Breakdown. 3.10. The pMOS transistor. 3.11. Device symbols. 3.12. Model accuracy, parameter extraction, and computer simulation -- ch. 4. MOSFET small-signal modeling. 4.1. Introduction. 4.2. Small-signal conductance parameters. 4.3. Expressions for small-signal conductance parameters in weak and in strong inversion. 4.4. Capacitance parameters. 4.5. Intrinsic cutoff frequency and limits of model validity. 4.6. The transistor at very high frequencies. 4.7. Noise. 4.8. General models and moderate inversion. 4.9. Parameter extraction for accurate small-signal modeling. 4.10. Requirements for good CAD models -- ch. 5. Technology and available circuit components. 5.1. Introduction. 5.2. The n-well CMOS process. 5.3. BiCMOS processes. 5.4. Other silicon processes. 5.5. Sensors. 5.6. Trimming. 5.7. Tolerance and matching of electrical parameters. 5.8. Chip size and yield. 5.9. The influence of pads and package -- ch. 6. Layout. 6.1. Introduction. 6.2. Relation of fabricated transistors to layout. 6.3. Transistor geometry and layout. 6.4. Layout for device matching and precision parameter ratios. 6.5. Layout for interference reduction. 6.6. Integrated-circuit design. |
| Record Nr. | UNINA-9910451952803321 |
Tsividis Yannis
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| Singapore ; ; River Edge, N.J., : World Scientific, c2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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