top

  Info

  • Utilizzare la checkbox di selezione a fianco di ciascun documento per attivare le funzionalità di stampa, invio email, download nei formati disponibili del (i) record.

  Info

  • Utilizzare questo link per rimuovere la selezione effettuata.

Biblioteca

MARC Lista (tabellare)
16th International Conference on Information Technology-New Generations (ITNG 2019) [[electronic resource] /] / edited by Shahram Latifi
16th International Conference on Information Technology-New Generations (ITNG 2019) [[electronic resource] /] / edited by Shahram Latifi
Edizione [1st ed. 2019.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019
Descrizione fisica 1 online resource (611 pages)
Disciplina 004
Collana Advances in Intelligent Systems and Computing
Soggetto topico Application software
Signal processing
Image processing
Speech processing systems
Data structures (Computer science)
Input-output equipment (Computers)
Information Systems Applications (incl. Internet)
Signal, Image and Speech Processing
Data Structures and Information Theory
Input/Output and Data Communications
ISBN 3-030-14070-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Networking and Wireless Communications -- Cybersecurity -- Data Mining -- Software Engineering -- High Performance Computing Architectures -- Computer Vision, HCI and Image Processing/Analysis -- Signal Processing, UAVs -- Health, Bioinformatics, Pattern Detection and Optimization -- Education, Applications and Systems -- Short Papers.
Record Nr. UNINA-9910337601303321
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Accelerator Programming Using Directives [[electronic resource] ] : 6th International Workshop, WACCPD 2019, Denver, CO, USA, November 18, 2019, Revised Selected Papers / / edited by Sandra Wienke, Sridutt Bhalachandra
Accelerator Programming Using Directives [[electronic resource] ] : 6th International Workshop, WACCPD 2019, Denver, CO, USA, November 18, 2019, Revised Selected Papers / / edited by Sandra Wienke, Sridutt Bhalachandra
Edizione [1st ed. 2020.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020
Descrizione fisica 1 online resource (170 pages)
Disciplina 005.1
Collana Programming and Software Engineering
Soggetto topico Programming languages (Electronic computers)
Computer organization
Microprogramming 
Input-output equipment (Computers)
Logic design
Programming Languages, Compilers, Interpreters
Computer Systems Organization and Communication Networks
Control Structures and Microprogramming
Input/Output and Data Communications
Logic Design
ISBN 3-030-49943-X
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNINA-9910409662003321
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Accelerator Programming Using Directives [[electronic resource] ] : 6th International Workshop, WACCPD 2019, Denver, CO, USA, November 18, 2019, Revised Selected Papers / / edited by Sandra Wienke, Sridutt Bhalachandra
Accelerator Programming Using Directives [[electronic resource] ] : 6th International Workshop, WACCPD 2019, Denver, CO, USA, November 18, 2019, Revised Selected Papers / / edited by Sandra Wienke, Sridutt Bhalachandra
Edizione [1st ed. 2020.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020
Descrizione fisica 1 online resource (170 pages)
Disciplina 005.1
Collana Programming and Software Engineering
Soggetto topico Programming languages (Electronic computers)
Computer organization
Microprogramming 
Input-output equipment (Computers)
Logic design
Programming Languages, Compilers, Interpreters
Computer Systems Organization and Communication Networks
Control Structures and Microprogramming
Input/Output and Data Communications
Logic Design
ISBN 3-030-49943-X
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNISA-996418304403316
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
Accelerator Programming Using Directives [[electronic resource] ] : 5th International Workshop, WACCPD 2018, Dallas, TX, USA, November 11-17, 2018, Proceedings / / edited by Sunita Chandrasekaran, Guido Juckeland, Sandra Wienke
Accelerator Programming Using Directives [[electronic resource] ] : 5th International Workshop, WACCPD 2018, Dallas, TX, USA, November 11-17, 2018, Proceedings / / edited by Sunita Chandrasekaran, Guido Juckeland, Sandra Wienke
Edizione [1st ed. 2019.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019
Descrizione fisica 1 online resource (IX, 137 p. 61 illus., 43 illus. in color.)
Disciplina 001.642
Collana Programming and Software Engineering
Soggetto topico Programming languages (Electronic computers)
Logic design
Input-output equipment (Computers)
Microprogramming 
Computer organization
Programming Languages, Compilers, Interpreters
Logic Design
Input/Output and Data Communications
Control Structures and Microprogramming
Computer Systems Organization and Communication Networks
ISBN 3-030-12274-3
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNINA-9910337577103321
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Accelerator Programming Using Directives [[electronic resource] ] : 5th International Workshop, WACCPD 2018, Dallas, TX, USA, November 11-17, 2018, Proceedings / / edited by Sunita Chandrasekaran, Guido Juckeland, Sandra Wienke
Accelerator Programming Using Directives [[electronic resource] ] : 5th International Workshop, WACCPD 2018, Dallas, TX, USA, November 11-17, 2018, Proceedings / / edited by Sunita Chandrasekaran, Guido Juckeland, Sandra Wienke
Edizione [1st ed. 2019.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019
Descrizione fisica 1 online resource (IX, 137 p. 61 illus., 43 illus. in color.)
Disciplina 001.642
Collana Programming and Software Engineering
Soggetto topico Programming languages (Electronic computers)
Logic design
Input-output equipment (Computers)
Microprogramming 
Computer organization
Programming Languages, Compilers, Interpreters
Logic Design
Input/Output and Data Communications
Control Structures and Microprogramming
Computer Systems Organization and Communication Networks
ISBN 3-030-12274-3
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNISA-996466464703316
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
Adaptive Identification of Acoustic Multichannel Systems Using Sparse Representations [[electronic resource] /] / by Karim Helwani
Adaptive Identification of Acoustic Multichannel Systems Using Sparse Representations [[electronic resource] /] / by Karim Helwani
Autore Helwani Karim
Edizione [1st ed. 2015.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015
Descrizione fisica 1 online resource (120 p.)
Disciplina 621.3822
Collana T-Labs Series in Telecommunication Services
Soggetto topico Signal processing
Image processing
Speech processing systems
Input-output equipment (Computers)
Electrical engineering
Acoustics
Signal, Image and Speech Processing
Input/Output and Data Communications
Communications Engineering, Networks
ISBN 3-319-08954-4
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction -- Fundamentals of Adaptive Filter Theory -- Spatio-Temporal Regularized Recursive Least Squares Algorithm -- Sparse Representation of Multichannel Acoustic Systems -- Unique System Identification from Projections -- Geometrical Constraints -- Acoustic Echo Suppression -- Conclusion.
Record Nr. UNINA-9910299851503321
Helwani Karim  
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Advances in Communication, Cloud, and Big Data [[electronic resource] ] : Proceedings of 2nd National Conference on CCB 2016 / / edited by Hiren Kumar Deva Sarma, Samarjeet Borah, Nitul Dutta
Advances in Communication, Cloud, and Big Data [[electronic resource] ] : Proceedings of 2nd National Conference on CCB 2016 / / edited by Hiren Kumar Deva Sarma, Samarjeet Borah, Nitul Dutta
Edizione [1st ed. 2019.]
Pubbl/distr/stampa Singapore : , : Springer Singapore : , : Imprint : Springer, , 2019
Descrizione fisica 1 online resource (XIII, 173 p. 47 illus.)
Disciplina 004.6
Collana Lecture Notes in Networks and Systems
Soggetto topico Electrical engineering
Big data
Input-output equipment (Computers)
Communications Engineering, Networks
Big Data
Input/Output and Data Communications
ISBN 981-10-8911-6
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Chapter 1. Survey on Energy Efficient Routing Protocols in Wireless Sensor Networks using Game Theory -- Chapter 2. Design and Analysis of Optimum APSK Modulation Technique -- Chapter 3. Big Data Analytics in the Higher Education: Need of the future. Chapter 4. Land Capability Classification for Agriculture: GIS and Remote Sensing Approach: A Survey -- Chapter 5. Review on Vehicular Radar for Road Safety -- Chapter 6. Landmark Based Robot Navigation: A Paradigm Shift from Onboard Processing to Cloud -- Chapter 7. From Cognitive Psychology to Image Segmentation: A Change of Perspective -- Chapter 8. An Exploration in Perception Based Digital Media Processing: A Psychological Perspective -- Chapter 9. Converting and developing live website into a web content management system -- Chapter 10. A Review on Existing QoS Routing Protocols Based on Link Efficiency and Link Stability -- Chapter 11. A Diamond Shaped Fractal Bow-Tie Antenna for THz Applications -- Chapter 12. A Study on Few Approaches to Counter Security Breaches in MANETs -- Chapter 13. A Survey: EMG Signal Based Controller as Human Computer Interaction -- Chapter 14 [CCB 1622-] IEEE 802.15.4 as the MAC protocol for Internet of Things (IoT) Applications for achieving QoS and Energy Efficiency -- Chapter 15. HMM Based Speaker Gender Recognition for Bodo Language -- Chapter 16. Accurate Drainage Network Extraction From Satellite Imagery –a Survey -- Chapter 17. Survey on Transmission Control Protocol Performance over different Mobile Ad-Hoc Routing Protocols -- Chapter 18 -- Survey on detection and mitigation of Distributed Denial of Service attack in named data networking.
Record Nr. UNINA-9910337626703321
Singapore : , : Springer Singapore : , : Imprint : Springer, , 2019
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Advances in Computer Systems Architecture [[electronic resource] ] : 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings / / edited by Pen-Chung Yew, Jingling Xue
Advances in Computer Systems Architecture [[electronic resource] ] : 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings / / edited by Pen-Chung Yew, Jingling Xue
Edizione [1st ed. 2004.]
Pubbl/distr/stampa Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2004
Descrizione fisica 1 online resource (XVIII, 602 p.)
Disciplina 004.2/2
Collana Lecture Notes in Computer Science
Soggetto topico Architecture, Computer
Arithmetic and logic units, Computer
Input-output equipment (Computers)
Microprocessors
Computer communication systems
Computer System Implementation
Arithmetic and Logic Structures
Input/Output and Data Communications
Register-Transfer-Level Implementation
Computer Communication Networks
Processor Architectures
ISBN 3-540-30102-X
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Keynote Address I -- Some Real Observations on Virtual Machines -- Session 1A: Cache and Memory -- Replica Victim Caching to Improve Reliability of In-Cache Replication -- Efficient Victim Mechanism on Sector Cache Organization -- Cache Behavior Analysis of a Compiler-Assisted Cache Replacement Policy -- Modeling the Cache Behavior of Codes with Arbitrary Data-Dependent Conditional Structures -- Session 1B: Reconfigurable and Embedded Architectures -- A Configurable System-on-Chip Architecture for Embedded Devices -- An Auto-adaptative Reconfigurable Architecture for the Control -- Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory -- Heuristic Algorithm for Reducing Mapping Sets of Hardware-Software Partitioning in Reconfigurable System -- Session 2A: Processor Architecture and Design I -- Architecture Design of a High-Performance 32-Bit Fixed-Point DSP -- TengYue-1: A High Performance Embedded SoC -- A Fault-Tolerant Single-Chip Multiprocessor -- Session 2B: Power and Energy Management -- Initial Experiences with Dreamy Memory and the RAMpage Memory Hierarchy -- dDVS: An Efficient Dynamic Voltage Scaling Algorithm Based on the Differential of CPU Utilization -- High Performance Microprocessor Design Methods Exploiting Information Locality and Data Redundancy for Lower Area Cost and Power Consumption -- Session 3A: Processor Architecture and Design II -- Dynamic Reallocation of Functional Units in Superscalar Processors -- Multiple-Dimension Scalable Adaptive Stream Architecture -- Impact of Register-Cache Bandwidth Variation on Processor Performance -- Session 3B: Compiler and Operating System Issues -- Exploiting Free Execution Slots on EPIC Processors for Efficient and Accurate Runtime Profiling -- Continuous Adaptive Object-Code Re-optimization Framework -- Initial Evaluation of a User-Level Device Driver Framework -- Keynote Address II -- A Generation Ahead of Microprocessor: Where Software Can Drive uArchitecture To? -- Session 4A: Application-Specific Systems -- A Cost-Effective Supersampling for Full Scene AntiAliasing -- A Simple Architectural Enhancement for Fast and Flexible Elliptic Curve Cryptography over Binary Finite Fields GF(2 m ) -- Scalable Design Framework for JPEG2000 System Architecture -- Real-Time Three Dimensional Vision -- Session 4B: Interconnection Networks -- A Router Architecture for QoS Capable Clusters -- Optimal Scheduling Algorithms in WDM Optical Interconnects with Limited Range Wavelength Conversion Capability -- Comparative Evaluation of Adaptive and Deterministic Routing in the OTIS-Hypercube -- A Two-Level On-Chip Bus System Based on Multiplexers -- Keynote Address III -- Make Computers Cheaper and Simpler -- Session 5A: Prediction Techniques -- A Low Power Branch Predictor to Selectively Access the BTB -- Static Techniques to Improve Power Efficiency of Branch Predictors -- Choice Predictor for Free -- Performance Impact of Different Data Value Predictors -- Session 5B: Parallel Architecture and Programming -- Heterogeneous Networks of Workstations -- Finding High Performance Solution in Reconfigurable Mesh-Connected VLSI Arrays -- Order Independent Transparency for Image Composition Parallel Rendering Machines -- An Authorization Architecture Oriented to Engineering and Scientific Computation in Grid Environments -- Session 6A: Microarchitecture Design and Evaluations -- Validating Word-Oriented Processors for Bit and Multi-word Operations -- Dynamic Fetch Engine for Simultaneous Multithreaded Processors -- A Novel Rename Register Architecture and Performance Analysis -- Session 6B: Memory and I/O Systems -- A New Hierarchy Cache Scheme Using RAM and Pagefile -- An Object-Oriented Data Storage System on Network-Attached Object Devices -- A Scalable and Adaptive Directory Scheme for Hardware Distributed Shared Memory -- Session 7A: Potpourri -- A Compiler-Assisted On-Chip Assigned-Signature Control Flow Checking -- A Floating Point Divider Performing IEEE Rounding and Quotient Conversion in Parallel -- Efficient Buffer Allocation for Asynchronous Linear Pipelines by Design Space Localization.
Record Nr. UNINA-9910144151503321
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2004
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Advances in Computer Systems Architecture [[electronic resource] ] : 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings / / edited by Pen-Chung Yew, Jingling Xue
Advances in Computer Systems Architecture [[electronic resource] ] : 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings / / edited by Pen-Chung Yew, Jingling Xue
Edizione [1st ed. 2004.]
Pubbl/distr/stampa Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2004
Descrizione fisica 1 online resource (XVIII, 602 p.)
Disciplina 004.2/2
Collana Lecture Notes in Computer Science
Soggetto topico Architecture, Computer
Arithmetic and logic units, Computer
Input-output equipment (Computers)
Microprocessors
Computer communication systems
Computer System Implementation
Arithmetic and Logic Structures
Input/Output and Data Communications
Register-Transfer-Level Implementation
Computer Communication Networks
Processor Architectures
ISBN 3-540-30102-X
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Keynote Address I -- Some Real Observations on Virtual Machines -- Session 1A: Cache and Memory -- Replica Victim Caching to Improve Reliability of In-Cache Replication -- Efficient Victim Mechanism on Sector Cache Organization -- Cache Behavior Analysis of a Compiler-Assisted Cache Replacement Policy -- Modeling the Cache Behavior of Codes with Arbitrary Data-Dependent Conditional Structures -- Session 1B: Reconfigurable and Embedded Architectures -- A Configurable System-on-Chip Architecture for Embedded Devices -- An Auto-adaptative Reconfigurable Architecture for the Control -- Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory -- Heuristic Algorithm for Reducing Mapping Sets of Hardware-Software Partitioning in Reconfigurable System -- Session 2A: Processor Architecture and Design I -- Architecture Design of a High-Performance 32-Bit Fixed-Point DSP -- TengYue-1: A High Performance Embedded SoC -- A Fault-Tolerant Single-Chip Multiprocessor -- Session 2B: Power and Energy Management -- Initial Experiences with Dreamy Memory and the RAMpage Memory Hierarchy -- dDVS: An Efficient Dynamic Voltage Scaling Algorithm Based on the Differential of CPU Utilization -- High Performance Microprocessor Design Methods Exploiting Information Locality and Data Redundancy for Lower Area Cost and Power Consumption -- Session 3A: Processor Architecture and Design II -- Dynamic Reallocation of Functional Units in Superscalar Processors -- Multiple-Dimension Scalable Adaptive Stream Architecture -- Impact of Register-Cache Bandwidth Variation on Processor Performance -- Session 3B: Compiler and Operating System Issues -- Exploiting Free Execution Slots on EPIC Processors for Efficient and Accurate Runtime Profiling -- Continuous Adaptive Object-Code Re-optimization Framework -- Initial Evaluation of a User-Level Device Driver Framework -- Keynote Address II -- A Generation Ahead of Microprocessor: Where Software Can Drive uArchitecture To? -- Session 4A: Application-Specific Systems -- A Cost-Effective Supersampling for Full Scene AntiAliasing -- A Simple Architectural Enhancement for Fast and Flexible Elliptic Curve Cryptography over Binary Finite Fields GF(2 m ) -- Scalable Design Framework for JPEG2000 System Architecture -- Real-Time Three Dimensional Vision -- Session 4B: Interconnection Networks -- A Router Architecture for QoS Capable Clusters -- Optimal Scheduling Algorithms in WDM Optical Interconnects with Limited Range Wavelength Conversion Capability -- Comparative Evaluation of Adaptive and Deterministic Routing in the OTIS-Hypercube -- A Two-Level On-Chip Bus System Based on Multiplexers -- Keynote Address III -- Make Computers Cheaper and Simpler -- Session 5A: Prediction Techniques -- A Low Power Branch Predictor to Selectively Access the BTB -- Static Techniques to Improve Power Efficiency of Branch Predictors -- Choice Predictor for Free -- Performance Impact of Different Data Value Predictors -- Session 5B: Parallel Architecture and Programming -- Heterogeneous Networks of Workstations -- Finding High Performance Solution in Reconfigurable Mesh-Connected VLSI Arrays -- Order Independent Transparency for Image Composition Parallel Rendering Machines -- An Authorization Architecture Oriented to Engineering and Scientific Computation in Grid Environments -- Session 6A: Microarchitecture Design and Evaluations -- Validating Word-Oriented Processors for Bit and Multi-word Operations -- Dynamic Fetch Engine for Simultaneous Multithreaded Processors -- A Novel Rename Register Architecture and Performance Analysis -- Session 6B: Memory and I/O Systems -- A New Hierarchy Cache Scheme Using RAM and Pagefile -- An Object-Oriented Data Storage System on Network-Attached Object Devices -- A Scalable and Adaptive Directory Scheme for Hardware Distributed Shared Memory -- Session 7A: Potpourri -- A Compiler-Assisted On-Chip Assigned-Signature Control Flow Checking -- A Floating Point Divider Performing IEEE Rounding and Quotient Conversion in Parallel -- Efficient Buffer Allocation for Asynchronous Linear Pipelines by Design Space Localization.
Record Nr. UNISA-996465379503316
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2004
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
Advances in Computer Systems Architecture [[electronic resource] ] : 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings / / edited by Amos Omondi, Stanislav Sedukhin
Advances in Computer Systems Architecture [[electronic resource] ] : 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings / / edited by Amos Omondi, Stanislav Sedukhin
Edizione [1st ed. 2003.]
Pubbl/distr/stampa Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2003
Descrizione fisica 1 online resource (XIV, 410 p.)
Disciplina 004.2/2
Collana Lecture Notes in Computer Science
Soggetto topico Architecture, Computer
Logic design
Arithmetic and logic units, Computer
Input-output equipment (Computers)
Microprocessors
Computer communication systems
Computer System Implementation
Logic Design
Arithmetic and Logic Structures
Input/Output and Data Communications
Processor Architectures
Computer Communication Networks
ISBN 3-540-39864-3
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto How Can the Earth Simulator Impact on Human Activities -- Toward Architecting and Designing Novel Computers -- Designing Ultra-large Instruction Issue Windows -- Multi-threaded Microprocessors – Evolution or Revolution -- The Development of System Software for Parallel Supercomputers -- Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA -- Reconfigurable Logic: A Saviour for Experimental Computer Architecture Research -- Design and Implementation of Java Processors -- MOOSS: CPU Architecture with Memory Protection and Support for OOP -- Reducing Access Count to Register-Files through Operand Reuse -- SimAlpha Version 1.0: Simple and Readable Alpha Processor Simulator -- Towards an Asynchronous MIPS Processor -- On Implementing High Level Concurrency in Java -- Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures -- A Novel Architecture for Genomic Sequence Searching and Alignment -- A Reconfigurable Multi-threaded Architecture Model -- Reconfigurable Instruction-Level Parallel Processor Architecture -- Mapping Applications to a Coarse Grain Reconfigurable System -- Packing with Boundary Constraints for a Reconfigurable Operating System -- Arithmetic Circuits Combining Residue and Signed-Digit Representations -- A New On-the-fly Summation Algorithm -- State Reordering for Low Power Combinational Logic -- User-Level Management of Kernel Memory -- Variable Radix Page Table: A Page Table for Modern Architectures -- L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy -- Legba: Fast Hardware Support for Fine-Grained Protection -- Live-Cache: Exploiting Data Redundancy to Reduce Leakage Energy in a Cache Subsystem -- Implementation of Fast Address-Space Switching and TLB Sharing on the StrongARM Processor -- Performance of the Achilles Router -- Latency Improvement in Virtual Multicasting -- A Router Architecture to Achieve Link Rate Throughput in Suburban Ad-hoc Networks.
Record Nr. UNINA-9910144047403321
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2003
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui