Info
- Utilizzare la checkbox di selezione a fianco di ciascun documento per attivare le funzionalità di stampa, invio email, download nei formati disponibili del (i) record.
Formal methods in architecture and urbanism / / edited by David Leite Viana, Franklim Morais and Jorge Vieira Vaz
| Formal methods in architecture and urbanism / / edited by David Leite Viana, Franklim Morais and Jorge Vieira Vaz |
| Pubbl/distr/stampa | Newcastle upon Tyne, UK : , : Cambridge Scholars Publishing, , 2018 |
| Descrizione fisica | 1 online resource (405 pages) |
| Disciplina | 720.28402855369 |
| Soggetto topico |
Architecture - Data processing
Formal methods (Computer science) |
| ISBN | 1-5275-1457-9 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910812082603321 |
| Newcastle upon Tyne, UK : , : Cambridge Scholars Publishing, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Formal methods in computer-aided design : second international conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998 : proceedings / / Ganesh Gopalakrishnan, Phillip Windley (editors)
| Formal methods in computer-aided design : second international conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998 : proceedings / / Ganesh Gopalakrishnan, Phillip Windley (editors) |
| Edizione | [1st ed. 1998.] |
| Pubbl/distr/stampa | Berlin : , : Springer, , [1998] |
| Descrizione fisica | 1 online resource (X, 538 p.) |
| Disciplina | 621.392 |
| Collana | Lecture notes in computer science |
| Soggetto topico |
Digital integrated circuits - Computer-aided design
Computer engineering - Computer-aided design Integrated circuits - Verification Automatic theorem proving Formal methods (Computer science) |
| ISBN | 3-540-49519-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Minimalist Proof Assistants: Interactions of Technology and Methodology in Formal System Level Verification -- Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution -- Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking -- Solving Bit-Vector Equations -- The Formal Design of 1M-Gate ASICs -- Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations -- A Tutorial on Stålmarck’s Proof Procedure for Propositional Logic -- Almana: A BDD Minimization Tool Integrating Heuristic and RewritingMethods -- Bisimulation Minimization in an Automata-Theoretic Verification Framework -- Automatic Verification of Mixed-Level Logic Circuits -- A Timed Automaton-Based Method for Accurate Computation of Circuit Delay in the Presence of Cross-Talk -- Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints -- Using MTBDDs for Composition and Model Checking of Real-Time Systems -- Formal Methods in CAD from an Industrial Perspective -- A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool -- Combined Formal Post- and Presynthesis Verification in High Level Synthesis -- Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem -- A Performance Study of BDD-Based Model Checking -- Symbolic Model Checking Visualization -- Input Elimination and Abstraction in Model Checking -- Symbolic Simulation of the JEM1 Microprocessor -- Symbolic Simulation: An ACL2 Approach -- Verification of Data-Insensitive Circuits: An In-Order-Retirement Case Study -- Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification -- Formally Verifying Data and Control with Weak Reachability Invariants -- Generalized Reversible Rules -- An Assume-Guarantee Rule for Checking Simulation -- Three Approaches to Hardware Verification: HOL, MDG, and VIS Compared -- An Instruction Set Process Calculus -- Techniques for Implicit State Enumeration of EFSMs -- Model Checking on Product Structures -- BDDNOW: A Parallel BDD Package -- Model Checking VHDL with CV -- Alexandria: A Tool for Hierarchical Verification -- PV: An Explicit Enumeration Model-Checker. |
| Record Nr. | UNINA-9910143467903321 |
| Berlin : , : Springer, , [1998] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Formal methods in computer-aided design : second international conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998 : proceedings / / Ganesh Gopalakrishnan, Phillip Windley (editors)
| Formal methods in computer-aided design : second international conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998 : proceedings / / Ganesh Gopalakrishnan, Phillip Windley (editors) |
| Edizione | [1st ed. 1998.] |
| Pubbl/distr/stampa | Berlin : , : Springer, , [1998] |
| Descrizione fisica | 1 online resource (X, 538 p.) |
| Disciplina | 621.392 |
| Collana | Lecture notes in computer science |
| Soggetto topico |
Digital integrated circuits - Computer-aided design
Computer engineering - Computer-aided design Integrated circuits - Verification Automatic theorem proving Formal methods (Computer science) |
| ISBN | 3-540-49519-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Minimalist Proof Assistants: Interactions of Technology and Methodology in Formal System Level Verification -- Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution -- Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking -- Solving Bit-Vector Equations -- The Formal Design of 1M-Gate ASICs -- Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations -- A Tutorial on Stålmarck’s Proof Procedure for Propositional Logic -- Almana: A BDD Minimization Tool Integrating Heuristic and RewritingMethods -- Bisimulation Minimization in an Automata-Theoretic Verification Framework -- Automatic Verification of Mixed-Level Logic Circuits -- A Timed Automaton-Based Method for Accurate Computation of Circuit Delay in the Presence of Cross-Talk -- Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints -- Using MTBDDs for Composition and Model Checking of Real-Time Systems -- Formal Methods in CAD from an Industrial Perspective -- A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool -- Combined Formal Post- and Presynthesis Verification in High Level Synthesis -- Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem -- A Performance Study of BDD-Based Model Checking -- Symbolic Model Checking Visualization -- Input Elimination and Abstraction in Model Checking -- Symbolic Simulation of the JEM1 Microprocessor -- Symbolic Simulation: An ACL2 Approach -- Verification of Data-Insensitive Circuits: An In-Order-Retirement Case Study -- Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification -- Formally Verifying Data and Control with Weak Reachability Invariants -- Generalized Reversible Rules -- An Assume-Guarantee Rule for Checking Simulation -- Three Approaches to Hardware Verification: HOL, MDG, and VIS Compared -- An Instruction Set Process Calculus -- Techniques for Implicit State Enumeration of EFSMs -- Model Checking on Product Structures -- BDDNOW: A Parallel BDD Package -- Model Checking VHDL with CV -- Alexandria: A Tool for Hierarchical Verification -- PV: An Explicit Enumeration Model-Checker. |
| Record Nr. | UNISA-996465910703316 |
| Berlin : , : Springer, , [1998] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Formal methods: foundations and applications : 25th Brazilian symposium, SBMF 2022, virtual event, December 6-9, 2022, proceedings / / Lucas Lima, Vince Molnár (editors)
| Formal methods: foundations and applications : 25th Brazilian symposium, SBMF 2022, virtual event, December 6-9, 2022, proceedings / / Lucas Lima, Vince Molnár (editors) |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , [2022] |
| Descrizione fisica | 1 online resource (154 pages) |
| Disciplina | 005.1 |
| Collana | Lecture notes in computer science |
| Soggetto topico |
Computer software - Development
Formal methods (Computer science) |
| ISBN | 3-031-22476-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Preface -- Organization -- Invited Talks -- Cooperative Verification -- Taming Monsters with Dragons: A Fractal Approach to Digital Twin Pipelines -- Developing an Open-Source, State-of-the-Art Symbolic Model-Checking Framework for the Model-Checking Research Community -- Some Applications of Formal Methods -- Contents -- Model Checking and Semantics -- An Efficient Customized Clock Allocation Algorithm for a Class of Timed Automata -- 1 Introduction -- 2 Timed automata -- 3 The Class TADS -- 4 The Notion of Optimality -- 5 Finding an Optimal Allocation of Clocks -- 5.1 Liveness Analysis of Clocks -- 5.2 Clock Allocation -- 5.3 The Clock Allocation Algorithm -- 5.4 Generating Clock Constraints and Clock Resets -- 6 Related Work and Conclusions -- References -- Formalization of Functional Block Diagrams Using HOL Theorem Proving -- 1 Introduction -- 2 Preliminaries -- 2.1 Formal ET Modeling -- 2.2 Formal ET Probabilistic Analysis -- 3 Functional Block Diagrams -- 4 FBD Formalization -- 4.1 Formal FBD Modeling -- 4.2 Formal FBD Probabilistic Analysis -- 5 Conclusions -- References -- Generation and Synthesis -- A Sound Strategy to Compile General Recursion into Finite Depth Pattern Matching -- 1 Introduction -- 2 Basic Definitions -- 3 Expansion and Transformation -- 3.1 Unrolling -- 3.2 Recursion Elimination -- 4 Term Generation -- 4.1 Soundness of Term Generation -- 5 Quick-Checking Properties -- 6 Related Work -- 7 Conclusion -- References -- Automatic Generation of Verified Concurrent Hardware Using VHDL -- 1 Introduction -- 1.1 Related Work -- 2 Theoretical Background -- 2.1 CSP -- 2.2 VHDL -- 3 CSP to VHDL Translation -- 3.1 Translation Overview -- 3.2 Restrictions -- 4 Tool Support -- 5 Case Study -- 6 Conclusion -- References -- Synthesis of Implementations for Divide-and-Conquer Specifications -- 1 Introduction -- 2 Preliminaries.
3 From Divide-and-Conquer Specifications to Their Implementations -- 3.1 The Synthesis Rule -- 4 Case Study: Deriving an Implementation of a Greedy Algorithm -- 4.1 Weighted Matroids and Their Bases -- 4.2 Establishing max-basisI as a Divide-and-Conquer Specification -- 4.3 Implementations of Decomposition and Composition -- 5 Related Work -- 6 Conclusions and Outlook -- A The Three Auxiliary Lemmas -- References -- Verification and Solvers -- Compositional Verification of Simulink Block Diagrams Using tock-CSP and CSP-Prover -- 1 Introduction -- 2 Background -- 2.1 Block Diagrams and MDD -- 2.2 Running Example - Simple Actuator System (SAS) -- 2.3 Formal Verification and CSP -- 2.4 tock-CSP -- 2.5 Roscoe and Dathi's Compositional Deadlock Analysis Theory -- 2.6 CSP-Prover -- 3 Mechanised Compositional Verification of Timed Process Networks -- 3.1 Time-Stop Free Processes -- 3.2 Time-Stop Free Process Networks -- 3.3 Mechanisation in CSP-Prover -- 4 From Simulink to tock-CSP -- 5 Conclusion and Future Works -- References -- Excommunication: Transforming -Calculus Specifications to Remove Internal Communication -- 1 Introduction -- 2 The -Calculus -- 3 The Excommunication Algorithm -- 3.1 Transformation Rules -- 4 Example Application: A Leakage Analysis -- 4.1 An Application of the Leakage Analysis -- 5 Conclusion and Further Work -- References -- Level-Up - From Bits to Words -- 1 Introduction -- 2 Background -- 2.1 Verification Using Satisfiability Solvers -- 2.2 Word-Level Verification -- 3 Using Bit-Level Information on Word-Level -- 3.1 Computing Bit-Level Information -- 3.2 Bit-Level Information for the Example -- 3.3 Integration Strategies -- 3.4 Integration Strategies for Bit-Level Information -- 3.5 Implementation and Tool Chain -- 4 Evaluation Experiments -- 4.1 Experimental Setup -- 4.2 Experimental Results -- 5 Related Work. 6 Conclusion and Outlook -- References -- Author Index. |
| Record Nr. | UNINA-9910633930503321 |
| Cham, Switzerland : , : Springer, , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Formal methods: foundations and applications : 25th Brazilian symposium, SBMF 2022, virtual event, December 6-9, 2022, proceedings / / Lucas Lima, Vince Molnár (editors)
| Formal methods: foundations and applications : 25th Brazilian symposium, SBMF 2022, virtual event, December 6-9, 2022, proceedings / / Lucas Lima, Vince Molnár (editors) |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , [2022] |
| Descrizione fisica | 1 online resource (154 pages) |
| Disciplina | 005.1 |
| Collana | Lecture notes in computer science |
| Soggetto topico |
Computer software - Development
Formal methods (Computer science) |
| ISBN | 3-031-22476-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Preface -- Organization -- Invited Talks -- Cooperative Verification -- Taming Monsters with Dragons: A Fractal Approach to Digital Twin Pipelines -- Developing an Open-Source, State-of-the-Art Symbolic Model-Checking Framework for the Model-Checking Research Community -- Some Applications of Formal Methods -- Contents -- Model Checking and Semantics -- An Efficient Customized Clock Allocation Algorithm for a Class of Timed Automata -- 1 Introduction -- 2 Timed automata -- 3 The Class TADS -- 4 The Notion of Optimality -- 5 Finding an Optimal Allocation of Clocks -- 5.1 Liveness Analysis of Clocks -- 5.2 Clock Allocation -- 5.3 The Clock Allocation Algorithm -- 5.4 Generating Clock Constraints and Clock Resets -- 6 Related Work and Conclusions -- References -- Formalization of Functional Block Diagrams Using HOL Theorem Proving -- 1 Introduction -- 2 Preliminaries -- 2.1 Formal ET Modeling -- 2.2 Formal ET Probabilistic Analysis -- 3 Functional Block Diagrams -- 4 FBD Formalization -- 4.1 Formal FBD Modeling -- 4.2 Formal FBD Probabilistic Analysis -- 5 Conclusions -- References -- Generation and Synthesis -- A Sound Strategy to Compile General Recursion into Finite Depth Pattern Matching -- 1 Introduction -- 2 Basic Definitions -- 3 Expansion and Transformation -- 3.1 Unrolling -- 3.2 Recursion Elimination -- 4 Term Generation -- 4.1 Soundness of Term Generation -- 5 Quick-Checking Properties -- 6 Related Work -- 7 Conclusion -- References -- Automatic Generation of Verified Concurrent Hardware Using VHDL -- 1 Introduction -- 1.1 Related Work -- 2 Theoretical Background -- 2.1 CSP -- 2.2 VHDL -- 3 CSP to VHDL Translation -- 3.1 Translation Overview -- 3.2 Restrictions -- 4 Tool Support -- 5 Case Study -- 6 Conclusion -- References -- Synthesis of Implementations for Divide-and-Conquer Specifications -- 1 Introduction -- 2 Preliminaries.
3 From Divide-and-Conquer Specifications to Their Implementations -- 3.1 The Synthesis Rule -- 4 Case Study: Deriving an Implementation of a Greedy Algorithm -- 4.1 Weighted Matroids and Their Bases -- 4.2 Establishing max-basisI as a Divide-and-Conquer Specification -- 4.3 Implementations of Decomposition and Composition -- 5 Related Work -- 6 Conclusions and Outlook -- A The Three Auxiliary Lemmas -- References -- Verification and Solvers -- Compositional Verification of Simulink Block Diagrams Using tock-CSP and CSP-Prover -- 1 Introduction -- 2 Background -- 2.1 Block Diagrams and MDD -- 2.2 Running Example - Simple Actuator System (SAS) -- 2.3 Formal Verification and CSP -- 2.4 tock-CSP -- 2.5 Roscoe and Dathi's Compositional Deadlock Analysis Theory -- 2.6 CSP-Prover -- 3 Mechanised Compositional Verification of Timed Process Networks -- 3.1 Time-Stop Free Processes -- 3.2 Time-Stop Free Process Networks -- 3.3 Mechanisation in CSP-Prover -- 4 From Simulink to tock-CSP -- 5 Conclusion and Future Works -- References -- Excommunication: Transforming -Calculus Specifications to Remove Internal Communication -- 1 Introduction -- 2 The -Calculus -- 3 The Excommunication Algorithm -- 3.1 Transformation Rules -- 4 Example Application: A Leakage Analysis -- 4.1 An Application of the Leakage Analysis -- 5 Conclusion and Further Work -- References -- Level-Up - From Bits to Words -- 1 Introduction -- 2 Background -- 2.1 Verification Using Satisfiability Solvers -- 2.2 Word-Level Verification -- 3 Using Bit-Level Information on Word-Level -- 3.1 Computing Bit-Level Information -- 3.2 Bit-Level Information for the Example -- 3.3 Integration Strategies -- 3.4 Integration Strategies for Bit-Level Information -- 3.5 Implementation and Tool Chain -- 4 Evaluation Experiments -- 4.1 Experimental Setup -- 4.2 Experimental Results -- 5 Related Work. 6 Conclusion and Outlook -- References -- Author Index. |
| Record Nr. | UNISA-996500061203316 |
| Cham, Switzerland : , : Springer, , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Formal modeling and analysis of timed systems : 20th international conference, FORMATS 2022, Warsaw, Poland, September 13-15, 2022, proceedings / / Sergiy Bogomolov, David Parker (editors)
| Formal modeling and analysis of timed systems : 20th international conference, FORMATS 2022, Warsaw, Poland, September 13-15, 2022, proceedings / / Sergiy Bogomolov, David Parker (editors) |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , [2022] |
| Descrizione fisica | 1 online resource (315 pages) |
| Disciplina | 003.3 |
| Collana | Lecture notes in computer science |
| Soggetto topico |
Computer simulation
Formal methods (Computer science) System analysis |
| ISBN | 3-031-15839-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Preface -- Organization -- Abstracts -- A Behaviour-Based Approach to Quantitative Validation of Cyber-Physical Systems -- A Personal History of Formal Modeling and Analysis of Timed Systems Before There was FORMATS -- Contents -- Invited Papers -- Algebraic Model Checking for Discrete Linear Dynamical Systems -- 1 Introduction -- 1.1 Skolem Oracles -- 1.2 Main Results -- 2 Algebraic Model Checking -- 3 Conclusion -- References -- Zone-Based Verification of Timed Automata: Extrapolations, Simulations and What Next? -- 1 Introduction -- 2 Birth of Timed Automata for Verification: The Early 90's -- 2.1 Preliminaries -- 2.2 The Timed Automaton Model ch2AD90,ch2AD94 -- 3 A Symbolic Approach to the Verification of Timed Automata -- 3.1 Zones and Symbolic Forward Computation -- 3.2 Difference Bounded Matrices (DBMs) -- 3.3 Efficiency of the Forward Analysis -- 4 Extrapolation: A First Solution -- 4.1 The First Extrapolation Operator -- 4.2 Two Refinements of This Approach -- 4.3 Problems with Diagonal Clock Constraints -- 5 Simulation: An Alternative Solution -- 6 Beyond Reachability -- 6.1 Weighted Timed Automata -- 6.2 Liveness Properties -- 7 Tools -- 7.1 A Tool for Verifying Timed Automata: Uppaal -- 7.2 The Tool TChecker -- 8 What Next? -- 8.1 BDD and SAT Based Methods -- 8.2 The Local-Time Semantics and Partial-Order Reduction -- 8.3 Domain-Specific Algorithms -- 8.4 Richer Models -- References -- Monitoring Timed Properties (Revisited) -- 1 Introduction -- 2 Related Work -- 3 Preliminaries -- 4 Monitoring in a Timed Setting -- 5 Time Divergence -- 6 A Symbolic Method for Monitoring -- 7 Time Uncertainty -- 8 Time Predictive Monitoring -- 9 Conclusion -- References -- Probabilistic and Timed Systems -- Bounded Delay Timed Channel Coding -- 1 Introduction -- 2 Preliminary Work -- 2.1 Timed Languages and Timed Automata.
2.2 Entropy and Capacity -- 2.3 Pseudo-Distance on Timed Languages -- 2.4 The Factor Language -- 3 Bandwidth -- 3.1 Definitions -- 3.2 Examples -- 3.3 Existence of Limits -- 4 Encodings -- 4.1 Definition -- 4.2 Necessary Condition -- 4.3 Sufficient Condition -- 5 Conclusion and Further Work -- References -- Robustly Complete Finite-State Abstractions for Verification of Stochastic Systems -- 1 Introduction -- 2 Preliminaries -- 2.1 Canonical Sample Space -- 2.2 Markov Transition Systems -- 2.3 Weak Convergence and Prokhorov's Theorem -- 2.4 Discrete-Time Continuous-State Stochastic Systems -- 2.5 Robust Abstractions -- 3 Soundness of Robust IMC Abstractions -- 3.1 Weak Compactness of Marginal Space Mt of Probabilities -- 3.2 Weak Compactness of Probability Laws of I on Infinite Horizon -- 3.3 Soundness of IMC Abstractions -- 4 Robust Completeness of IMC Abstractions -- 5 Conclusion -- References -- Model Checking for Entanglement Swapping -- 1 Introduction -- 2 Preliminaries -- 2.1 Probabilistic Timed Automata -- 3 Modeling and Validation -- 3.1 The PTA Model -- 3.2 Validation Through Simulations -- 4 Experimental Setup -- 5 Results -- 6 Discussions and Outlook -- References -- Temporal Logic -- An STL-Based Formulation of Resilience in Cyber-Physical Systems -- 1 Introduction -- 2 Preliminaries -- 3 Specifying Resilience in STL -- 3.1 Resiliency Specification Language -- 3.2 Semantics of Resiliency Specifications -- 4 Case Study -- 4.1 UAV Package Delivery -- 4.2 Multi-agent Flocking -- 5 Related Work -- 6 Conclusion -- References -- MITL Verification Under Timing Uncertainty -- 1 Introduction -- 2 Preliminaries -- 2.1 Set Theory -- 2.2 Topology -- 3 Problem Formulation -- 3.1 Syntax and Semantics of MITL -- 3.2 Truth Sets and Interval Queues -- 4 Interval Queue Fundamentals -- 4.1 Construction Algorithm -- 4.2 Complementation Algorithm. 5 Verification Procedure -- 5.1 Operators in the Interval Queue Domain -- 5.2 Constructing Under- and Over-Approximations -- 5.3 Conservativeness -- 6 Numerical Example -- 7 Conclusion -- A Proof of Theorem 1 -- References -- Classification of Driving Behaviors Using STL Formulas: A Comparative Study -- 1 Introduction -- 2 Preliminaries -- 3 Specifying Longitudinal Driving Behavior with STL -- 4 Methods -- 5 Experiments -- 6 Discussion and Conclusions -- References -- Timed Automata and Games -- Timed Games with Bounded Window Parity Objectives -- 1 Introduction -- 2 Preliminaries -- 3 Bounded Window Objectives -- 4 Verification of Timed Automata -- 5 Solving Timed Games -- References -- Non-blind Strategies in Timed Network Congestion Games -- 1 Introduction -- 2 Preliminaries -- 2.1 Timed Network Congestion Game -- 2.2 Studied Problems -- 3 Existence and Computation of Nash Equilibria -- 3.1 Transformation into an Equivalent Finite Concurrent Game -- 3.2 Existence of Nash Equilibria -- 3.3 Computation of Nash Equilibria -- 4 Social Optimality and Prices of Anarchy and Stability -- 4.1 Constrained-Social-Welfare Problem: Asymmetric Case -- 4.2 Constrained-Social-Welfare Problem: Symmetric Case -- 4.3 Social Optimum and Prices of Anarchy and Stability -- References -- Efficient Convex Zone Merging in Parametric Timed Automata -- 1 Introduction -- 2 Preliminaries -- 3 Efficient State Merging in Parametric Timed Automata -- 3.1 Merging Algorithm -- 3.2 Heuristics for Merging -- 3.3 Preservation of Properties -- 4 Experiments -- 4.1 Dataset and Experimental Environment -- 4.2 Description of the Experiments -- 5 Conclusion -- A Results for All Heuristics on the Full Benchmark -- References -- Neural Networks -- Neural Network Repair with Reachability Analysis -- 1 Introduction -- 2 Deep Neural Network Repair -- 2.1 Provably Safe DNNs. 2.2 DNN Agent Repair for Deep Reinforcement Learning -- 2.3 Computation of Exact Unsafe Domain of ReLU DNNs -- 3 Framework for DNN Repair -- 3.1 Formulation of Loss Function for Problems 1 & -- 2 -- 3.2 Repair for Deep Reinforcement Learning -- 4 Experiments and Evaluation -- 4.1 Repair of ACAS Xu Neural Network Controllers -- 4.2 Rocket Lander Benchmark -- 5 Conclusion and Future Work -- References -- On Neural Network Equivalence Checking Using SMT Solvers -- 1 Introduction -- 2 Preliminaries: Neural Networks -- 2.1 Notation -- 2.2 Neural Networks -- 3 Strict and Approximate Equivalences for Neural Networks -- 3.1 Strict Neural Network Equivalence -- 3.2 Approximate Neural Network Equivalences Based on Lp Norms -- 3.3 Approximate Neural Network Equivalences Based on Order of Outputs -- 3.4 Hybrid Lp-argsort Equivalences -- 3.5 The Neural Network Equivalence Checking Problem -- 3.6 Discussion of Application Domains for the Above Equivalence Relations -- 4 Neural Network Equivalence Checking Using SMT Solvers -- 4.1 Encoding Neural Networks as SMT Formulas -- 4.2 Encoding of the Equivalence Relation -- 4.3 Optimizing the Encoding -- 5 Experimental Results -- 5.1 Sanity Checks -- 5.2 Equivalence Checking -- 6 Related Work -- 7 Conclusions -- References -- Reachability Analysis of a General Class of Neural Ordinary Differential Equations -- 1 Introduction -- 2 Background and Problem Formulation -- 2.1 General Neural ODE -- 2.2 NODE: Applications -- 2.3 Reachability Analysis -- 2.4 Reachability Methods -- 3 Evaluation -- 3.1 Method and Tool Comparison -- 3.2 Case Study: Adaptive Cruise Control (ACC) -- 3.3 Classification NODEs -- 4 Related Work -- 5 Conclusion and Future Work -- References -- Reinforcement Learning -- Robust Event-Driven Interactions in Cooperative Multi-agent Learning -- 1 Introduction -- 1.1 Main Contribution -- 2 Preliminaries. 2.1 Notation -- 2.2 MDPs and Multi-agent MDPs -- 2.3 Value Functions and Q-Learning in c-MMDPs -- 3 Information Sharing Between Collaborative Agents: Problem Formulation -- 4 Efficient Communication Strategies -- 4.1 Event-Driven Interactions -- 5 Robustness Surrogate and Its Computation -- 5.1 Learning the Robustness Surrogate with the Scenario Approach -- 6 Experiments -- 6.1 Benchmark: Collaborative Particle-Tag -- 6.2 Computation of Robustness Surrogates -- 6.3 Results -- 7 Discussion -- References -- Learning that Grid-Convenience Does Not Hurt Resilience in the Presence of Uncertainty -- 1 Introduction -- 2 Case Study -- 3 Methodology -- 4 Results -- 5 Reproducibility and Conclusions -- References -- Author Index. |
| Record Nr. | UNINA-9910590070203321 |
| Cham, Switzerland : , : Springer, , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Formal modeling and analysis of timed systems : 20th international conference, FORMATS 2022, Warsaw, Poland, September 13-15, 2022, proceedings / / Sergiy Bogomolov, David Parker (editors)
| Formal modeling and analysis of timed systems : 20th international conference, FORMATS 2022, Warsaw, Poland, September 13-15, 2022, proceedings / / Sergiy Bogomolov, David Parker (editors) |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , [2022] |
| Descrizione fisica | 1 online resource (315 pages) |
| Disciplina | 003.3 |
| Collana | Lecture notes in computer science |
| Soggetto topico |
Computer simulation
Formal methods (Computer science) System analysis |
| ISBN | 3-031-15839-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Preface -- Organization -- Abstracts -- A Behaviour-Based Approach to Quantitative Validation of Cyber-Physical Systems -- A Personal History of Formal Modeling and Analysis of Timed Systems Before There was FORMATS -- Contents -- Invited Papers -- Algebraic Model Checking for Discrete Linear Dynamical Systems -- 1 Introduction -- 1.1 Skolem Oracles -- 1.2 Main Results -- 2 Algebraic Model Checking -- 3 Conclusion -- References -- Zone-Based Verification of Timed Automata: Extrapolations, Simulations and What Next? -- 1 Introduction -- 2 Birth of Timed Automata for Verification: The Early 90's -- 2.1 Preliminaries -- 2.2 The Timed Automaton Model ch2AD90,ch2AD94 -- 3 A Symbolic Approach to the Verification of Timed Automata -- 3.1 Zones and Symbolic Forward Computation -- 3.2 Difference Bounded Matrices (DBMs) -- 3.3 Efficiency of the Forward Analysis -- 4 Extrapolation: A First Solution -- 4.1 The First Extrapolation Operator -- 4.2 Two Refinements of This Approach -- 4.3 Problems with Diagonal Clock Constraints -- 5 Simulation: An Alternative Solution -- 6 Beyond Reachability -- 6.1 Weighted Timed Automata -- 6.2 Liveness Properties -- 7 Tools -- 7.1 A Tool for Verifying Timed Automata: Uppaal -- 7.2 The Tool TChecker -- 8 What Next? -- 8.1 BDD and SAT Based Methods -- 8.2 The Local-Time Semantics and Partial-Order Reduction -- 8.3 Domain-Specific Algorithms -- 8.4 Richer Models -- References -- Monitoring Timed Properties (Revisited) -- 1 Introduction -- 2 Related Work -- 3 Preliminaries -- 4 Monitoring in a Timed Setting -- 5 Time Divergence -- 6 A Symbolic Method for Monitoring -- 7 Time Uncertainty -- 8 Time Predictive Monitoring -- 9 Conclusion -- References -- Probabilistic and Timed Systems -- Bounded Delay Timed Channel Coding -- 1 Introduction -- 2 Preliminary Work -- 2.1 Timed Languages and Timed Automata.
2.2 Entropy and Capacity -- 2.3 Pseudo-Distance on Timed Languages -- 2.4 The Factor Language -- 3 Bandwidth -- 3.1 Definitions -- 3.2 Examples -- 3.3 Existence of Limits -- 4 Encodings -- 4.1 Definition -- 4.2 Necessary Condition -- 4.3 Sufficient Condition -- 5 Conclusion and Further Work -- References -- Robustly Complete Finite-State Abstractions for Verification of Stochastic Systems -- 1 Introduction -- 2 Preliminaries -- 2.1 Canonical Sample Space -- 2.2 Markov Transition Systems -- 2.3 Weak Convergence and Prokhorov's Theorem -- 2.4 Discrete-Time Continuous-State Stochastic Systems -- 2.5 Robust Abstractions -- 3 Soundness of Robust IMC Abstractions -- 3.1 Weak Compactness of Marginal Space Mt of Probabilities -- 3.2 Weak Compactness of Probability Laws of I on Infinite Horizon -- 3.3 Soundness of IMC Abstractions -- 4 Robust Completeness of IMC Abstractions -- 5 Conclusion -- References -- Model Checking for Entanglement Swapping -- 1 Introduction -- 2 Preliminaries -- 2.1 Probabilistic Timed Automata -- 3 Modeling and Validation -- 3.1 The PTA Model -- 3.2 Validation Through Simulations -- 4 Experimental Setup -- 5 Results -- 6 Discussions and Outlook -- References -- Temporal Logic -- An STL-Based Formulation of Resilience in Cyber-Physical Systems -- 1 Introduction -- 2 Preliminaries -- 3 Specifying Resilience in STL -- 3.1 Resiliency Specification Language -- 3.2 Semantics of Resiliency Specifications -- 4 Case Study -- 4.1 UAV Package Delivery -- 4.2 Multi-agent Flocking -- 5 Related Work -- 6 Conclusion -- References -- MITL Verification Under Timing Uncertainty -- 1 Introduction -- 2 Preliminaries -- 2.1 Set Theory -- 2.2 Topology -- 3 Problem Formulation -- 3.1 Syntax and Semantics of MITL -- 3.2 Truth Sets and Interval Queues -- 4 Interval Queue Fundamentals -- 4.1 Construction Algorithm -- 4.2 Complementation Algorithm. 5 Verification Procedure -- 5.1 Operators in the Interval Queue Domain -- 5.2 Constructing Under- and Over-Approximations -- 5.3 Conservativeness -- 6 Numerical Example -- 7 Conclusion -- A Proof of Theorem 1 -- References -- Classification of Driving Behaviors Using STL Formulas: A Comparative Study -- 1 Introduction -- 2 Preliminaries -- 3 Specifying Longitudinal Driving Behavior with STL -- 4 Methods -- 5 Experiments -- 6 Discussion and Conclusions -- References -- Timed Automata and Games -- Timed Games with Bounded Window Parity Objectives -- 1 Introduction -- 2 Preliminaries -- 3 Bounded Window Objectives -- 4 Verification of Timed Automata -- 5 Solving Timed Games -- References -- Non-blind Strategies in Timed Network Congestion Games -- 1 Introduction -- 2 Preliminaries -- 2.1 Timed Network Congestion Game -- 2.2 Studied Problems -- 3 Existence and Computation of Nash Equilibria -- 3.1 Transformation into an Equivalent Finite Concurrent Game -- 3.2 Existence of Nash Equilibria -- 3.3 Computation of Nash Equilibria -- 4 Social Optimality and Prices of Anarchy and Stability -- 4.1 Constrained-Social-Welfare Problem: Asymmetric Case -- 4.2 Constrained-Social-Welfare Problem: Symmetric Case -- 4.3 Social Optimum and Prices of Anarchy and Stability -- References -- Efficient Convex Zone Merging in Parametric Timed Automata -- 1 Introduction -- 2 Preliminaries -- 3 Efficient State Merging in Parametric Timed Automata -- 3.1 Merging Algorithm -- 3.2 Heuristics for Merging -- 3.3 Preservation of Properties -- 4 Experiments -- 4.1 Dataset and Experimental Environment -- 4.2 Description of the Experiments -- 5 Conclusion -- A Results for All Heuristics on the Full Benchmark -- References -- Neural Networks -- Neural Network Repair with Reachability Analysis -- 1 Introduction -- 2 Deep Neural Network Repair -- 2.1 Provably Safe DNNs. 2.2 DNN Agent Repair for Deep Reinforcement Learning -- 2.3 Computation of Exact Unsafe Domain of ReLU DNNs -- 3 Framework for DNN Repair -- 3.1 Formulation of Loss Function for Problems 1 & -- 2 -- 3.2 Repair for Deep Reinforcement Learning -- 4 Experiments and Evaluation -- 4.1 Repair of ACAS Xu Neural Network Controllers -- 4.2 Rocket Lander Benchmark -- 5 Conclusion and Future Work -- References -- On Neural Network Equivalence Checking Using SMT Solvers -- 1 Introduction -- 2 Preliminaries: Neural Networks -- 2.1 Notation -- 2.2 Neural Networks -- 3 Strict and Approximate Equivalences for Neural Networks -- 3.1 Strict Neural Network Equivalence -- 3.2 Approximate Neural Network Equivalences Based on Lp Norms -- 3.3 Approximate Neural Network Equivalences Based on Order of Outputs -- 3.4 Hybrid Lp-argsort Equivalences -- 3.5 The Neural Network Equivalence Checking Problem -- 3.6 Discussion of Application Domains for the Above Equivalence Relations -- 4 Neural Network Equivalence Checking Using SMT Solvers -- 4.1 Encoding Neural Networks as SMT Formulas -- 4.2 Encoding of the Equivalence Relation -- 4.3 Optimizing the Encoding -- 5 Experimental Results -- 5.1 Sanity Checks -- 5.2 Equivalence Checking -- 6 Related Work -- 7 Conclusions -- References -- Reachability Analysis of a General Class of Neural Ordinary Differential Equations -- 1 Introduction -- 2 Background and Problem Formulation -- 2.1 General Neural ODE -- 2.2 NODE: Applications -- 2.3 Reachability Analysis -- 2.4 Reachability Methods -- 3 Evaluation -- 3.1 Method and Tool Comparison -- 3.2 Case Study: Adaptive Cruise Control (ACC) -- 3.3 Classification NODEs -- 4 Related Work -- 5 Conclusion and Future Work -- References -- Reinforcement Learning -- Robust Event-Driven Interactions in Cooperative Multi-agent Learning -- 1 Introduction -- 1.1 Main Contribution -- 2 Preliminaries. 2.1 Notation -- 2.2 MDPs and Multi-agent MDPs -- 2.3 Value Functions and Q-Learning in c-MMDPs -- 3 Information Sharing Between Collaborative Agents: Problem Formulation -- 4 Efficient Communication Strategies -- 4.1 Event-Driven Interactions -- 5 Robustness Surrogate and Its Computation -- 5.1 Learning the Robustness Surrogate with the Scenario Approach -- 6 Experiments -- 6.1 Benchmark: Collaborative Particle-Tag -- 6.2 Computation of Robustness Surrogates -- 6.3 Results -- 7 Discussion -- References -- Learning that Grid-Convenience Does Not Hurt Resilience in the Presence of Uncertainty -- 1 Introduction -- 2 Case Study -- 3 Methodology -- 4 Results -- 5 Reproducibility and Conclusions -- References -- Author Index. |
| Record Nr. | UNISA-996485665403316 |
| Cham, Switzerland : , : Springer, , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Formal models of agents : ESPRIT Project ModelAge final report / / John-Jules Ch. Meyer, Pierre-Yves Schobbens, editors
| Formal models of agents : ESPRIT Project ModelAge final report / / John-Jules Ch. Meyer, Pierre-Yves Schobbens, editors |
| Edizione | [1st ed. 1999.] |
| Pubbl/distr/stampa | Berlin ; ; Heidelberg : , : Springer, , [2000] |
| Descrizione fisica | 1 online resource (VIII, 260 p.) |
| Disciplina | 006.30285436 |
| Collana | Lecture Notes in Artificial Intelligence |
| Soggetto topico |
Intelligent agents (Computer software)
Formal methods (Computer science) |
| ISBN | 3-540-46581-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Formal Models of Agents: An Introduction -- A Model of BDI-Agent in Game-Theoretic Framework -- Dynamic Belief Hierarchies -- Modelling Internal Dynamic Behaviour of BDI Agents -- Towards an Agent-Oriented Framework for Specification of Information Systems -- The Impossibility of Modelling Cooperation in PD-Game -- Designing Multi-agent Systems around an Extensible Communication Abstraction -- Social Interactions of Autonomous Agents: Private and Global Views on Communication -- Towards a Proof-Theoretic Foundation for Actor Specification and Verification -- Nondeterministic Actions with Typical Effects: Reasoning about Scenarios -- Agents’ Dynamic Mental Attitudes -- Diagnostic Agents for Distributed Systems -- Preferential Action Semantics (Preliminary Report) -- Dialectical proof theory for defeasible argumentation with defeasible priorities (preliminary report) -- The Role of Diagnosis and Decision Theory in Normative Reasoning -- Contextual Deontic Logic. |
| Record Nr. | UNINA-9910143639103321 |
| Berlin ; ; Heidelberg : , : Springer, , [2000] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Formal models of agents : ESPRIT Project ModelAge final report / / John-Jules Ch. Meyer, Pierre-Yves Schobbens, editors
| Formal models of agents : ESPRIT Project ModelAge final report / / John-Jules Ch. Meyer, Pierre-Yves Schobbens, editors |
| Edizione | [1st ed. 1999.] |
| Pubbl/distr/stampa | Berlin ; ; Heidelberg : , : Springer, , [2000] |
| Descrizione fisica | 1 online resource (VIII, 260 p.) |
| Disciplina | 006.30285436 |
| Collana | Lecture Notes in Artificial Intelligence |
| Soggetto topico |
Intelligent agents (Computer software)
Formal methods (Computer science) |
| ISBN | 3-540-46581-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Formal Models of Agents: An Introduction -- A Model of BDI-Agent in Game-Theoretic Framework -- Dynamic Belief Hierarchies -- Modelling Internal Dynamic Behaviour of BDI Agents -- Towards an Agent-Oriented Framework for Specification of Information Systems -- The Impossibility of Modelling Cooperation in PD-Game -- Designing Multi-agent Systems around an Extensible Communication Abstraction -- Social Interactions of Autonomous Agents: Private and Global Views on Communication -- Towards a Proof-Theoretic Foundation for Actor Specification and Verification -- Nondeterministic Actions with Typical Effects: Reasoning about Scenarios -- Agents’ Dynamic Mental Attitudes -- Diagnostic Agents for Distributed Systems -- Preferential Action Semantics (Preliminary Report) -- Dialectical proof theory for defeasible argumentation with defeasible priorities (preliminary report) -- The Role of Diagnosis and Decision Theory in Normative Reasoning -- Contextual Deontic Logic. |
| Record Nr. | UNISA-996465584003316 |
| Berlin ; ; Heidelberg : , : Springer, , [2000] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Formal techniques for distributed objects, components, and systems : 42nd IFIP WG 6.1 International Conference, FORTE 2022, held as part of the 17th International Federated Conference on Distributed Computing Techniques, DisCoTec 2022, Lucca, Italy, June 13-18, 2022, proceedings / / Mohammad Reza Mousavi, Anna Philippou, editors
| Formal techniques for distributed objects, components, and systems : 42nd IFIP WG 6.1 International Conference, FORTE 2022, held as part of the 17th International Federated Conference on Distributed Computing Techniques, DisCoTec 2022, Lucca, Italy, June 13-18, 2022, proceedings / / Mohammad Reza Mousavi, Anna Philippou, editors |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , [2022] |
| Descrizione fisica | 1 online resource (222 pages) |
| Disciplina | 004.36 |
| Collana | Lecture notes in computer science |
| Soggetto topico |
Electronic data processing - Distributed processing
Formal methods (Computer science) Software engineering |
| ISBN | 3-031-08679-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996478867303316 |
| Cham, Switzerland : , : Springer, , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
