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Designing embedded systems with PIC microcontrollers [[electronic resource] ] : principles and applications / / Tim Wilmshurst
| Designing embedded systems with PIC microcontrollers [[electronic resource] ] : principles and applications / / Tim Wilmshurst |
| Autore | Wilmshurst Tim |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston ; ; London, : Newnes, 2007 |
| Descrizione fisica | 1 online resource (583 p.) |
| Disciplina | 004.16 |
| Soggetto topico |
Embedded computer systems - Design and construction
Microprocessors - Design and construction |
| ISBN |
1-280-74740-4
9786610747405 0-08-046814-4 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front cover; Title page; Copyright page; Table of contents; Introduction; Acknowledgements; Section 1 Getting Started with Embedded Systems; 1 Tiny computers, hidden control; 1.1 The main idea - embedded systems in today's world; 1.1.1 What is an embedded system?; 1.2 Some example embedded systems; 1.2.1 The domestic refrigerator; 1.2.2 A car door mechanism; 1.2.3 The electronic 'ping-pong'; 1.2.4 The Derbot Autonomous Guided Vehicle; 1.3 Some computer essentials; 1.3.1 Elements of a computer; 1.3.2 Instruction sets - CISC and RISC; 1.3.3 Memory types; 1.3.4 Organising memory
1.4 Microprocessors and microcontrollers 1.4.1 Microprocessors; 1.4.2 Microcontrollers; 1.4.3 Microcontroller families; 1.4.4 Microcontroller packaging and appearance; 1.5 Microchip and the PIC microcontroller; 1.5.1 Background; 1.5.2 PIC microcontrollers today; 1.6 An introduction to PIC microcontrollers using the 12 Series; 1.6.1 The 12F508 architecture; 1.7 What others do - a Freescale microcontroller; Summary; References; Section 2 Minimum Systems and the PIC® 16F84A; 2 Introducing the PIC® 16 Series and the 16F84A; 2.1 The main idea - the PIC 16 Series family; 2.1.1 A family overview 2.1.2 The 16F84A 2.1.3 A caution on upgrades; 2.2 An architecture overview of the 16F84A; 2.2.1 The Status register; 2.3 A review of memory technologies; 2.3.1 Static RAM (SRAM); 2.3.2 EPROM (Erasable Programmable Read-Only Memory); 2.3.3 EEPROM (Electrically Erasable Programmable Read-Only Memory); 2.3.4 Flash; 2.4 The 16F84A memory; 2.4.1 The 16F84A program memory; 2.4.2 The 16F84A data and Special Function Register memory ('RAM'); 2.4.3 The Configuration Word; 2.4.4 EEPROM; 2.5 Some issues of timing; 2.5.1 Clock oscillator and instruction cycle; 2.5.2 Pipelining; 2.6 Power-up and Reset 2.7 What others do - the Atmel AT89C2051 2.8 Taking things further - the 16F84A on-chip reset circuit; Summary; References; 3 Parallel ports, power supply and the clock oscillator; 3.1 The main idea - parallel input/output; 3.2 The technical challenge of parallel input/output; 3.2.1 Building a parallel interface; 3.2.2 Port electrical characteristics; 3.2.3 Some special cases; 3.3 Connecting to the parallel port; 3.3.1 Switches; 3.3.2 Light-emitting diodes; 3.4 The PIC 16F84A parallel ports; 3.4.1 The 16F84A Port B; 3.4.2 The 16F84A Port A; 3.4.3 Port output characteristics 3.5 The clock oscillator 3.5.1 Clock oscillator types; 3.5.2 Practical oscillator considerations; 3.5.3 The 16F84A clock oscillator; 3.6 Power supply; 3.6.1 The need for power, and its sources; 3.6.2 16F84A operating conditions; 3.7 The hardware design of the electronic ping-pong; Summary; References; 4 Starting to program - an introduction to Assembler; 4.1 The main idea - what programs do and how we develop them; 4.1.1 The problem of programming and the Assembler compromise; 4.1.2 The process of writing in Assembler; 4.1.3 The program development process 4.2 The PIC 16 Series instruction set, with a little more on the ALU |
| Record Nr. | UNINA-9910784459903321 |
Wilmshurst Tim
|
||
| Amsterdam ; ; Boston ; ; London, : Newnes, 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Designing embedded systems with PIC microcontrollers : principles and applications / / Tim Wilmshurst
| Designing embedded systems with PIC microcontrollers : principles and applications / / Tim Wilmshurst |
| Autore | Wilmshurst Tim |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston ; ; London, : Newnes, 2007 |
| Descrizione fisica | 1 online resource (583 p.) |
| Disciplina | 004.16 |
| Soggetto topico |
Embedded computer systems - Design and construction
Microprocessors - Design and construction |
| ISBN |
1-280-74740-4
9786610747405 0-08-046814-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front cover; Title page; Copyright page; Table of contents; Introduction; Acknowledgements; Section 1 Getting Started with Embedded Systems; 1 Tiny computers, hidden control; 1.1 The main idea - embedded systems in today's world; 1.1.1 What is an embedded system?; 1.2 Some example embedded systems; 1.2.1 The domestic refrigerator; 1.2.2 A car door mechanism; 1.2.3 The electronic 'ping-pong'; 1.2.4 The Derbot Autonomous Guided Vehicle; 1.3 Some computer essentials; 1.3.1 Elements of a computer; 1.3.2 Instruction sets - CISC and RISC; 1.3.3 Memory types; 1.3.4 Organising memory
1.4 Microprocessors and microcontrollers 1.4.1 Microprocessors; 1.4.2 Microcontrollers; 1.4.3 Microcontroller families; 1.4.4 Microcontroller packaging and appearance; 1.5 Microchip and the PIC microcontroller; 1.5.1 Background; 1.5.2 PIC microcontrollers today; 1.6 An introduction to PIC microcontrollers using the 12 Series; 1.6.1 The 12F508 architecture; 1.7 What others do - a Freescale microcontroller; Summary; References; Section 2 Minimum Systems and the PIC® 16F84A; 2 Introducing the PIC® 16 Series and the 16F84A; 2.1 The main idea - the PIC 16 Series family; 2.1.1 A family overview 2.1.2 The 16F84A 2.1.3 A caution on upgrades; 2.2 An architecture overview of the 16F84A; 2.2.1 The Status register; 2.3 A review of memory technologies; 2.3.1 Static RAM (SRAM); 2.3.2 EPROM (Erasable Programmable Read-Only Memory); 2.3.3 EEPROM (Electrically Erasable Programmable Read-Only Memory); 2.3.4 Flash; 2.4 The 16F84A memory; 2.4.1 The 16F84A program memory; 2.4.2 The 16F84A data and Special Function Register memory ('RAM'); 2.4.3 The Configuration Word; 2.4.4 EEPROM; 2.5 Some issues of timing; 2.5.1 Clock oscillator and instruction cycle; 2.5.2 Pipelining; 2.6 Power-up and Reset 2.7 What others do - the Atmel AT89C2051 2.8 Taking things further - the 16F84A on-chip reset circuit; Summary; References; 3 Parallel ports, power supply and the clock oscillator; 3.1 The main idea - parallel input/output; 3.2 The technical challenge of parallel input/output; 3.2.1 Building a parallel interface; 3.2.2 Port electrical characteristics; 3.2.3 Some special cases; 3.3 Connecting to the parallel port; 3.3.1 Switches; 3.3.2 Light-emitting diodes; 3.4 The PIC 16F84A parallel ports; 3.4.1 The 16F84A Port B; 3.4.2 The 16F84A Port A; 3.4.3 Port output characteristics 3.5 The clock oscillator 3.5.1 Clock oscillator types; 3.5.2 Practical oscillator considerations; 3.5.3 The 16F84A clock oscillator; 3.6 Power supply; 3.6.1 The need for power, and its sources; 3.6.2 16F84A operating conditions; 3.7 The hardware design of the electronic ping-pong; Summary; References; 4 Starting to program - an introduction to Assembler; 4.1 The main idea - what programs do and how we develop them; 4.1.1 The problem of programming and the Assembler compromise; 4.1.2 The process of writing in Assembler; 4.1.3 The program development process 4.2 The PIC 16 Series instruction set, with a little more on the ALU |
| Record Nr. | UNINA-9910811285803321 |
|
Wilmshurst Tim
|
||
| Amsterdam ; ; Boston ; ; London, : Newnes, 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Designing SOCs with configured cores [[electronic resource] ] : unleashing the Tensilica Xtensa and diamond cores / / Steve Leibson
| Designing SOCs with configured cores [[electronic resource] ] : unleashing the Tensilica Xtensa and diamond cores / / Steve Leibson |
| Autore | Leibson Steve |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2006 |
| Descrizione fisica | 1 online resource (341 p.) |
| Disciplina | 621.3815 |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Embedded computer systems - Design and construction
Systems on a chip - Design and construction |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-280-96685-8
9786610966851 0-08-047245-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; About the Author; Title page; Copyright Page; Table of contents; Foreword; Preface; Acknowledgements; 1 Introduction to 21st-Century SOC Design; 1.1 The Start of Something Big; 1.2 Few Pins = Massive Multiplexing; 1.3 Third Time's a Charm; 1.4 The Microprocessor: A Universal System Building Block; 1.5 The Consequences of Performance-in the Macro World; 1.6 Increasing Processor Performance in the Micro World; 1.7 I/O Bandwidth and Processor Core Clock Rate; 1.8 Multitasking and Processor Core Clock Rate; 1.9 System-Design Evolution
1.10 Heterogeneous- and Homogeneous-Processor System-Design Approaches1.11 The Rise of MPSOC Design; 1.12 Veering Away from Processor Multitasking in SOC Design; 1.13 Processors: The Original, Reusable Design Block; 1.14 A Closer Look at 21st-Century Processor Cores for SOC Design; Bibliography; 2 The SOC Design Flow; 2.1 System-Design Goals; 2.2 The ASIC Design Flow; 2.3 The ad-hoc SOC Design Flow; 2.4 A Systematic MPSOC Design Flow; 2.5 Computational Alternatives; 2.6 Communication Alternatives; 2.7 Cycle-Accurate System Simulation; 2.8 Detailed Implementation 2.9 Summary: Handling SOC ComplexityBibliography; 3 Xtensa Architectural Basics; 3.1 Introduction to Configurable Processor Architectures; 3.2 Xtensa Registers; 3.3 Register Windowing; 3.4 The Xtensa Program Counter; 3.5 Memory Address Space; 3.6 Bit and Byte Ordering; 3.7 Base Xtensa Instructions; 3.8 Benchmarking the Xtensa Core ISA; Bibliography; 4 Basic Processor Configurability; 4.1 Processor Generation; 4.2 Xtensa Processor Block Diagram; 4.3 Pre-Configured Processor Cores; 4.4 Basics of TIE; 4.5 TIE Instructions; 4.6 Improving Application Performance Using TIE 4.7 TIE Registers and Register Files4.8 TIE Ports; 4.9 TIE Queue Interfaces; 4.10 Combining Instruction Extensions with Queues; 4.11 Diamond Standard Series Processor Cores-Dealing with Complexity; Bibliography; 5 MPSOC System Architectures and Design Tools; 5.1 SOC Architectural Evolution; 5.2 The Consequences of Architectural Evolution; 5.3 Memory Interfaces; 5.4 Memory Caches; 5.5 Local ROM and Local RAM Interfaces, the XLMI Port, and the PIF; 5.6 The PIF; 5.7 Ports and Queue Interfaces; 5.8 SOC Connection Topologies; 5.9 Shared-Memory Topologies; 5.10 Direct Port-Connected Topologies 5.11 Queue-Based System Topologies5.12 Existing Design Tools for Complex SOC Designs; 5.13 MPSOC Architectural-Design Tools; 5.14 Platform Design; 5.15 An MPSOC-Design Tool; 5.16 MPSOC System-Level Simulation Example; 5.17 SOC Design in the 21st Century; Bibliography; 6 Introduction to Diamond Standard Series Processor Cores; 6.1 The Diamond Standard Series of 32-bit Processor Cores; 6.2 Diamond Standard Series Software-Development Tools; 6.3 Diamond Standard Series Feature Summary; 6.4 Diamond Standard Series Processor Core Hardware Overview and Comparison 6.5 Diamond-Core Local-Memory Interfaces |
| Record Nr. | UNINA-9910458596803321 |
|
Leibson Steve
|
||
| Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Designing SOCs with configured cores [[electronic resource] ] : unleashing the Tensilica Xtensa and diamond cores / / Steve Leibson
| Designing SOCs with configured cores [[electronic resource] ] : unleashing the Tensilica Xtensa and diamond cores / / Steve Leibson |
| Autore | Leibson Steve |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2006 |
| Descrizione fisica | 1 online resource (341 p.) |
| Disciplina | 621.3815 |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Embedded computer systems - Design and construction
Systems on a chip - Design and construction |
| ISBN |
1-280-96685-8
9786610966851 0-08-047245-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; About the Author; Title page; Copyright Page; Table of contents; Foreword; Preface; Acknowledgements; 1 Introduction to 21st-Century SOC Design; 1.1 The Start of Something Big; 1.2 Few Pins = Massive Multiplexing; 1.3 Third Time's a Charm; 1.4 The Microprocessor: A Universal System Building Block; 1.5 The Consequences of Performance-in the Macro World; 1.6 Increasing Processor Performance in the Micro World; 1.7 I/O Bandwidth and Processor Core Clock Rate; 1.8 Multitasking and Processor Core Clock Rate; 1.9 System-Design Evolution
1.10 Heterogeneous- and Homogeneous-Processor System-Design Approaches1.11 The Rise of MPSOC Design; 1.12 Veering Away from Processor Multitasking in SOC Design; 1.13 Processors: The Original, Reusable Design Block; 1.14 A Closer Look at 21st-Century Processor Cores for SOC Design; Bibliography; 2 The SOC Design Flow; 2.1 System-Design Goals; 2.2 The ASIC Design Flow; 2.3 The ad-hoc SOC Design Flow; 2.4 A Systematic MPSOC Design Flow; 2.5 Computational Alternatives; 2.6 Communication Alternatives; 2.7 Cycle-Accurate System Simulation; 2.8 Detailed Implementation 2.9 Summary: Handling SOC ComplexityBibliography; 3 Xtensa Architectural Basics; 3.1 Introduction to Configurable Processor Architectures; 3.2 Xtensa Registers; 3.3 Register Windowing; 3.4 The Xtensa Program Counter; 3.5 Memory Address Space; 3.6 Bit and Byte Ordering; 3.7 Base Xtensa Instructions; 3.8 Benchmarking the Xtensa Core ISA; Bibliography; 4 Basic Processor Configurability; 4.1 Processor Generation; 4.2 Xtensa Processor Block Diagram; 4.3 Pre-Configured Processor Cores; 4.4 Basics of TIE; 4.5 TIE Instructions; 4.6 Improving Application Performance Using TIE 4.7 TIE Registers and Register Files4.8 TIE Ports; 4.9 TIE Queue Interfaces; 4.10 Combining Instruction Extensions with Queues; 4.11 Diamond Standard Series Processor Cores-Dealing with Complexity; Bibliography; 5 MPSOC System Architectures and Design Tools; 5.1 SOC Architectural Evolution; 5.2 The Consequences of Architectural Evolution; 5.3 Memory Interfaces; 5.4 Memory Caches; 5.5 Local ROM and Local RAM Interfaces, the XLMI Port, and the PIF; 5.6 The PIF; 5.7 Ports and Queue Interfaces; 5.8 SOC Connection Topologies; 5.9 Shared-Memory Topologies; 5.10 Direct Port-Connected Topologies 5.11 Queue-Based System Topologies5.12 Existing Design Tools for Complex SOC Designs; 5.13 MPSOC Architectural-Design Tools; 5.14 Platform Design; 5.15 An MPSOC-Design Tool; 5.16 MPSOC System-Level Simulation Example; 5.17 SOC Design in the 21st Century; Bibliography; 6 Introduction to Diamond Standard Series Processor Cores; 6.1 The Diamond Standard Series of 32-bit Processor Cores; 6.2 Diamond Standard Series Software-Development Tools; 6.3 Diamond Standard Series Feature Summary; 6.4 Diamond Standard Series Processor Core Hardware Overview and Comparison 6.5 Diamond-Core Local-Memory Interfaces |
| Record Nr. | UNINA-9910784654303321 |
|
Leibson Steve
|
||
| Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Designing SOCs with configured cores : unleashing the Tensilica Xtensa and diamond cores / / Steve Leibson
| Designing SOCs with configured cores : unleashing the Tensilica Xtensa and diamond cores / / Steve Leibson |
| Autore | Leibson Steve |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2006 |
| Descrizione fisica | 1 online resource (341 p.) |
| Disciplina | 621.3815 |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Embedded computer systems - Design and construction
Systems on a chip - Design and construction |
| ISBN |
1-280-96685-8
9786610966851 0-08-047245-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; About the Author; Title page; Copyright Page; Table of contents; Foreword; Preface; Acknowledgements; 1 Introduction to 21st-Century SOC Design; 1.1 The Start of Something Big; 1.2 Few Pins = Massive Multiplexing; 1.3 Third Time's a Charm; 1.4 The Microprocessor: A Universal System Building Block; 1.5 The Consequences of Performance-in the Macro World; 1.6 Increasing Processor Performance in the Micro World; 1.7 I/O Bandwidth and Processor Core Clock Rate; 1.8 Multitasking and Processor Core Clock Rate; 1.9 System-Design Evolution
1.10 Heterogeneous- and Homogeneous-Processor System-Design Approaches1.11 The Rise of MPSOC Design; 1.12 Veering Away from Processor Multitasking in SOC Design; 1.13 Processors: The Original, Reusable Design Block; 1.14 A Closer Look at 21st-Century Processor Cores for SOC Design; Bibliography; 2 The SOC Design Flow; 2.1 System-Design Goals; 2.2 The ASIC Design Flow; 2.3 The ad-hoc SOC Design Flow; 2.4 A Systematic MPSOC Design Flow; 2.5 Computational Alternatives; 2.6 Communication Alternatives; 2.7 Cycle-Accurate System Simulation; 2.8 Detailed Implementation 2.9 Summary: Handling SOC ComplexityBibliography; 3 Xtensa Architectural Basics; 3.1 Introduction to Configurable Processor Architectures; 3.2 Xtensa Registers; 3.3 Register Windowing; 3.4 The Xtensa Program Counter; 3.5 Memory Address Space; 3.6 Bit and Byte Ordering; 3.7 Base Xtensa Instructions; 3.8 Benchmarking the Xtensa Core ISA; Bibliography; 4 Basic Processor Configurability; 4.1 Processor Generation; 4.2 Xtensa Processor Block Diagram; 4.3 Pre-Configured Processor Cores; 4.4 Basics of TIE; 4.5 TIE Instructions; 4.6 Improving Application Performance Using TIE 4.7 TIE Registers and Register Files4.8 TIE Ports; 4.9 TIE Queue Interfaces; 4.10 Combining Instruction Extensions with Queues; 4.11 Diamond Standard Series Processor Cores-Dealing with Complexity; Bibliography; 5 MPSOC System Architectures and Design Tools; 5.1 SOC Architectural Evolution; 5.2 The Consequences of Architectural Evolution; 5.3 Memory Interfaces; 5.4 Memory Caches; 5.5 Local ROM and Local RAM Interfaces, the XLMI Port, and the PIF; 5.6 The PIF; 5.7 Ports and Queue Interfaces; 5.8 SOC Connection Topologies; 5.9 Shared-Memory Topologies; 5.10 Direct Port-Connected Topologies 5.11 Queue-Based System Topologies5.12 Existing Design Tools for Complex SOC Designs; 5.13 MPSOC Architectural-Design Tools; 5.14 Platform Design; 5.15 An MPSOC-Design Tool; 5.16 MPSOC System-Level Simulation Example; 5.17 SOC Design in the 21st Century; Bibliography; 6 Introduction to Diamond Standard Series Processor Cores; 6.1 The Diamond Standard Series of 32-bit Processor Cores; 6.2 Diamond Standard Series Software-Development Tools; 6.3 Diamond Standard Series Feature Summary; 6.4 Diamond Standard Series Processor Core Hardware Overview and Comparison 6.5 Diamond-Core Local-Memory Interfaces |
| Record Nr. | UNINA-9910808929603321 |
|
Leibson Steve
|
||
| Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
EDERC 2010 : proceedings : European DSP in Education and Research Conference
| EDERC 2010 : proceedings : European DSP in Education and Research Conference |
| Pubbl/distr/stampa | New York : , : IEEE, , 2012 |
| Descrizione fisica | 1 online resource (155 pages) |
| Soggetto topico |
Signal processing - Digital techniques
Embedded computer systems - Design and construction |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996206835803316 |
| New York : , : IEEE, , 2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
EDERC 2010 : proceedings : European DSP in Education and Research Conference
| EDERC 2010 : proceedings : European DSP in Education and Research Conference |
| Pubbl/distr/stampa | New York : , : IEEE, , 2012 |
| Descrizione fisica | 1 online resource (155 pages) |
| Soggetto topico |
Signal processing - Digital techniques
Embedded computer systems - Design and construction |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910141173003321 |
| New York : , : IEEE, , 2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Embedded computer systems : architectures, modeling, and simulation : 22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022, proceedings / / Alex Orailoglu, Marc Reichenbach, and Matthias Jung, editors
| Embedded computer systems : architectures, modeling, and simulation : 22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022, proceedings / / Alex Orailoglu, Marc Reichenbach, and Matthias Jung, editors |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer International Publishing, , [2022] |
| Descrizione fisica | 1 online resource (434 pages) |
| Disciplina | 004.16 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Embedded computer systems
Embedded computer systems - Design and construction |
| ISBN | 3-031-15074-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Preface -- Organization -- Contents -- High Level Synthesis -- High-Level Synthesis of Digital Circuits from Template Haskell and SDF-AP -- 1 Introduction -- 2 Related Work -- 2.1 High-Level Synthesis Tools -- 2.2 Temporal Models for Hardware Design -- 3 SDF-AP -- 4 From Functional Description to SDF-AP -- 4.1 Template Haskell: The Toolflow -- 4.2 Conformance Relation -- 4.3 The Basic Idea of Combining SDF-AP with a Functional Language -- 4.4 The Advantages -- 4.5 The Current Limitations -- 5 Node Decomposition -- 6 Case Studies -- 6.1 Dot Product Case Study -- 6.2 Center of Mass Case Study -- 6.3 DCT2D Case Study -- 7 Conclusion -- References -- Implementing Synthetic Aperture Radar Backprojection in Chisel - A Field Report -- 1 Introduction -- 2 System Description -- 2.1 Synthetic Aperture Radar (SAR) -- 2.2 Backprojection (BP) -- 2.3 Architecture Overview -- 3 Measurements -- 3.1 Code Size -- 3.2 Transparency of Generated Code -- 4 Experience Using Chisel -- 5 Conclusion -- A Code Examples -- A.1 Chisel Code -- A.2 VHDL Code -- References -- EasyHBM: Simple and Fast HBM Access for FPGAs Using High-Level-Synthesis -- 1 Introduction -- 2 Related Work -- 3 Methodology -- 4 Architecture -- 4.1 PE High-Level Synthesis -- 4.2 HBM Connection -- 5 Evaluation -- 5.1 Design Complexity -- 5.2 Setup Overhead -- 5.3 Performance -- 6 Conclusion -- References -- Memory Systems -- TREAM: A Tool for Evaluating Error Resilience of Tree-Based Models Using Approximate Memory -- 1 Introduction -- 2 System Model -- 2.1 Memory and Error Model -- 2.2 Definitions for Error Resilience -- 2.3 Research Questions -- 3 TREAM: An Extension to Sklearn -- 3.1 High-Level Overview of TREAM -- 3.2 Implementation -- 4 The Effect of Bit Flips in Tree-Based Models -- 4.1 Bit Flips in Split and Feature Value -- 4.2 Bit Flips in Child Indices.
4.3 Bit Flips in Feature Index -- 5 Evaluation -- 6 Conclusion -- References -- Split'n'Cover: ISO26262 Hardware Safety Analysis with SystemC -- 1 Introduction -- 2 Background -- 3 Related Work -- 4 Methodology -- 5 Implementation -- 6 Experimental Case Study and Results -- 7 Conclusion and Future Work -- References -- Tagged Geometric History Length Access Interval Prediction for Tightly Coupled Memory Systems -- 1 Introduction -- 2 Background and Related Work -- 3 Access Interval Prediction -- 3.1 System Overview -- 3.2 Theory and Notation -- 4 TAGE Access Interval Predictor -- 4.1 Design -- 4.2 Interval Representation -- 4.3 Subprediction and Update Method -- 5 Performance Evaluation -- 5.1 Interval Representation -- 5.2 Subprediction and Update Method -- 5.3 Comparison -- 6 Conclusion and Outlook -- References -- Processor Architecture -- NanoController: A Minimal and Flexible Processor Architecture for Ultra-Low-Power Always-On System State Controllers -- 1 Introduction -- 2 Related Work -- 3 NanoController Architecture -- 3.1 Data Path -- 3.2 Control Path and ISA -- 3.3 Program Code Generation -- 4 Evaluation -- 4.1 Exemplary Control Application -- 4.2 Code Size Comparison -- 4.3 Performance Comparison -- 4.4 Silicon Area and Power/Energy Consumption -- 5 Conclusion -- References -- ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration -- 1 Introduction -- 2 Related Work -- 3 The ControlPULP Platform -- 3.1 System Architecture -- 3.2 Power Control Firmware -- 4 Experimental Results -- 4.1 Area Evaluation -- 4.2 Firmware Control Action -- 4.3 In-band Services -- 4.4 System-Level PCF Step Evaluation -- 4.5 Control-Level PCF Step Evaluation -- 5 Conclusion -- References -- Embedded Software Systems and Beyond. CASA: An Approach for Exposing and Documenting Concurrency-Related Software Properties -- 1 Introduction -- 2 Related Work -- 3 Exposing and Documenting Concurrency-Related Software Architecture Decisions -- 3.1 Guideline for Identification of Concurrency-Critical Components (GICCS) -- 3.2 Documentation of Synchronisation Mechanisms -- 3.3 Testing of Concurrent Software with CASA's Support -- 4 Integration of CASA in Agile SCRUM -- 5 Evaluation -- 5.1 Setup I: Reverse Engineering of Synchronisation Decisions in Industrial Environment -- 5.2 Setup II: Survey with Software Engineering Professionals -- 5.3 Threats to Validity -- 6 Conclusion -- References -- High-Level Simulation of Embedded Software Vulnerabilities to EM Side-Channel Attacks -- 1 Introduction -- 2 Related Work -- 3 EM Synthesis Flow -- 3.1 Dictionary Construction -- 3.2 Synthesis -- 4 Experiments -- 4.1 Accuracy and Dictionary Cost -- 4.2 Case Study: Compile-Time Control Flow Prediction -- 5 Summary and Conclusions -- References -- Deep Learning Optimization I -- A Design Space Exploration Methodology for Enabling Tensor Train Decomposition in Edge Devices -- 1 Introduction -- 2 Background and Related Works -- 2.1 Low-Rank Factorization -- 2.2 Tensor-Train (TT) Format and T3F Library -- 2.3 Motivation -- 3 Methodology -- 4 Experimental Results -- 5 Conclusion -- References -- Study of DNN-Based Ragweed Detection from Drones -- 1 Introduction -- 2 Related Work -- 2.1 Weed Detection and Eradication -- 2.2 Deep Learning and Model Compression -- 3 System Architecture -- 3.1 Ground Sampling Distance -- 3.2 Flight Parameter Model -- 3.3 Dataset -- 3.4 Object Detection Network -- 3.5 Semantic Segmentation Network -- 4 Results -- 4.1 Drone Selection -- 4.2 Experimental Setup -- 5 Conclusion and Future Work -- References. PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning -- 1 Introduction -- 2 Related Work -- 3 On-Device Training on PULP -- 3.1 The PULP Platform -- 3.2 PULP-TrainLib Library -- 3.3 Accelerating SW Training Primitives -- 3.4 AutoTuner -- 4 Experimental Results -- 4.1 Latency Optimization on PULP-TrainLib -- 4.2 Effect of Tensor Shapes on AutoTuning -- 4.3 TinyML Benchmark Training -- 4.4 Comparison with the State of the Art -- 5 Conclusion -- References -- Extra-Functional Property Estimation -- The Impact of Dynamic Storage Allocation on CPython Execution Time, Memory Footprint and Energy Consumption: An Empirical Study -- 1 Introduction -- 1.1 Contributions -- 2 Method -- 3 Experimental Setup -- 3.1 Rationale -- 3.2 PGO, LTO Sensitivity -- 3.3 Configuration Points -- 3.4 Benchmarking Script -- 3.5 Platform Independence -- 4 Results -- 4.1 Discussion -- 5 Limitations -- 6 Related Work -- 7 Conclusions -- References -- Application Runtime Estimation for AURIX Embedded MCU Using Deep Learning -- 1 Introduction -- 1.1 Performance Modeling Approaches -- 1.2 Structure of the Paper -- 2 Related Work -- 3 Methodology -- 3.1 Mechanistic Model, Based on QEMU -- 3.2 Using Artificial Neural Networks for Performance Estimation -- 4 Training Data -- 4.1 Preprocessing of the Training Data -- 4.2 Analysis of the Training Data -- 5 Evaluation -- 5.1 Hyperparameter Search -- 5.2 Architectures Chosen for the Evaluation with Program Traces -- 6 Conclusion and Outlook -- References -- A Hybrid Performance Prediction Approach for Fully-Connected Artificial Neural Networks on Multi-core Platforms -- 1 Introduction -- 2 Related Work -- 3 Proposed Modeling Approach -- 3.1 Target Application: Fully-Connected ANNs -- 3.2 Modeling ANNs with SDF -- 3.3 Mapping on the Targeted Architecture -- 3.4 Computation Time Model. 3.5 Simulation Using SystemC Models -- 4 Experiments -- 4.1 Testing Configuration -- 4.2 Experiment Results -- 4.3 Exploration of Partitionings and Mappings -- 5 Conclusion -- References -- Deep Learning Optimization II -- A Smart HW-Accelerator for Non-uniform Linear Interpolation of ML-Activation Functions -- 1 Introduction -- 2 Related Work -- 2.1 Lookup Table Approximation -- 2.2 Piecewise Linear Approximation (PWL) -- 2.3 Piecewise Nonlinear Approximation (PWNL) -- 2.4 CORDIC -- 3 Proposed Approach -- 3.1 Overview -- 3.2 HW Generator -- 3.3 Integrated Features -- 3.4 Software Preprocessing -- 3.5 Proposed Architecture -- 3.6 Multiplier Optimizations -- 4 Experimental Results -- 4.1 Optimized Search for Interpolation Points -- 4.2 Optimized Generated Hardware -- 4.3 Comparison with Similar Works -- 5 Conclusion -- 6 Future Work -- References -- Hardware-Aware Evolutionary Filter Pruning -- 1 Introduction -- 2 Related Work -- 3 Fundamentals -- 3.1 Filter Pruning of CNNs -- 3.2 Inference Time Analysis of Convolutional Layers on GPUs -- 4 Design Space Exploration -- 4.1 Search Strategies -- 5 Experiments -- 5.1 Influence of Number of Groups G -- 5.2 VGG-11 and VGG-16 on CIFAR-10 -- 5.3 Retraining with Reduced Data Set During DSE -- 5.4 ResNet-18 and ResNet-101 on ILSVRC-2012 -- 6 Conclusion -- References -- Innovative Architectures and Tools for Security -- Obfuscating the Hierarchy of a Digital IP -- 1 Introduction -- 2 Proposed Approach -- 2.1 Motivation and Background -- 2.2 Hierarchical Obfuscation -- 3 Results -- 3.1 Power-Performance-Area Evaluations -- 3.2 Security Analysis -- 4 Conclusion -- References -- On the Effectiveness of True Random Number Generators Implemented on FPGAs -- 1 Introduction -- 2 Methodology -- 2.1 Digital Noise Sources -- 2.2 Post-processing Methods -- 3 Experimental Evaluation -- 3.1 Setup -- 3.2 Resource Utilization. 3.3 Throughput. |
| Record Nr. | UNISA-996485668903316 |
| Cham, Switzerland : , : Springer International Publishing, , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Embedded computer systems : architectures, modeling, and simulation : 22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022, proceedings / / Alex Orailoglu, Marc Reichenbach, and Matthias Jung, editors
| Embedded computer systems : architectures, modeling, and simulation : 22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022, proceedings / / Alex Orailoglu, Marc Reichenbach, and Matthias Jung, editors |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer International Publishing, , [2022] |
| Descrizione fisica | 1 online resource (434 pages) |
| Disciplina | 004.16 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Embedded computer systems
Embedded computer systems - Design and construction |
| ISBN | 3-031-15074-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Preface -- Organization -- Contents -- High Level Synthesis -- High-Level Synthesis of Digital Circuits from Template Haskell and SDF-AP -- 1 Introduction -- 2 Related Work -- 2.1 High-Level Synthesis Tools -- 2.2 Temporal Models for Hardware Design -- 3 SDF-AP -- 4 From Functional Description to SDF-AP -- 4.1 Template Haskell: The Toolflow -- 4.2 Conformance Relation -- 4.3 The Basic Idea of Combining SDF-AP with a Functional Language -- 4.4 The Advantages -- 4.5 The Current Limitations -- 5 Node Decomposition -- 6 Case Studies -- 6.1 Dot Product Case Study -- 6.2 Center of Mass Case Study -- 6.3 DCT2D Case Study -- 7 Conclusion -- References -- Implementing Synthetic Aperture Radar Backprojection in Chisel - A Field Report -- 1 Introduction -- 2 System Description -- 2.1 Synthetic Aperture Radar (SAR) -- 2.2 Backprojection (BP) -- 2.3 Architecture Overview -- 3 Measurements -- 3.1 Code Size -- 3.2 Transparency of Generated Code -- 4 Experience Using Chisel -- 5 Conclusion -- A Code Examples -- A.1 Chisel Code -- A.2 VHDL Code -- References -- EasyHBM: Simple and Fast HBM Access for FPGAs Using High-Level-Synthesis -- 1 Introduction -- 2 Related Work -- 3 Methodology -- 4 Architecture -- 4.1 PE High-Level Synthesis -- 4.2 HBM Connection -- 5 Evaluation -- 5.1 Design Complexity -- 5.2 Setup Overhead -- 5.3 Performance -- 6 Conclusion -- References -- Memory Systems -- TREAM: A Tool for Evaluating Error Resilience of Tree-Based Models Using Approximate Memory -- 1 Introduction -- 2 System Model -- 2.1 Memory and Error Model -- 2.2 Definitions for Error Resilience -- 2.3 Research Questions -- 3 TREAM: An Extension to Sklearn -- 3.1 High-Level Overview of TREAM -- 3.2 Implementation -- 4 The Effect of Bit Flips in Tree-Based Models -- 4.1 Bit Flips in Split and Feature Value -- 4.2 Bit Flips in Child Indices.
4.3 Bit Flips in Feature Index -- 5 Evaluation -- 6 Conclusion -- References -- Split'n'Cover: ISO26262 Hardware Safety Analysis with SystemC -- 1 Introduction -- 2 Background -- 3 Related Work -- 4 Methodology -- 5 Implementation -- 6 Experimental Case Study and Results -- 7 Conclusion and Future Work -- References -- Tagged Geometric History Length Access Interval Prediction for Tightly Coupled Memory Systems -- 1 Introduction -- 2 Background and Related Work -- 3 Access Interval Prediction -- 3.1 System Overview -- 3.2 Theory and Notation -- 4 TAGE Access Interval Predictor -- 4.1 Design -- 4.2 Interval Representation -- 4.3 Subprediction and Update Method -- 5 Performance Evaluation -- 5.1 Interval Representation -- 5.2 Subprediction and Update Method -- 5.3 Comparison -- 6 Conclusion and Outlook -- References -- Processor Architecture -- NanoController: A Minimal and Flexible Processor Architecture for Ultra-Low-Power Always-On System State Controllers -- 1 Introduction -- 2 Related Work -- 3 NanoController Architecture -- 3.1 Data Path -- 3.2 Control Path and ISA -- 3.3 Program Code Generation -- 4 Evaluation -- 4.1 Exemplary Control Application -- 4.2 Code Size Comparison -- 4.3 Performance Comparison -- 4.4 Silicon Area and Power/Energy Consumption -- 5 Conclusion -- References -- ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration -- 1 Introduction -- 2 Related Work -- 3 The ControlPULP Platform -- 3.1 System Architecture -- 3.2 Power Control Firmware -- 4 Experimental Results -- 4.1 Area Evaluation -- 4.2 Firmware Control Action -- 4.3 In-band Services -- 4.4 System-Level PCF Step Evaluation -- 4.5 Control-Level PCF Step Evaluation -- 5 Conclusion -- References -- Embedded Software Systems and Beyond. CASA: An Approach for Exposing and Documenting Concurrency-Related Software Properties -- 1 Introduction -- 2 Related Work -- 3 Exposing and Documenting Concurrency-Related Software Architecture Decisions -- 3.1 Guideline for Identification of Concurrency-Critical Components (GICCS) -- 3.2 Documentation of Synchronisation Mechanisms -- 3.3 Testing of Concurrent Software with CASA's Support -- 4 Integration of CASA in Agile SCRUM -- 5 Evaluation -- 5.1 Setup I: Reverse Engineering of Synchronisation Decisions in Industrial Environment -- 5.2 Setup II: Survey with Software Engineering Professionals -- 5.3 Threats to Validity -- 6 Conclusion -- References -- High-Level Simulation of Embedded Software Vulnerabilities to EM Side-Channel Attacks -- 1 Introduction -- 2 Related Work -- 3 EM Synthesis Flow -- 3.1 Dictionary Construction -- 3.2 Synthesis -- 4 Experiments -- 4.1 Accuracy and Dictionary Cost -- 4.2 Case Study: Compile-Time Control Flow Prediction -- 5 Summary and Conclusions -- References -- Deep Learning Optimization I -- A Design Space Exploration Methodology for Enabling Tensor Train Decomposition in Edge Devices -- 1 Introduction -- 2 Background and Related Works -- 2.1 Low-Rank Factorization -- 2.2 Tensor-Train (TT) Format and T3F Library -- 2.3 Motivation -- 3 Methodology -- 4 Experimental Results -- 5 Conclusion -- References -- Study of DNN-Based Ragweed Detection from Drones -- 1 Introduction -- 2 Related Work -- 2.1 Weed Detection and Eradication -- 2.2 Deep Learning and Model Compression -- 3 System Architecture -- 3.1 Ground Sampling Distance -- 3.2 Flight Parameter Model -- 3.3 Dataset -- 3.4 Object Detection Network -- 3.5 Semantic Segmentation Network -- 4 Results -- 4.1 Drone Selection -- 4.2 Experimental Setup -- 5 Conclusion and Future Work -- References. PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning -- 1 Introduction -- 2 Related Work -- 3 On-Device Training on PULP -- 3.1 The PULP Platform -- 3.2 PULP-TrainLib Library -- 3.3 Accelerating SW Training Primitives -- 3.4 AutoTuner -- 4 Experimental Results -- 4.1 Latency Optimization on PULP-TrainLib -- 4.2 Effect of Tensor Shapes on AutoTuning -- 4.3 TinyML Benchmark Training -- 4.4 Comparison with the State of the Art -- 5 Conclusion -- References -- Extra-Functional Property Estimation -- The Impact of Dynamic Storage Allocation on CPython Execution Time, Memory Footprint and Energy Consumption: An Empirical Study -- 1 Introduction -- 1.1 Contributions -- 2 Method -- 3 Experimental Setup -- 3.1 Rationale -- 3.2 PGO, LTO Sensitivity -- 3.3 Configuration Points -- 3.4 Benchmarking Script -- 3.5 Platform Independence -- 4 Results -- 4.1 Discussion -- 5 Limitations -- 6 Related Work -- 7 Conclusions -- References -- Application Runtime Estimation for AURIX Embedded MCU Using Deep Learning -- 1 Introduction -- 1.1 Performance Modeling Approaches -- 1.2 Structure of the Paper -- 2 Related Work -- 3 Methodology -- 3.1 Mechanistic Model, Based on QEMU -- 3.2 Using Artificial Neural Networks for Performance Estimation -- 4 Training Data -- 4.1 Preprocessing of the Training Data -- 4.2 Analysis of the Training Data -- 5 Evaluation -- 5.1 Hyperparameter Search -- 5.2 Architectures Chosen for the Evaluation with Program Traces -- 6 Conclusion and Outlook -- References -- A Hybrid Performance Prediction Approach for Fully-Connected Artificial Neural Networks on Multi-core Platforms -- 1 Introduction -- 2 Related Work -- 3 Proposed Modeling Approach -- 3.1 Target Application: Fully-Connected ANNs -- 3.2 Modeling ANNs with SDF -- 3.3 Mapping on the Targeted Architecture -- 3.4 Computation Time Model. 3.5 Simulation Using SystemC Models -- 4 Experiments -- 4.1 Testing Configuration -- 4.2 Experiment Results -- 4.3 Exploration of Partitionings and Mappings -- 5 Conclusion -- References -- Deep Learning Optimization II -- A Smart HW-Accelerator for Non-uniform Linear Interpolation of ML-Activation Functions -- 1 Introduction -- 2 Related Work -- 2.1 Lookup Table Approximation -- 2.2 Piecewise Linear Approximation (PWL) -- 2.3 Piecewise Nonlinear Approximation (PWNL) -- 2.4 CORDIC -- 3 Proposed Approach -- 3.1 Overview -- 3.2 HW Generator -- 3.3 Integrated Features -- 3.4 Software Preprocessing -- 3.5 Proposed Architecture -- 3.6 Multiplier Optimizations -- 4 Experimental Results -- 4.1 Optimized Search for Interpolation Points -- 4.2 Optimized Generated Hardware -- 4.3 Comparison with Similar Works -- 5 Conclusion -- 6 Future Work -- References -- Hardware-Aware Evolutionary Filter Pruning -- 1 Introduction -- 2 Related Work -- 3 Fundamentals -- 3.1 Filter Pruning of CNNs -- 3.2 Inference Time Analysis of Convolutional Layers on GPUs -- 4 Design Space Exploration -- 4.1 Search Strategies -- 5 Experiments -- 5.1 Influence of Number of Groups G -- 5.2 VGG-11 and VGG-16 on CIFAR-10 -- 5.3 Retraining with Reduced Data Set During DSE -- 5.4 ResNet-18 and ResNet-101 on ILSVRC-2012 -- 6 Conclusion -- References -- Innovative Architectures and Tools for Security -- Obfuscating the Hierarchy of a Digital IP -- 1 Introduction -- 2 Proposed Approach -- 2.1 Motivation and Background -- 2.2 Hierarchical Obfuscation -- 3 Results -- 3.1 Power-Performance-Area Evaluations -- 3.2 Security Analysis -- 4 Conclusion -- References -- On the Effectiveness of True Random Number Generators Implemented on FPGAs -- 1 Introduction -- 2 Methodology -- 2.1 Digital Noise Sources -- 2.2 Post-processing Methods -- 3 Experimental Evaluation -- 3.1 Setup -- 3.2 Resource Utilization. 3.3 Throughput. |
| Record Nr. | UNINA-9910586635503321 |
| Cham, Switzerland : , : Springer International Publishing, , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Embedded memory design for multi-core and systems on chip / / Baker Mohammed
| Embedded memory design for multi-core and systems on chip / / Baker Mohammed |
| Autore | Mohammad Baker |
| Edizione | [1st ed. 2014.] |
| Pubbl/distr/stampa | New York : , : Springer, , 2014 |
| Descrizione fisica | 1 online resource (xiii, 95 pages) : illustrations (chiefly color) |
| Disciplina |
004.22
006.2 |
| Collana | Analog Circuits and Signal Processing |
| Soggetto topico |
Embedded computer systems - Design and construction
Multiprocessors Computer storage devices |
| ISBN | 1-4614-8881-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Cache Architecture and Main Blocks -- Embedded Memory Hierarchy -- SRAM Memory Operation and Yield -- Low Power and High Yield SRAM Memory -- Leakage Reduction -- Embedded Memory Verification -- Embedded Memory Design Validation and Design For Test -- Emerging Memory Technology Opportunities and Challenges. |
| Record Nr. | UNINA-9910299492503321 |
|
Mohammad Baker
|
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| New York : , : Springer, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
