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Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009, Proceedings / / edited by Koen Bertels, Nikitas Dimopoulos, Cristina Silvano, Stephan Wong
| Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009, Proceedings / / edited by Koen Bertels, Nikitas Dimopoulos, Cristina Silvano, Stephan Wong |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 |
| Descrizione fisica | 1 online resource (354 p.) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer systems
Computers Microprocessors Computer architecture Computer networks Electronic digital computers—Evaluation Computer System Implementation Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation |
| ISBN |
1-282-33186-8
9786612331862 3-642-03138-2 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Beachnote -- What Else Is Broken? Can We Fix It? -- Architectures for Multimedia -- Programmable and Scalable Architecture for Graphics Processing Units -- The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors -- CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey -- Programmable Accelerators for Reconfigurable Video Decoder -- Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study -- Multiple Description Scalable Coding for Video Transmission over Unreliable Networks -- Multi/Many Cores Architectures -- Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC -- Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture -- Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management -- A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA -- VLSI Architectures Design -- Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing -- Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata -- Prediction in Dynamic SDRAM Controller Policies -- Inversion/Non-inversion Implementation for an 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI -- Architecture Modeling and Exploration Tools -- Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration -- Modeling Scalable SIMD DSPs in LISA -- NoGAP: A Micro Architecture Construction Framework -- A Comparison of NoTA and GENESYS -- Special Session 1: Instruction-Set Customization -- to Instruction-Set Customization -- Constraint-Driven Identification of Application Specific Instructions in the DURASE System -- A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs) -- Runtime Adaptive Extensible Embedded Processors — A Survey -- Special Session 2: The Future of Reconfigurable Computing and Processor Architectures -- to the Future of Reconfigurable Computing and Processor Architectures -- An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems -- Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study -- Reconfigurable Multicore Server Processors for Low Power Operation -- Reconfigurable Computing in the New Age of Parallelism -- Reconfigurable Multithreading Architectures: A Survey -- Special Session 3: Mastering Cell BE and GPU Execution Platforms -- to Mastering Cell BE and GPU Execution Platforms -- Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors -- Implementing Blocked Sparse Matrix-Vector Multiplication on NVIDIA GPUs -- Experiences with Cell-BE and GPU for Tomography -- Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell -- Exploiting Locality on the Cell/B.E. through Bypassing -- Exploiting the Cell/BE Architecture with the StarPU Unified Runtime System. |
| Record Nr. | UNISA-996465602203316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008, Proceedings / / edited by Mladen Berekovic, Nikitas Dimopoulos, Stephan Wong
| Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008, Proceedings / / edited by Mladen Berekovic, Nikitas Dimopoulos, Stephan Wong |
| Edizione | [1st ed. 2008.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 |
| Descrizione fisica | 1 online resource (XVI, 300 p.) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer systems
Computer networks Computer science Computers Microprocessors Computer architecture Electronic digital computers—Evaluation Computer System Implementation Computer Communication Networks Theory of Computation Computer Hardware Processor Architectures System Performance and Evaluation |
| ISBN | 3-540-70550-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Beachnote -- Can They Be Fixed: Some Thoughts After 40 Years in the Business -- Architecture -- On the Benefit of Caching Traffic Flow Data in the Link Buffer -- Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor -- Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic -- Scalable Architecture for Prefix Preserving Anonymization of IP Addresses -- New Frontiers -- Arithmetic Design on Quantum-Dot Cellular Automata Nanotechnology -- Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications -- 802.15.3 Transmitter: A Fast Design Cycle Using OFDM Framework in Bluespec -- SoC -- A Real-Time Programming Model for Heterogeneous MPSoCs -- A Multi-objective and Hierarchical Exploration Tool for SoC Performance Estimation -- A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs -- Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors -- Application Specific -- Area Reliability Trade-Off in Improved Reed Muller Coding -- Efficient Reed-Solomon Iterative Decoder Using Galois Field Instruction Set -- ASIP-eFPGA Architecture for Multioperable GNSS Receivers -- Special Session: System Level Design for Heterogeneous Systems -- to System Level Design for Heterogeneous Systems -- Streaming Systems in FPGAs -- Heterogeneous Design in Functional DIF -- Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study -- Evaluation of ASIPs Design with LISATek -- High Level Loop Transformations for Systematic Signal Processing Embedded Applications -- Memory-Centric Hardware Synthesis from Dataflow Models -- Special Session: Programming Multicores -- to Programming Multicores -- Design Issues in Parallel Array Languages for Shared Memory -- An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency -- Sensors and Sensor Networks -- Climate and Biological Sensor Network -- Monitoring of Environmentally Hazardous Exhaust Emissions from Cars Using Optical Fibre Sensors -- Application Server for Wireless Sensor Networks -- Embedded Software Architecture for Diagnosing Network and Node Failures in Wireless Sensor Networks -- System Modeling and Design -- Signature-Based Calibration of Analytical System-Level Performance Models -- System-Level Design Space Exploration of Dynamic Reconfigurable Architectures -- Intellectual Property Protection for Embedded Sensor Nodes. |
| Record Nr. | UNISA-996466104403316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings / / edited by Stamatis Vassiliadis, Mladen Berekovic, Timo D. Hämäläinen
| Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings / / edited by Stamatis Vassiliadis, Mladen Berekovic, Timo D. Hämäläinen |
| Edizione | [1st ed. 2007.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 |
| Descrizione fisica | 1 online resource (XVII, 470 p.) |
| Disciplina | 004.22 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Computers Microprocessors Computer architecture Computer networks Electronic digital computers—Evaluation Computer systems Theory of Computation Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation Computer System Implementation |
| ISBN | 3-540-73625-5 |
| Classificazione |
DAT 260f
SS 4800 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynotes -- Software Is the Answer But What Is the Question? -- Integrating VLIW Processors with a Network on Chip -- System Modeling and Simulation -- Communication Architecture Simulation on the Virtual Synchronization Framework -- A Model-Driven Automatically-Retargetable Debug Tool for Embedded Systems -- Performance Evaluation of Memory Management Configurations in Linux for an OS-Level Design Space Exploration -- SC2SCFL: Automated SystemC to Translation -- VLSI Architectures -- Model and Validation of Block Cleaning Cost for Flash Memory -- VLSI Architecture for MRF Based Stereo Matching -- Low-Power Twiddle Factor Unit for FFT Computation -- Trade-Offs Between Voltage Scaling and Processor Shutdown for Low-Energy Embedded Multiprocessors -- Scheduling & Programming Models -- An Automatically-Retargetable Time-Constraint-Driven Instruction Scheduler for Post-compiling Optimization of Embedded Code -- Improving TriMedia Cache Performance by Profile Guided Code Reordering -- A Streaming Machine Description and Programming Model -- Multi-processor Architectures -- Mapping and Performance Evaluation for Heterogeneous MP-SoCs Via Packing -- Strategies for Compiling ?TC to Novel Chip Multiprocessors -- Image Quantisation on a Massively Parallel Embedded Processor -- Stream Image Processing on a Dual-Core Embedded System -- Reconfigurable Architectures -- MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing -- FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder -- Evaluating Large System-on-Chip on Multi-FPGA Platform -- Design Space Exploration -- Efficiency Measures for Multimedia SOCs -- On-Chip Bus Modeling for Power and Performance Estimation -- A Framework Introducing Model Reversibility in SoC Design Space Exploration -- Towards Multi-application Workload Modeling in Sesame for System-Level Design Space Exploration -- Processor Components -- Resource Conflict Detection in Simulation of Function Unit Pipelines -- A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing -- High-Bandwidth Address Generation Unit -- An IP Core for Embedded Java Systems -- Embedded Processors -- Parallel Memory Architecture for TTA Processor -- A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable Size -- Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction -- A Study of Energy Saving in Customizable Processors -- SoC for SDR -- Trends in Low Power Handset Software Defined Radio -- Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals -- Area Efficient Fully Programmable Baseband Processors -- The Next Generation Challenge for Software Defined Radio -- Design Methodology for Software Radio Systems -- Power Efficient Co-simulation Framework for a Wireless Application Using Platform Based SoC -- A Comparative Study of Different FFT Architectures for Software Defined Radio -- Wireless Sensors -- Design of 100 ?W Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring -- Tool-Aided Design and Implementation of Indoor Surveillance Wireless Sensor Network -- System Architecture Modeling of an UWB Receiver for Wireless Sensor Network -- An Embedded Platform with Duty-Cycled Radio and Processing Subsystems for Wireless Sensor Networks -- SensorOS: A New Operating System for Time Critical WSN Applications -- Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor Networks -- k ?+? Neigh: An Energy Efficient Topology Control for Wireless Sensor Networks. |
| Record Nr. | UNISA-996466103503316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings / / edited by Stamatis Vassiliadis, Stephan Wong, Timo D. Hämäläinen
| Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings / / edited by Stamatis Vassiliadis, Stephan Wong, Timo D. Hämäläinen |
| Edizione | [1st ed. 2006.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006 |
| Descrizione fisica | 1 online resource (XV, 492 p.) |
| Disciplina | 004.2/2 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer systems
Computers Microprocessors Computer architecture Computer networks Electronic digital computers—Evaluation Computer System Implementation Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation |
| ISBN | 3-540-36411-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynotes -- Reconfigurable Platform for Digital Convergence Terminals -- European Research in Embedded Systems -- System Design and Modeling -- Interface Overheads in Embedded Multimedia Software -- A UML Profile for Asynchronous Hardware Design -- Automated Distribution of UML 2.0 Designed Applications to a Configurable Multiprocessor Platform -- Towards a Transformation Chain Modeling Language -- Key Research Challenges for Successfully Applying MDD Within Real-Time Embedded Software Development -- Domain-Specific Modeling of Power Aware Distributed Real-Time Embedded Systems -- Mining Dynamic Document Spaces with Massively Parallel Embedded Processors -- Efficient Automated Clock Gating Using CoDeL -- An Optimization Methodology for Memory Allocation and Task Scheduling in SoCs Via Linear Programming -- Wireless Sensor Networks -- Designing Wireless Sensor Nodes -- Design, Implementation, and Experiments on Outdoor Deployment of Wireless Sensor Network for Environmental Monitoring -- LATONA: An Advanced Server Architecture for Ubiquitous Sensor Network -- An Approach for the Reduction of Power Consumption in Sensor Nodes of Wireless Sensor Networks: Case Analysis of Mica2 -- Energy-Driven Partitioning of Signal Processing Algorithms in Sensor Networks -- Preamble Sense Multiple Access (PSMA) for Impulse Radio Ultra Wideband Sensor Networks -- Security in Wireless Sensor Networks: Considerations and Experiments -- On Security of PAN Wireless Systems -- Processor Design -- Code Size Reduction by Compiler Tuning -- Energy Optimization of a Multi-bank Main Memory -- Probabilistic Modelling and Evaluation of Soft Real-Time Embedded Systems -- Hybrid Functional and Instruction Level Power Modeling for Embedded Processors -- Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform -- Software Pipelining Support for Transport Triggered Architecture Processors -- SAD Prefetching for MPEG4 Using Flux Caches -- Effects of Program Compression -- Integrated Instruction Scheduling and Fine-Grain Register Allocation for Embedded Processors -- Compilation and Simulation Tool Chain for Memory Aware Energy Optimizations -- A Scalable, Multi-thread, Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme -- Reducing Execution Unit Leakage Power in Embedded Processors -- Memory Architecture Evaluation for Video Encoding on Enhanced Embedded Processors -- Advantages of Java Processors in Cache Performance and Power for Embedded Applications -- Dependable Computing -- CARROT – A Tool for Fast and Accurate Soft Error Rate Estimation -- A Scheduling Strategy for a Real-Time Dependable Organic Middleware -- Autonomous Construction Technology of Community for Achieving High Assurance Service -- Preventing Denial-of-Service Attacks in Shared CMP Caches -- Architectures and Implementations -- A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures -- Real-Time Embedded System for Rear-View Mirror Overtaking Car Monitoring -- Design of Asynchronous Embedded Processor with New Ternary Data Encoding Scheme -- Hardware-Based IP Lookup Using n-Way Set Associative Memory and LPM Comparator -- A Flash File System to Support Fast Mounting for NAND Flash Memory Based Embedded Systems -- Rescheduling for Optimized SHA-1 Calculation -- Software Implementation of WiMAX on the Sandbridge SandBlaster Platform -- High-Radix Addition and Multiplication in the Electron Counting Paradigm Using Single Electron Tunneling Technology -- Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box -- Embedded Sensor Systems -- Integrated Microsystems in Industrial Applications -- A Solid-State 2-D Wind Sensor -- Fault-Tolerant Bus System for Airbag Sensors and Actuators. |
| Record Nr. | UNISA-996465573703316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, Proceedings / / edited by Timo D. Hämäläinen, Andy D. Pimentel, Jarmo Takala, Stamatis Vassiliadis
| Embedded Computer Systems: Architectures, Modeling, and Simulation [[electronic resource] ] : 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, Proceedings / / edited by Timo D. Hämäläinen, Andy D. Pimentel, Jarmo Takala, Stamatis Vassiliadis |
| Edizione | [1st ed. 2005.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2005 |
| Descrizione fisica | 1 online resource (XV, 476 p.) |
| Disciplina | 004.2/2 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Computers Microprocessors Computer architecture Computer networks Electronic digital computers—Evaluation Computer systems Theory of Computation Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation Computer System Implementation |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynote -- Platform Thinking in Embedded Systems -- Reconfigurable System Design and Implementations -- Interprocedural Optimization for Dynamic Hardware Configurations -- Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques -- Reconfigurable Multiple Operation Array -- RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration -- Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping -- Automatic FIR Filter Generation for FPGAs -- Two-Dimensional Fast Cosine Transform for Vector-STA Architectures -- Configurable Computing for High-Security/High-Performance Ambient Systems -- FPL-3E: Towards Language Support for Reconfigurable Packet Processing -- Processor Architectures, Design and Simulation -- Flux Caches: What Are They and Are They Useful? -- First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption -- A Novel JAVA Processor for Embedded Devices -- Formal Specification of a Protocol Processor -- Tuning a Protocol Processor Architecture Towards DSP Operations -- Observations on Power-Efficiency Trends in Mobile Communication Devices -- CORDIC-Augmented Sandbridge Processor for Channel Equalization -- Power-Aware Branch Logic: A Hardware Based Technique for Filtering Access to Branch Logic -- Exploiting Intra-function Correlation with the Global History Stack -- Power Efficient Instruction Caches for Embedded Systems -- Micro-architecture Performance Estimation by Formula -- Offline Phase Analysis and Optimization for Multi-configuration Processors -- Hardware Cost Estimation for Application-Specific Processor Design -- Ultra Fast Cycle-Accurate Compiled Emulation of Inorder Pipelined Architectures -- Generating Stream Based Code from Plain C -- Fast Real-Time Job Selection with Resource Constraints Under Earliest Deadline First -- A Programming Model for an Embedded Media Processing Architecture -- Automatic ADL-Based Assembler Generation for ASIP Programming Support -- Sandbridge Software Tools -- Architectures and Implementations -- A Hardware Accelerator for Controlling Access to Multiple-Unit Resources in Safety/Time-Critical Systems -- Pattern Matching Acceleration for Network Intrusion Detection Systems -- Real-Time Stereo Vision on a Reconfigurable System -- Application of Very Fast Simulated Reannealing (VFSR) to Low Power Design -- Compressed Swapping for NAND Flash Memory Based Embedded Systems -- A Radix-8 Multiplier Design and Its Extension for Efficient Implementation of Imaging Algorithms -- A Scalable Embedded JPEG2000 Architecture -- A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design -- Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context -- DDM-CMP: Data-Driven Multithreading on a Chip Multiprocessor -- System Level Design, Modeling and Simulation -- Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets -- High Abstraction Level Design and Implementation Framework for Wireless Sensor Networks -- The ODYSSEY Tool-Set for System-Level Synthesis of Object-Oriented Models -- Design and Implementation of a WLAN Terminal Using UML 2.0 Based Design Flow -- Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms -- DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context -- SystemQ: A Queuing-Based Approach to Architecture Performance Evaluation with SystemC -- Moving Up to the Modeling Level for the Transformation of Data Structures in Embedded Multimedia Applications -- A Case for Visualization-Integrated System-Level Design Space Exploration -- Mixed Virtual/Real Prototypes for Incremental System Design – A Proof of Concept. |
| Record Nr. | UNISA-996465831203316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Embedded Software and Systems [[electronic resource] ] : First International Conference, ICESS 2004, Hangzhou, China, December 9-10, 2004, Revised Selected Papers / / edited by Zhaohui Wu, Minyi Guo, Chun Chen, Jiajun Bu
| Embedded Software and Systems [[electronic resource] ] : First International Conference, ICESS 2004, Hangzhou, China, December 9-10, 2004, Revised Selected Papers / / edited by Zhaohui Wu, Minyi Guo, Chun Chen, Jiajun Bu |
| Edizione | [1st ed. 2005.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2005 |
| Descrizione fisica | 1 online resource (XX, 612 p.) |
| Disciplina | 005.1 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Software engineering
Computer networks Microprocessors Computer architecture Computers, Special purpose Electronic digital computers—Evaluation Software Engineering Computer Communication Networks Processor Architectures Special Purpose and Application-Based Systems System Performance and Evaluation |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynote Speeches and Invited Talks Abstracts (Partial) -- Track 1 Distributed Embedded Computing -- Track 2 Embedded Systems -- Track 3 Embedded Hardware and Architecture -- Track 4 Middleware for Embedded Computing -- Track 5 Mobile Systems -- Track 6 Transducer Network -- Track 7 Embedded Operating System -- Track 8 Power-Aware Computing -- Track 9 Real-Time System -- Track 10 Embedded System Verification and Testing -- Track 11 Software Tools for Embedded Systems. |
| Record Nr. | UNISA-996465907503316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Euro-Par 2008 Parallel Processing [[electronic resource] ] : 14th International Euro-Par Conference, Las Palmas de Gran Canaria, Spain, August 26-29, 2008, Proceedings / / edited by Emilio Luque, Tomas Margalef, Domingo Benítez
| Euro-Par 2008 Parallel Processing [[electronic resource] ] : 14th International Euro-Par Conference, Las Palmas de Gran Canaria, Spain, August 26-29, 2008, Proceedings / / edited by Emilio Luque, Tomas Margalef, Domingo Benítez |
| Edizione | [1st ed. 2008.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 |
| Descrizione fisica | 1 online resource (XXVIII, 964 p.) |
| Disciplina | 004 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer engineering
Computer networks Computer science Software engineering Electronic digital computers—Evaluation Database management Computer Engineering and Networks Theory of Computation Software Engineering System Performance and Evaluation Database Management |
| ISBN | 3-540-85451-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Topic 1: Support Tools and Environments -- Topic 2: Performance Prediction and Evaluation -- Topic 3: Scheduling and Load Balancing -- Topic 4: High Performance Architectures and Compilers -- Topic 5: Parallel and Distributed Databases -- Topic 6: Grid and Cluster Computing -- Topic 7: Peer-to-Peer Computing -- Topic 8: Distributed Systems and Algorithms -- Topic 9: Parallel and Distributed Programming -- Topic 10: Parallel Numerical Algorithms -- Topic 11: Distributed and High-Performance Multimedia -- Topic 12: Theory and Algorithms for Parallel Computation -- Topic 13: High-Performance Networks. |
| Record Nr. | UNISA-996466107003316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Euro-Par 2008 Parallel Processing : 14th International Euro-Par Conference, Las Palmas de Gran Canaria, Spain, August 26-29, 2008, Proceedings / / edited by Emilio Luque, Tomas Margalef, Domingo Benítez
| Euro-Par 2008 Parallel Processing : 14th International Euro-Par Conference, Las Palmas de Gran Canaria, Spain, August 26-29, 2008, Proceedings / / edited by Emilio Luque, Tomas Margalef, Domingo Benítez |
| Edizione | [1st ed. 2008.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 |
| Descrizione fisica | 1 online resource (XXVIII, 964 p.) |
| Disciplina | 004 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer engineering
Computer networks Computer science Software engineering Electronic digital computers—Evaluation Database management Computer Engineering and Networks Theory of Computation Software Engineering System Performance and Evaluation Database Management |
| ISBN | 3-540-85451-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Topic 1: Support Tools and Environments -- Topic 2: Performance Prediction and Evaluation -- Topic 3: Scheduling and Load Balancing -- Topic 4: High Performance Architectures and Compilers -- Topic 5: Parallel and Distributed Databases -- Topic 6: Grid and Cluster Computing -- Topic 7: Peer-to-Peer Computing -- Topic 8: Distributed Systems and Algorithms -- Topic 9: Parallel and Distributed Programming -- Topic 10: Parallel Numerical Algorithms -- Topic 11: Distributed and High-Performance Multimedia -- Topic 12: Theory and Algorithms for Parallel Computation -- Topic 13: High-Performance Networks. |
| Record Nr. | UNINA-9910483347003321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Euro-Par 2009 - Parallel Processing [[electronic resource] ] : 15th International Euro-Par Conference, Delft, The Netherlands, August 25-28, 2009, Proceedings / / edited by Henk Sips, Dick Epema, Hai-Xiang Lin
| Euro-Par 2009 - Parallel Processing [[electronic resource] ] : 15th International Euro-Par Conference, Delft, The Netherlands, August 25-28, 2009, Proceedings / / edited by Henk Sips, Dick Epema, Hai-Xiang Lin |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 |
| Descrizione fisica | 1 online resource (XXVII, 1120 p.) |
| Disciplina | 004.3522gerDNB |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer systems
Computer engineering Computer networks Electronic digital computers—Evaluation Microprocessors Computer architecture Operating systems (Computers) Computer System Implementation Computer Engineering and Networks System Performance and Evaluation Processor Architectures Computer Communication Networks Operating Systems |
| ISBN | 3-642-03869-7 |
| Classificazione |
DAT 216f
DAT 516f SS 4800 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Abstracts Invited Talks -- Topic 1: Support Tools and Environments -- Topic 2: Performance Prediction and Evaluation -- Topic 3: Scheduling and Load Balancing -- Topic 4: High Performance Architectures and Compilers -- Topic 5: Parallel and Distributed Databases -- Topic 6: Grid, Cluster, and Cloud Computing -- Topic 7: Peer-to-Peer Computing -- Topic 8: Distributed Systems and Algorithms -- Topic 9: Parallel and Distributed Programming -- Topic 10: Parallel Numerical Algorithms -- Topic 11: Multicore and Manycore Programming -- Topic 12: Theory and Algorithms for Parallel Computation -- Topic 13: High-Performance Networks -- Topic 14: Mobile and Ubiquitous Computing. |
| Record Nr. | UNISA-996465641003316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Euro-Par 2009, Parallel Processing - Workshops [[electronic resource] ] : HPPC, HeteroPar, PROPER, ROIA, UNICORE, VHPC, Delft, The Netherlands, August 25-28, 2009, Workshops / / edited by Hai-Xiang Lin, Michael Alexander, Martti Forsell, Andreas Knüpfer, Radu Prodan, Leonel Sousa, Achim Streit
| Euro-Par 2009, Parallel Processing - Workshops [[electronic resource] ] : HPPC, HeteroPar, PROPER, ROIA, UNICORE, VHPC, Delft, The Netherlands, August 25-28, 2009, Workshops / / edited by Hai-Xiang Lin, Michael Alexander, Martti Forsell, Andreas Knüpfer, Radu Prodan, Leonel Sousa, Achim Streit |
| Edizione | [1st ed. 2010.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2010 |
| Descrizione fisica | 1 online resource (XIX, 468 p. 137 illus.) |
| Disciplina | 004.6 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer networks
Electronic digital computers—Evaluation Software engineering Algorithms Computer programming Computers, Special purpose Computer Communication Networks System Performance and Evaluation Software Engineering Programming Techniques Special Purpose and Application-Based Systems |
| ISBN |
1-280-38768-8
9786613565600 3-642-14122-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Third Workshop on Highly Parallel Processing on a Chip (HPPC 2009) -- HPPC 2009: 3rd Workshop on Highly Parallel Processing on a Chip -- The Next 25 Years of Computer Architecture? -- Software Development and Programming of Multi-core SoC -- HPPC 2009 Panel: Are Many-Core Computer Vendors on Track? -- Distance Constrained Mapping to Support NoC Platforms Based on Source Routing -- Parallel Variable-Length Encoding on GPGPUs -- Towards Metaprogramming for Parallel Systems on a Chip -- Dynamic Detection of Uniform and Affine Vectors in GPGPU Computations -- Automatic Calibration of Performance Models on Heterogeneous Multicore Architectures -- Seventh International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar 2009) -- Preface -- Static Worksharing Strategies for Heterogeneous Computers with Unrecoverable Failures -- Resource Allocation for Multiple Concurrent In-network Stream-Processing Applications -- Distributed Data Partitioning for Heterogeneous Processors Based on Partial Estimation of Their Functional Performance Models -- An Efficient Weighted Bi-objective Scheduling Algorithm for Heterogeneous Systems -- Two-Dimensional Matrix Partitioning for Parallel Computing on Heterogeneous Processors Based on Their Functional Performance Models -- Accelerating S3D: A GPGPU Case Study -- Using Hybrid CPU-GPU Platforms to Accelerate the Computation of the Matrix Sign Function -- Modelling Pilot-Job Applications on Production Grids -- Modeling Resubmission in Unreliable Grids: The Bottom-Up Approach -- Reliable Parallel Programming Model for Distributed Computing Environments -- Second Workshop on Productivity and Performance (PROPER 2009) -- PROPER 2009: Workshop on Productivity and Performance – Tools for HPC Application Development -- Argument Controlled Profiling -- Detailed Performance Analysis Using Coarse Grain Sampling -- Automatic Performance Analysis of Large Scale Simulations -- Performance Simulation of Non-blocking Communication in Message-Passing Applications -- Capturing and Visualizing Event Flow Graphs of MPI Applications -- Scalable Event Trace Visualization -- Workshop on Real-Time Interactive Applications on the Grid (ROIA 2009) -- Preface -- Bipartite Electronic SLA as a Business Framework to Support Cross-Organization Load Management of Real-Time Online Applications -- Monitoring and Fault Tolerance for Real-Time Online Interactive Applications -- A Service-Oriented Interface for Highly Interactive Distributed Applications -- CompTalks – From a Meta-model Towards a Framework for Application-Level Interaction Protocols -- CAMEO: Continuous Analytics for Massively Multiplayer Online Games on Cloud Resources -- Complex Multiplayer Urban Design System – Concept and Case Studies -- UNICORE Summit 2009 -- Preface -- JavaGAT Adaptor for UNICORE 6 – Development and Evaluation in the Project AeroGrid -- Towards a Common Authorization Infrastructure for the Grid -- Using UNICORE and WS-BPEL for Scientific Workflow Execution in Grid Environments -- Enhancing UNICORE Storage Management Using Hadoop Distributed File System -- A Data Management System for UNICORE 6 -- UNICORE-Related Projects for Deploying the Belarusian National Grid Network -- Fourth Workshop on Virtualization in High - Performance Cloud Computing (VHPC 2009) -- VHPC 2009: 4th Workshop on Virtualization in High-Performance Cloud Computing -- SSD-HDD-Hybrid Virtual Disk in Consolidated Environments -- An Efficient Implementation of GPU Virtualization in High Performance Clusters -- MyriXen: Message Passing in Xen Virtual Machines over Myrinet and Ethernet -- Virtage: Server Virtualization with Hardware Transparency -- Scalable Repositories for Virtual Clusters -- Dynamic Virtual Cluster Reconfiguration for Efficient IaaS Provisioning -- Performance Measurement of a Private Cloud in the OpenCirrusTM Testbed -- Providing Grid Services Based on Virtualization and Cloud Technologies -- Real-Time Issues in Live Migration of Virtual Machines. |
| Record Nr. | UNISA-996465850203316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2010 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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