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Reconfigurable Computing: Architectures, Tools and Applications [[electronic resource] ] : 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009, Proceedings / / edited by Jürgen Becker, Roger Woods, Peter Athanas, Fearghal Morgan
| Reconfigurable Computing: Architectures, Tools and Applications [[electronic resource] ] : 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009, Proceedings / / edited by Jürgen Becker, Roger Woods, Peter Athanas, Fearghal Morgan |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 |
| Descrizione fisica | 1 online resource (XV, 388 p.) |
| Disciplina | 004 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computers
Microprocessors Computer architecture Computer networks Electronic digital computers—Evaluation Computer systems Computer vision Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation Computer System Implementation Computer Vision |
| ISBN | 3-642-00641-8 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynotes -- FPGA Design Productivity – A Discussion of the State of the Art and a Research Agenda -- Resiliency in Elemental Computing -- The Colour of Embedded Computation -- Applications 1 -- A HyperTransport 3 Physical Layer Interface for FPGAs -- Parametric Design for Reconfigurable Software-Defined Radio -- Applications 2 -- Hardware/Software FPGA Architecture for Robotics Applications -- Reconfigurable Operator Based Multimedia Embedded Processor -- FPGA Security and Bitstream Analysis -- A Protocol for Secure Remote Updates of FPGA Configurations -- FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing -- Fault Tolerant Systems -- An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications -- Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs -- Architectures -- A Novel Local Interconnect Architecture for Variable Grain Logic Cell -- Dynamically Adapted Low Power ASIPs -- Fast Optical Reconfiguration of a Nine-Context DORGA -- Place and Route Techniques -- Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep -- On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks -- A New Datapath Merging Method for Reconfigurable System -- Cryptography -- Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform -- Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm -- Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs -- Resource Allocation and Scheduling -- Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures -- Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems -- Applications 3 -- Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator -- FPGA-Based Anomalous Trajectory Detection Using SOFM -- Posters -- SORU: A Reconfigurable Vector Unit for Adaptable Embedded Systems -- A Parallel Branching Program Machine for Emulation of Sequential Circuits -- Memory Sharing Approach for TMR Softcore Processor -- The Need for Reconfigurable Routers in Networks-on-Chip -- Transparent Dynamic Reconfiguration as a Service of a System-Level Middleware -- Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder -- Tile-Based Fault Tolerant Approach Using Partial Reconfiguration -- Regular Expression Pattern Matching Supporting Constrained Repetitions -- Accelerating Calculations on the RASC Platform: A Case Study of the Exponential Function -- AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications -- CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers -- Object Tracking and Motion Capturing in Hardware-Accelerated Multi-camera System -- Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture -- A Hardware Accelerated Simulation Environment for Spiking Neural Networks -- Survey of Advanced CABAC Accelerator Architectures for Future Multimedia -- Real Time Simulation in Floating Point Precision Using FPGA Computing -- A Hardware Analysis of Twisted Edwards Curves for an Elliptic Curve Cryptosystem -- A Seamless Virtualization Approach for Transparent Dynamical Function Mapping Targeting Heterogeneous and Reconfigurable Systems -- Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator -- ACCFS – Operating System Integration of Computational Accelerators Using a VFS Approach -- A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms. |
| Record Nr. | UNINA-9910484388003321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Reconfigurable Computing: Architectures, Tools and Applications [[electronic resource] ] : Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007, Proceedings / / edited by Pedro C. Diniz, Eduardo Marques, Koen Bertels, Marcio Merino Fernandes, Joao M.P. Cardoso
| Reconfigurable Computing: Architectures, Tools and Applications [[electronic resource] ] : Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007, Proceedings / / edited by Pedro C. Diniz, Eduardo Marques, Koen Bertels, Marcio Merino Fernandes, Joao M.P. Cardoso |
| Edizione | [1st ed. 2007.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 |
| Descrizione fisica | 1 online resource (404 p.) |
| Disciplina | 006.3 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Computers Microprocessors Computer architecture Computer networks Electronic digital computers—Evaluation Computer systems Theory of Computation Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation Computer System Implementation |
| ISBN |
1-280-94070-0
9786610940707 3-540-71431-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Architectures [Regular Papers] -- Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array -- A Configurable Multi-ported Register File Architecture for Soft Processor Cores -- MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture -- Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture -- Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs -- Systematic Customization of On-Chip Crossbar Interconnects -- Authentication of FPGA Bitstreams: Why and How -- Architectures [Short Papers] -- Design of a Reversible PLD Architecture -- Designing Heterogeneous FPGAs with Multiple SBs -- Mapping Techniques and Tools [Regular Papers] -- Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations -- Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware -- Adapting and Automating XILINX’s Partial Reconfiguration Flow for Multiple Module Implementations -- A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions -- Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping -- The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining -- Hardware/Software Codesign for Embedded Implementation of Neural Networks -- Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues -- Mapping Techniques and Tools [Short Papers] -- About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizations -- Arithmetic [Regular Papers] -- Switching Activity Models for Power Estimation in FPGA Multipliers -- Multiplication over on FPGA: A Survey -- A Parallel Version of the Itoh-Tsujii Multiplicative Inversion Algorithm -- A Fast Finite Field Multiplier -- Applications [Regular Papers] -- Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval -- Image Processing Architecture for Local Features Computation -- A Compact Shader for FPGA-Based Volume Rendering Accelerators -- Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications -- FPGA-Accelerated Molecular Dynamics Simulations: An Overview -- Reconfigurable Hardware Acceleration of Canonical Graph Labelling -- Reconfigurable Computing for Accelerating Protein Folding Simulations -- Reconfigurable Parallel Architecture for Genetic Algorithms: Application to the Synthesis of Digital Circuits -- Applications [Short Papers] -- A Space Variant Mapping Architecture for Reliable Car Segmentation -- A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads -- Searching the Web with an FPGA Based Search Engine -- An Acceleration Method for Evolutionary Systems Based on Iterated Prisoner’s Dilemma -- Real Time Architectures for Moving-Objects Tracking -- Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller -- Multiple Sequence Alignment Using Reconfigurable Computing -- Simulation of the Dynamic Behavior of One-Dimensional Cellular Automata Using Reconfigurable Computing. |
| Record Nr. | UNISA-996466268303316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Reconfigurable Computing: Architectures, Tools and Applications [[electronic resource] ] : Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007, Proceedings / / edited by Pedro C. Diniz, Eduardo Marques, Koen Bertels, Marcio Merino Fernandes, Joao M.P. Cardoso
| Reconfigurable Computing: Architectures, Tools and Applications [[electronic resource] ] : Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007, Proceedings / / edited by Pedro C. Diniz, Eduardo Marques, Koen Bertels, Marcio Merino Fernandes, Joao M.P. Cardoso |
| Edizione | [1st ed. 2007.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 |
| Descrizione fisica | 1 online resource (404 p.) |
| Disciplina | 006.3 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Computers Microprocessors Computer architecture Computer networks Electronic digital computers—Evaluation Computer systems Theory of Computation Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation Computer System Implementation |
| ISBN |
1-280-94070-0
9786610940707 3-540-71431-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Architectures [Regular Papers] -- Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array -- A Configurable Multi-ported Register File Architecture for Soft Processor Cores -- MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture -- Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture -- Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs -- Systematic Customization of On-Chip Crossbar Interconnects -- Authentication of FPGA Bitstreams: Why and How -- Architectures [Short Papers] -- Design of a Reversible PLD Architecture -- Designing Heterogeneous FPGAs with Multiple SBs -- Mapping Techniques and Tools [Regular Papers] -- Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations -- Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware -- Adapting and Automating XILINX’s Partial Reconfiguration Flow for Multiple Module Implementations -- A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions -- Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping -- The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining -- Hardware/Software Codesign for Embedded Implementation of Neural Networks -- Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues -- Mapping Techniques and Tools [Short Papers] -- About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizations -- Arithmetic [Regular Papers] -- Switching Activity Models for Power Estimation in FPGA Multipliers -- Multiplication over on FPGA: A Survey -- A Parallel Version of the Itoh-Tsujii Multiplicative Inversion Algorithm -- A Fast Finite Field Multiplier -- Applications [Regular Papers] -- Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval -- Image Processing Architecture for Local Features Computation -- A Compact Shader for FPGA-Based Volume Rendering Accelerators -- Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications -- FPGA-Accelerated Molecular Dynamics Simulations: An Overview -- Reconfigurable Hardware Acceleration of Canonical Graph Labelling -- Reconfigurable Computing for Accelerating Protein Folding Simulations -- Reconfigurable Parallel Architecture for Genetic Algorithms: Application to the Synthesis of Digital Circuits -- Applications [Short Papers] -- A Space Variant Mapping Architecture for Reliable Car Segmentation -- A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads -- Searching the Web with an FPGA Based Search Engine -- An Acceleration Method for Evolutionary Systems Based on Iterated Prisoner’s Dilemma -- Real Time Architectures for Moving-Objects Tracking -- Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller -- Multiple Sequence Alignment Using Reconfigurable Computing -- Simulation of the Dynamic Behavior of One-Dimensional Cellular Automata Using Reconfigurable Computing. |
| Record Nr. | UNINA-9910767553903321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Reconfigurable Computing: Architectures, Tools, and Applications [[electronic resource] ] : 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008, Proceedings / / edited by Roger Woods, Katherine Compton, Christos Bourganis, Pedro C. Diniz
| Reconfigurable Computing: Architectures, Tools, and Applications [[electronic resource] ] : 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008, Proceedings / / edited by Roger Woods, Katherine Compton, Christos Bourganis, Pedro C. Diniz |
| Edizione | [1st ed. 2008.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 |
| Descrizione fisica | 1 online resource (XIV, 346 p.) |
| Disciplina | 004 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Computers Microprocessors Computer architecture Computer networks Electronic digital computers—Evaluation Computer systems Theory of Computation Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation Computer System Implementation |
| ISBN | 3-540-78610-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynotes -- Synthesizing FPGA Circuits from Parallel Programs -- From Silicon to Science: The Long Road to Production Reconfigurable Supercomputing -- The von Neumann Syndrome and the CS Education Dilemma -- Programming and Compilation -- Optimal Unroll Factor for Reconfigurable Architectures -- Programming Reconfigurable Decoupled Application Control Accelerator for Mobile Systems -- DNA and String Processing Applications -- DNA Physical Mapping on a Reconfigurable Platform -- Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension -- Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs -- Scientific Applications -- A Custom Processor for a TDMA Solver in a CFD Application -- A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation -- Reconfigurable Computing Hardware and Systems -- Physical Design of FPGA Interconnect to Prevent Information Leakage -- Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs -- Run-Time Adaptable Architectures for Heterogeneous Behavior Embedded Systems -- Image Processing -- FPGA-Based Real-Time Super-Resolution on an Adaptive Image Sensor -- A Parallel Hardware Architecture for Image Feature Detection -- Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System -- Run-Time Behavior -- A New Self-managing Hardware Design Approach for FPGA-Based Reconfigurable Systems -- A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor -- Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens -- Instruction Set Extension -- ARISE Machines: Extending Processors with Hybrid Accelerators -- The Instruction-Set Extension Problem: A Survey -- Random Number Generation and Financial Computation -- An FPGA Run-Time Parameterisable Log-Normal Random Number Generator -- Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA -- Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models -- Posters -- Hybrid-Mode Floating-Point FPGA CORDIC Co-processor -- Multiplier-Based Double Precision Floating Point Divider According to the IEEE-754 Standard -- Creating the World’s Largest Reconfigurable Supercomputing System Based on the Scalable SGI® Altix® 4700 System Infrastructure and Benchmarking Life-Science Applications -- Highly Efficient Structure of 64-Bit Exponential Function Implemented in FPGAs -- A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures -- PARO: Synthesis of Hardware Accelerators for Multi-dimensional Dataflow-Intensive Applications -- Stream Transfer Balancing Scheme Utilizing Multi-path Routing in Networks on Chip -- Efficiency of Dynamic Reconfigurable Datapath Extensions – A Case Study -- Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices -- Data Reallocation by Exploiting FPGA Configuration Mechanisms -- A Networked, Lightweight and Partially Reconfigurable Platform -- Neuromolecularware – A Bio-inspired Evolvable Hardware and Its Application to Medical Diagnosis -- An FPGA Configuration Scheme for Bitstream Protection -- Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture. |
| Record Nr. | UNISA-996465518003316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Reconfigurable Computing: Architectures, Tools, and Applications [[electronic resource] ] : 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008, Proceedings / / edited by Roger Woods, Katherine Compton, Christos Bourganis, Pedro C. Diniz
| Reconfigurable Computing: Architectures, Tools, and Applications [[electronic resource] ] : 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008, Proceedings / / edited by Roger Woods, Katherine Compton, Christos Bourganis, Pedro C. Diniz |
| Edizione | [1st ed. 2008.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 |
| Descrizione fisica | 1 online resource (XIV, 346 p.) |
| Disciplina | 004 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Computers Microprocessors Computer architecture Computer networks Electronic digital computers—Evaluation Computer systems Theory of Computation Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation Computer System Implementation |
| ISBN | 3-540-78610-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynotes -- Synthesizing FPGA Circuits from Parallel Programs -- From Silicon to Science: The Long Road to Production Reconfigurable Supercomputing -- The von Neumann Syndrome and the CS Education Dilemma -- Programming and Compilation -- Optimal Unroll Factor for Reconfigurable Architectures -- Programming Reconfigurable Decoupled Application Control Accelerator for Mobile Systems -- DNA and String Processing Applications -- DNA Physical Mapping on a Reconfigurable Platform -- Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension -- Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs -- Scientific Applications -- A Custom Processor for a TDMA Solver in a CFD Application -- A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation -- Reconfigurable Computing Hardware and Systems -- Physical Design of FPGA Interconnect to Prevent Information Leakage -- Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs -- Run-Time Adaptable Architectures for Heterogeneous Behavior Embedded Systems -- Image Processing -- FPGA-Based Real-Time Super-Resolution on an Adaptive Image Sensor -- A Parallel Hardware Architecture for Image Feature Detection -- Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System -- Run-Time Behavior -- A New Self-managing Hardware Design Approach for FPGA-Based Reconfigurable Systems -- A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor -- Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens -- Instruction Set Extension -- ARISE Machines: Extending Processors with Hybrid Accelerators -- The Instruction-Set Extension Problem: A Survey -- Random Number Generation and Financial Computation -- An FPGA Run-Time Parameterisable Log-Normal Random Number Generator -- Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA -- Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models -- Posters -- Hybrid-Mode Floating-Point FPGA CORDIC Co-processor -- Multiplier-Based Double Precision Floating Point Divider According to the IEEE-754 Standard -- Creating the World’s Largest Reconfigurable Supercomputing System Based on the Scalable SGI® Altix® 4700 System Infrastructure and Benchmarking Life-Science Applications -- Highly Efficient Structure of 64-Bit Exponential Function Implemented in FPGAs -- A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures -- PARO: Synthesis of Hardware Accelerators for Multi-dimensional Dataflow-Intensive Applications -- Stream Transfer Balancing Scheme Utilizing Multi-path Routing in Networks on Chip -- Efficiency of Dynamic Reconfigurable Datapath Extensions – A Case Study -- Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices -- Data Reallocation by Exploiting FPGA Configuration Mechanisms -- A Networked, Lightweight and Partially Reconfigurable Platform -- Neuromolecularware – A Bio-inspired Evolvable Hardware and Its Application to Medical Diagnosis -- An FPGA Configuration Scheme for Bitstream Protection -- Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture. |
| Record Nr. | UNINA-9910485047503321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Robust and Online Large-Scale Optimization [[electronic resource] ] : Models and Techniques for Transportation Systems / / edited by Ravindra K. Ahuja, Rolf H. Möhring, Christos D. Zaroliagis
| Robust and Online Large-Scale Optimization [[electronic resource] ] : Models and Techniques for Transportation Systems / / edited by Ravindra K. Ahuja, Rolf H. Möhring, Christos D. Zaroliagis |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 |
| Descrizione fisica | 1 online resource (XVIII, 423 p.) |
| Disciplina | 004n/a |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computers
Electronic digital computers—Evaluation Computers, Special purpose Computer simulation Security systems Discrete mathematics Hardware Performance and Reliability System Performance and Evaluation Special Purpose and Application-Based Systems Computer Modelling Security Science and Technology Discrete Mathematics |
| ISBN | 3-642-05465-X |
| Classificazione |
004
BAU 853f MAT 910f SS 4800 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Robustness and Recoverability: New Concepts -- The Concept of Recoverable Robustness, Linear Programming Recovery, and Railway Applications -- Recoverable Robustness in Shunting and Timetabling -- Light Robustness -- Incentive-Compatible Robust Line Planning -- A Bicriteria Approach for Robust Timetabling -- Robust Timetabling and Route Planning -- Meta-heuristic and Constraint-Based Approaches for Single-Line Railway Timetabling -- Engineering Time-Expanded Graphs for Faster Timetable Information -- Time-Dependent Route Planning -- The Exact Subgraph Recoverable Robust Shortest Path Problem -- Efficient Timetable Information in the Presence of Delays -- Robust Planning under Scarce Resources -- Integrating Robust Railway Network Design and Line Planning under Failures -- Effective Allocation of Fleet Frequencies by Reducing Intermediate Stops and Short Turning in Transit Systems -- Shunting for Dummies: An Introductory Algorithmic Survey -- Integrated Gate and Bus Assignment at Amsterdam Airport Schiphol -- Online Planning: Delay and Disruption Management -- Mining Railway Delay Dependencies in Large-Scale Real-World Delay Data -- Rescheduling Dense Train Traffic over Complex Station Interlocking Areas -- Online Train Disposition: To Wait or Not to Wait? -- Disruption Management in Passenger Railway Transportation. |
| Record Nr. | UNISA-996465860203316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Robust and Online Large-Scale Optimization [[electronic resource] ] : Models and Techniques for Transportation Systems / / edited by Ravindra K. Ahuja, Rolf H. Möhring, Christos D. Zaroliagis
| Robust and Online Large-Scale Optimization [[electronic resource] ] : Models and Techniques for Transportation Systems / / edited by Ravindra K. Ahuja, Rolf H. Möhring, Christos D. Zaroliagis |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 |
| Descrizione fisica | 1 online resource (XVIII, 423 p.) |
| Disciplina | 004n/a |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computers
Electronic digital computers—Evaluation Computers, Special purpose Computer simulation Security systems Discrete mathematics Hardware Performance and Reliability System Performance and Evaluation Special Purpose and Application-Based Systems Computer Modelling Security Science and Technology Discrete Mathematics |
| ISBN | 3-642-05465-X |
| Classificazione |
004
BAU 853f MAT 910f SS 4800 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Robustness and Recoverability: New Concepts -- The Concept of Recoverable Robustness, Linear Programming Recovery, and Railway Applications -- Recoverable Robustness in Shunting and Timetabling -- Light Robustness -- Incentive-Compatible Robust Line Planning -- A Bicriteria Approach for Robust Timetabling -- Robust Timetabling and Route Planning -- Meta-heuristic and Constraint-Based Approaches for Single-Line Railway Timetabling -- Engineering Time-Expanded Graphs for Faster Timetable Information -- Time-Dependent Route Planning -- The Exact Subgraph Recoverable Robust Shortest Path Problem -- Efficient Timetable Information in the Presence of Delays -- Robust Planning under Scarce Resources -- Integrating Robust Railway Network Design and Line Planning under Failures -- Effective Allocation of Fleet Frequencies by Reducing Intermediate Stops and Short Turning in Transit Systems -- Shunting for Dummies: An Introductory Algorithmic Survey -- Integrated Gate and Bus Assignment at Amsterdam Airport Schiphol -- Online Planning: Delay and Disruption Management -- Mining Railway Delay Dependencies in Large-Scale Real-World Delay Data -- Rescheduling Dense Train Traffic over Complex Station Interlocking Areas -- Online Train Disposition: To Wait or Not to Wait? -- Disruption Management in Passenger Railway Transportation. |
| Record Nr. | UNINA-9910483050603321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Runtime Verification [[electronic resource] ] : 18th International Conference, RV 2018, Limassol, Cyprus, November 10–13, 2018, Proceedings / / edited by Christian Colombo, Martin Leucker
| Runtime Verification [[electronic resource] ] : 18th International Conference, RV 2018, Limassol, Cyprus, November 10–13, 2018, Proceedings / / edited by Christian Colombo, Martin Leucker |
| Edizione | [1st ed. 2018.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018 |
| Descrizione fisica | 1 online resource (XI, 470 p. 113 illus., 42 illus. in color.) |
| Disciplina | 005.14 |
| Collana | Programming and Software Engineering |
| Soggetto topico |
Software engineering
Compilers (Computer programs) Electronic digital computers—Evaluation Computer science Computers Professions Machine theory Software Engineering Compilers and Interpreters System Performance and Evaluation Computer Science Logic and Foundations of Programming The Computing Profession Formal Languages and Automata Theory |
| ISBN | 3-030-03769-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Papers -- Tutorial Papers -- Regular Papers -- Short Papers -- Tool Papers. |
| Record Nr. | UNISA-996466290203316 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Runtime Verification [[electronic resource] ] : 18th International Conference, RV 2018, Limassol, Cyprus, November 10–13, 2018, Proceedings / / edited by Christian Colombo, Martin Leucker
| Runtime Verification [[electronic resource] ] : 18th International Conference, RV 2018, Limassol, Cyprus, November 10–13, 2018, Proceedings / / edited by Christian Colombo, Martin Leucker |
| Edizione | [1st ed. 2018.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018 |
| Descrizione fisica | 1 online resource (XI, 470 p. 113 illus., 42 illus. in color.) |
| Disciplina | 005.14 |
| Collana | Programming and Software Engineering |
| Soggetto topico |
Software engineering
Compilers (Computer programs) Electronic digital computers—Evaluation Computer science Computers Professions Machine theory Software Engineering Compilers and Interpreters System Performance and Evaluation Computer Science Logic and Foundations of Programming The Computing Profession Formal Languages and Automata Theory |
| ISBN | 3-030-03769-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Papers -- Tutorial Papers -- Regular Papers -- Short Papers -- Tool Papers. |
| Record Nr. | UNINA-9910349393203321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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SOFSEM 2009: Theory and Practice of Computer Science [[electronic resource] ] : 35th Conference on Current Trends in Theory and Practice of Computer Science, Špindleruv Mlýn, Czech Republic, January 24-30, 2009. Proceedings / / edited by Mogens Nielsen, Antonin Kucera, Peter Bro Miltersen, Catuscia Palamidessi, Petr Tuma, Frank Valencia
| SOFSEM 2009: Theory and Practice of Computer Science [[electronic resource] ] : 35th Conference on Current Trends in Theory and Practice of Computer Science, Špindleruv Mlýn, Czech Republic, January 24-30, 2009. Proceedings / / edited by Mogens Nielsen, Antonin Kucera, Peter Bro Miltersen, Catuscia Palamidessi, Petr Tuma, Frank Valencia |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 |
| Descrizione fisica | 1 online resource (XVII, 670 p.) |
| Disciplina | 004.0151 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Database management Computer programming Electronic digital computers—Evaluation Data mining Information storage and retrieval systems Theory of Computation Database Management Programming Techniques System Performance and Evaluation Data Mining and Knowledge Discovery Information Storage and Retrieval |
| ISBN | 3-540-95891-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Talks -- A New Analysis of Expected Revenue -- Can Component/Service-Based Systems Be Proved Correct? -- Probabilistic Acceptors for Languages over Infinite Words -- Automatic Verification of Heap Manipulation Using Separation Logic -- Technology Diffusion in Social Networks -- Service Oriented Architecture Pitfalls -- Algorithms for Solving Infinite Games -- Randomness and Determination, from Physics and Computing towards Biology -- When Analysis Fails: Heuristic Mechanism Design via Self-correcting Procedures -- Regular Papers -- On Compositionality, Efficiency, and Applicability of Abstraction in Probabilistic Systems -- Framed Versus Unframed Two-Dimensional Languages -- Approximating Tree Edit Distance through String Edit Distance for Binary Tree Codes -- The Shortcut Problem – Complexity and Approximation -- Green Computing: Energy Consumption Optimized Service Hosting -- On the OBDD Complexity of Threshold Functions and the Variable Ordering Problem -- Natural Specifications Yield Decidability for Distributed Synthesis of Asynchronous Systems -- Epistemic Strategies and Games on Concurrent Processes -- On Finite Bases for Weak Semantics: Failures Versus Impossible Futures -- On Generating All Maximal Acyclic Subhypergraphs with Polynomial Delay -- Time and Fairness in a Process Algebra with Non-blocking Reading -- Expressiveness of Multiple Heads in CHR -- Weaknesses of Cuckoo Hashing with a Simple Universal Hash Class: The Case of Large Universes -- A Framework for Mutant Genetic Generation for WS-BPEL -- Implementing Services by Partial State Machines -- Pattern Matching with Swaps for Short Patterns in Linear Time -- Automatic Bug Detection in Microcontroller Software by Static Program Analysis -- On the Unification of Process Semantics: Observational Semantics -- Factoring and Testing Primes in Small Space -- Adaptive Incentive-Compatible Sponsored Search Auction -- Semantically-Aided Data-Aware Service Workflow Composition -- Increasing Machine Speed in On-Line Scheduling of Weighted Unit-Length Jobs in Slotted Time -- Abstract Storage Devices -- On Stateless Deterministic Restarting Automata -- User Care Preference-Based Semantic Service Discovery in a Ubiquitous Environment -- Safe Reasoning with Logic LTS -- Partial Order Semantics of Types of Nets -- A Problem Kernelization for Graph Packing -- -Hardness of Pure Nash Equilibrium in Scheduling and Connection Games -- Conjunctive Grammars with Restricted Disjunction -- Modelling and Verifying Mobile Systems Using ?-Graphs -- On Some SAT-Variants over Linear Formulas -- The Simple Reachability Problem in Switch Graphs -- Unambiguous Erasing Morphisms in Free Monoids -- An Efficient Symbolic Elimination Algorithm for the Stochastic Process Algebra Tool CASPA -- Asynchronous Deterministic Rendezvous on the Line -- Design Validation by Symbolic Simulation and Equivalence Checking: A Case Study in Memory Optimization for Image Manipulation -- Group Input Machine -- From Outermost Termination to Innermost Termination -- Improved Algorithms for the 2-Vertex Disjoint Paths Problem -- Event-Clock Visibly Pushdown Automata -- A Machine Checked Soundness Proof for an Intermediate Verification Language -- Symbolic State-Space Generation of Asynchronous Systems Using Extensible Decision Diagrams -- Symbolic Reachability Analysis of Integer Timed Petri Nets -- On Toda’s Theorem in Structural Communication Complexity -- The Minimum Reload s-t Path/Trail/Walk Problems -- Polylog Space Compression Is Incomparable with Lempel-Ziv and Pushdown Compression -- A New Family of Regular Operators Fitting with the Position Automaton Computation -- A Formal Model of Business Application Integration from Web Services (Position Paper). |
| Record Nr. | UNISA-996465903103316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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