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Quantum Technology and Optimization Problems [[electronic resource] ] : First International Workshop, QTOP 2019, Munich, Germany, March 18, 2019, Proceedings / / edited by Sebastian Feld, Claudia Linnhoff-Popien
| Quantum Technology and Optimization Problems [[electronic resource] ] : First International Workshop, QTOP 2019, Munich, Germany, March 18, 2019, Proceedings / / edited by Sebastian Feld, Claudia Linnhoff-Popien |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (VIII, 231 p. 166 illus., 67 illus. in color.) |
| Disciplina | 006.3843 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Algorithms
Electronic digital computers—Evaluation Computer systems Numerical analysis System Performance and Evaluation Computer System Implementation Numerical Analysis |
| ISBN | 3-030-14082-2 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Analysis of Optimization Problems -- Quantum Gate Algorithms -- Applications of Quantum Annealing -- Foundations and Quantum Technologies. |
| Record Nr. | UNINA-9910337566903321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Queueing Theory and Network Applications [[electronic resource] ] : 14th International Conference, QTNA 2019, Ghent, Belgium, August 27–29, 2019, Proceedings / / edited by Tuan Phung-Duc, Shoji Kasahara, Sabine Wittevrongel
| Queueing Theory and Network Applications [[electronic resource] ] : 14th International Conference, QTNA 2019, Ghent, Belgium, August 27–29, 2019, Proceedings / / edited by Tuan Phung-Duc, Shoji Kasahara, Sabine Wittevrongel |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (XIII, 389 p. 130 illus., 54 illus. in color.) |
| Disciplina | 519.82 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science—Mathematics
Mathematical statistics Computer networks Coding theory Information theory Electronic digital computers—Evaluation Numerical analysis Probability and Statistics in Computer Science Computer Communication Networks Coding and Information Theory System Performance and Evaluation Numerical Analysis Mathematical Applications in Computer Science |
| ISBN | 3-030-27181-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Retrial Queues -- Controllable Queues -- Strategic Queues -- Queueing Networks -- Scheduling Policies -- Multidimensional Systems -- Queueing Models in Applications. |
| Record Nr. | UNISA-996466425403316 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Queueing Theory and Network Applications [[electronic resource] ] : 14th International Conference, QTNA 2019, Ghent, Belgium, August 27–29, 2019, Proceedings / / edited by Tuan Phung-Duc, Shoji Kasahara, Sabine Wittevrongel
| Queueing Theory and Network Applications [[electronic resource] ] : 14th International Conference, QTNA 2019, Ghent, Belgium, August 27–29, 2019, Proceedings / / edited by Tuan Phung-Duc, Shoji Kasahara, Sabine Wittevrongel |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (XIII, 389 p. 130 illus., 54 illus. in color.) |
| Disciplina | 519.82 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science—Mathematics
Mathematical statistics Computer networks Coding theory Information theory Electronic digital computers—Evaluation Numerical analysis Probability and Statistics in Computer Science Computer Communication Networks Coding and Information Theory System Performance and Evaluation Numerical Analysis Mathematical Applications in Computer Science |
| ISBN | 3-030-27181-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Retrial Queues -- Controllable Queues -- Strategic Queues -- Queueing Networks -- Scheduling Policies -- Multidimensional Systems -- Queueing Models in Applications. |
| Record Nr. | UNINA-9910349302003321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Reachability Problems [[electronic resource] ] : 13th International Conference, RP 2019, Brussels, Belgium, September 11–13, 2019, Proceedings / / edited by Emmanuel Filiot, Raphaël Jungers, Igor Potapov
| Reachability Problems [[electronic resource] ] : 13th International Conference, RP 2019, Brussels, Belgium, September 11–13, 2019, Proceedings / / edited by Emmanuel Filiot, Raphaël Jungers, Igor Potapov |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (XX, 233 p. 275 illus., 14 illus. in color.) |
| Disciplina | 004.0151 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Software engineering Artificial intelligence Electronic digital computers—Evaluation Computers Professions Computer science—Mathematics Computer Science Logic and Foundations of Programming Software Engineering Artificial Intelligence System Performance and Evaluation The Computing Profession Mathematics of Computing |
| ISBN | 3-030-30806-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Bidding Games on Markov Decision Processes -- Primitivity and synchronizing automata: a functional analytic approach -- Reaching Out Towards Fully Verified Autonomous Systems -- On the m-eternal Domination Number of Cactus Graphs -- On Relevant Equilibria in Reachability Games -- Partial Solvers for Generalized Parity Games -- Reachability in Augmented Interval Markov Chains -- On Solving Word Equations Using SAT -- Parameterised Verification of Publish/Subscribe Networks with Exception Handling -- Cellular automata for the self-stabilisation of colourings and tilings -- On the termination problem for counter machines with incrementing errors -- Reachability Problems on Partially Lossy Queue Automata -- On the computation of the minimal coverability set of Petri nets -- Deciding Reachability for Piecewise Constant Derivative Systems on Orientable Manifolds -- Coverability is undecidable in one-dimensional pushdown vector addition systems with resets -- Synthesis of structurally restricted b-bounded Petri nets: complexity results -- Reachability of Five Gossip Protocols. |
| Record Nr. | UNISA-996466284203316 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Reachability Problems [[electronic resource] ] : 13th International Conference, RP 2019, Brussels, Belgium, September 11–13, 2019, Proceedings / / edited by Emmanuel Filiot, Raphaël Jungers, Igor Potapov
| Reachability Problems [[electronic resource] ] : 13th International Conference, RP 2019, Brussels, Belgium, September 11–13, 2019, Proceedings / / edited by Emmanuel Filiot, Raphaël Jungers, Igor Potapov |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (XX, 233 p. 275 illus., 14 illus. in color.) |
| Disciplina | 004.0151 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Software engineering Artificial intelligence Electronic digital computers—Evaluation Computers Professions Computer science—Mathematics Computer Science Logic and Foundations of Programming Software Engineering Artificial Intelligence System Performance and Evaluation The Computing Profession Mathematics of Computing |
| ISBN | 3-030-30806-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Bidding Games on Markov Decision Processes -- Primitivity and synchronizing automata: a functional analytic approach -- Reaching Out Towards Fully Verified Autonomous Systems -- On the m-eternal Domination Number of Cactus Graphs -- On Relevant Equilibria in Reachability Games -- Partial Solvers for Generalized Parity Games -- Reachability in Augmented Interval Markov Chains -- On Solving Word Equations Using SAT -- Parameterised Verification of Publish/Subscribe Networks with Exception Handling -- Cellular automata for the self-stabilisation of colourings and tilings -- On the termination problem for counter machines with incrementing errors -- Reachability Problems on Partially Lossy Queue Automata -- On the computation of the minimal coverability set of Petri nets -- Deciding Reachability for Piecewise Constant Derivative Systems on Orientable Manifolds -- Coverability is undecidable in one-dimensional pushdown vector addition systems with resets -- Synthesis of structurally restricted b-bounded Petri nets: complexity results -- Reachability of Five Gossip Protocols. |
| Record Nr. | UNINA-9910349282703321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Real-Time Simulation and Hardware-in-the-Loop Testing Using Typhoon HIL [[electronic resource] /] / edited by Saurabh Mani Tripathi, Francisco M. Gonzalez-Longatt
| Real-Time Simulation and Hardware-in-the-Loop Testing Using Typhoon HIL [[electronic resource] /] / edited by Saurabh Mani Tripathi, Francisco M. Gonzalez-Longatt |
| Edizione | [1st ed. 2023.] |
| Pubbl/distr/stampa | Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2023 |
| Descrizione fisica | 1 online resource (463 pages) |
| Disciplina | 929.374 |
| Collana | Transactions on Computer Systems and Networks |
| Soggetto topico |
Computers, Special purpose
Computer engineering Computer networks Electronic circuits Electronic digital computers—Evaluation Microprocessors Computer architecture Special Purpose and Application-Based Systems Computer Engineering and Networks Electronic Circuits and Systems System Performance and Evaluation Processor Architectures |
| Soggetto non controllato |
Computer Networks
Electronic Circuits Computer Architecture Expert Systems (Computer Science) Computers Technology & Engineering |
| ISBN |
9789819902248
9789819902231 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction to Typhoon HIL -- Typhoon HIL Control Centre and Virtual HIL Device -- Control of Grid-tied Converter: Real-time Validation -- Real-time Control Validation for Multilevel Converter -- Design and Analysis of Cascaded H-Bridge Eleven-Level Inverter -- Grid-connected converter employing optimized modulation strategy coordinated with the virtual synchronous machine concept -- Development of MMC based HVDC and model for SSR analysis in Typhoon HIL -- Selective Harmonic Compensation in Active Power Filter -- RHigh Impedance Fault Modelling and Tests for Real Time Applications -- Cyber Security in Smart Grid -- Sensorless Control of Electric Motor Drives -- Validation of Relaying Techniques on HIL Platform -- Power System Protection Co-ordination and Relay-in-the-Loop -- Testing Distance Element of SEL411-L using Power Hardware-in-the-Loop -- Testing IEC61850 Sampled Values using Typhoon HIL 604. |
| Record Nr. | UNISA-996547966203316 |
| Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2023 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Real-Time Simulation and Hardware-in-the-Loop Testing Using Typhoon HIL [[electronic resource] /] / edited by Saurabh Mani Tripathi, Francisco M. Gonzalez-Longatt
| Real-Time Simulation and Hardware-in-the-Loop Testing Using Typhoon HIL [[electronic resource] /] / edited by Saurabh Mani Tripathi, Francisco M. Gonzalez-Longatt |
| Edizione | [1st ed. 2023.] |
| Pubbl/distr/stampa | Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2023 |
| Descrizione fisica | 1 online resource (463 pages) |
| Disciplina | 929.374 |
| Collana | Transactions on Computer Systems and Networks |
| Soggetto topico |
Computers, Special purpose
Computer engineering Computer networks Electronic circuits Electronic digital computers—Evaluation Microprocessors Computer architecture Special Purpose and Application-Based Systems Computer Engineering and Networks Electronic Circuits and Systems System Performance and Evaluation Processor Architectures |
| Soggetto non controllato |
Computer Networks
Electronic Circuits Computer Architecture Expert Systems (Computer Science) Computers Technology & Engineering |
| ISBN |
9789819902248
9789819902231 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction to Typhoon HIL -- Typhoon HIL Control Centre and Virtual HIL Device -- Control of Grid-tied Converter: Real-time Validation -- Real-time Control Validation for Multilevel Converter -- Design and Analysis of Cascaded H-Bridge Eleven-Level Inverter -- Grid-connected converter employing optimized modulation strategy coordinated with the virtual synchronous machine concept -- Development of MMC based HVDC and model for SSR analysis in Typhoon HIL -- Selective Harmonic Compensation in Active Power Filter -- RHigh Impedance Fault Modelling and Tests for Real Time Applications -- Cyber Security in Smart Grid -- Sensorless Control of Electric Motor Drives -- Validation of Relaying Techniques on HIL Platform -- Power System Protection Co-ordination and Relay-in-the-Loop -- Testing Distance Element of SEL411-L using Power Hardware-in-the-Loop -- Testing IEC61850 Sampled Values using Typhoon HIL 604. |
| Record Nr. | UNINA-9910725096103321 |
| Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2023 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Reconfigurable Computing: Architectures and Applications [[electronic resource] ] : Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006 Revised Selected Papers / / edited by Koen Bertels, João M.P. Cardoso, Stamatis Vassiliadis
| Reconfigurable Computing: Architectures and Applications [[electronic resource] ] : Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006 Revised Selected Papers / / edited by Koen Bertels, João M.P. Cardoso, Stamatis Vassiliadis |
| Edizione | [1st ed. 2006.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006 |
| Descrizione fisica | 1 online resource (XVI, 469 p.) |
| Disciplina | 003.3 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer systems
Computers Microprocessors Computer architecture Computer networks Electronic digital computers—Evaluation Computer System Implementation Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation |
| ISBN | 3-540-36863-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Applications -- Implementation of Realtime and Highspeed Phase Detector on FPGA -- Case Study: Implementation of a Virtual Instrument on a Dynamically Reconfigurable Platform -- Configurable Embedded Core for Controlling Electro-Mechanical Systems -- Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors -- Dynamic Partial Reconfigurable FIR Filter Design -- Event-Driven Simulation Engine for Spiking Neural Networks on a Chip -- Towards an Optimal Implementation of MLP in FPGA -- Power -- Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture -- Quality Driven Dynamic Low Power Reconfiguration of Handhelds -- An Efficient Estimation Method of Dynamic Power Dissipation on VLSI Interconnects -- Image Processing -- Highly Paralellized Architecture for Image Motion Estimation -- Design Exploration of a Video Pre-processor for an FPGA Based SoC -- QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection -- Applications of Small-Scale Reconfigurability to Graphics Processors -- An Embedded Multi-camera System for Simultaneous Localization and Mapping -- Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor -- Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-Chip -- Handel-C Design Enhancement for FPGA-Based DV Decoder -- Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES’ Platform -- A New VLSI Architecture of Lifting-Based DWT -- Architecture Based on FPGA’s for Real-Time Image Processing -- Real Time Image Processing on a Portable Aid Device for Low Vision Patients -- General Purpose Real-Time Image Segmentation System -- Organization and Architecture -- Implementation of LPM Address Generators on FPGAs -- Self Reconfiguring EPIC Soft Core Processors -- Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs -- Area/Performance Improvement of NoC Architectures -- Implementation of Inner Product Architecture for Increased Flexibility in Bitwidths of Input Array -- A Flexible Multi-port Caching Scheme for Reconfigurable Platforms -- Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support -- A Reconfigurable Data Cache for Adaptive Processors -- The Emergence of Non-von Neumann Processors -- Scheduling Reconfiguration Activities of Run-Time Reconfigurable RTOS Using an Aperiodic Task Server -- A New Approach to Assess Defragmentation Strategies in Dynamically Reconfigurable FPGAs -- A 1,632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI -- PISC: Polymorphic Instruction Set Computers -- Networks and Communication -- Generic Network Interfaces for Plug and Play NoC Based Architecture -- Providing QoS Guarantees in a NoC by Virtual Channel Reservation -- Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA -- A Reconfigurable Architecture for MIMO Square Root Decoder -- Security -- Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking -- Updates on the Security of FPGAs Against Power Analysis Attacks -- Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems -- FPGA Implementation of a GF(2 m ) Tate Pairing Architecture -- Iterative Modular Division over GF(2 m ): Novel Algorithm and Implementations on FPGA -- Mobile Fingerprint Identification Using a Hardware Accelerated Biometric Service Provider -- UNITE: Uniform Hardware-Based Network Intrusion deTection Engine -- Tools -- Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs -- Automatic Compilation Framework for Bloom Filter Based Intrusion Detection -- A Basic Data Routing Model for a Coarse-Grain Reconfigurable Hardware -- Hardware and a Tool Chain for ADRES -- Integrating Custom Instruction Specifications into C Development Processes -- A Compiler-Oriented Architecture Description for Reconfigurable Systems -- Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software Compatibility -- High-Level Synthesis Using SPARK and Systolic Array -- Super Semi-systolic Array-Based Application-Specific PLD Architecture. |
| Record Nr. | UNISA-996465597903316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Reconfigurable Computing: Architectures and Applications [[electronic resource] ] : Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006 Revised Selected Papers / / edited by Koen Bertels, João M.P. Cardoso, Stamatis Vassiliadis
| Reconfigurable Computing: Architectures and Applications [[electronic resource] ] : Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006 Revised Selected Papers / / edited by Koen Bertels, João M.P. Cardoso, Stamatis Vassiliadis |
| Edizione | [1st ed. 2006.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006 |
| Descrizione fisica | 1 online resource (XVI, 469 p.) |
| Disciplina | 003.3 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer systems
Computers Microprocessors Computer architecture Computer networks Electronic digital computers—Evaluation Computer System Implementation Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation |
| ISBN | 3-540-36863-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Applications -- Implementation of Realtime and Highspeed Phase Detector on FPGA -- Case Study: Implementation of a Virtual Instrument on a Dynamically Reconfigurable Platform -- Configurable Embedded Core for Controlling Electro-Mechanical Systems -- Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors -- Dynamic Partial Reconfigurable FIR Filter Design -- Event-Driven Simulation Engine for Spiking Neural Networks on a Chip -- Towards an Optimal Implementation of MLP in FPGA -- Power -- Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture -- Quality Driven Dynamic Low Power Reconfiguration of Handhelds -- An Efficient Estimation Method of Dynamic Power Dissipation on VLSI Interconnects -- Image Processing -- Highly Paralellized Architecture for Image Motion Estimation -- Design Exploration of a Video Pre-processor for an FPGA Based SoC -- QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection -- Applications of Small-Scale Reconfigurability to Graphics Processors -- An Embedded Multi-camera System for Simultaneous Localization and Mapping -- Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor -- Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-Chip -- Handel-C Design Enhancement for FPGA-Based DV Decoder -- Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES’ Platform -- A New VLSI Architecture of Lifting-Based DWT -- Architecture Based on FPGA’s for Real-Time Image Processing -- Real Time Image Processing on a Portable Aid Device for Low Vision Patients -- General Purpose Real-Time Image Segmentation System -- Organization and Architecture -- Implementation of LPM Address Generators on FPGAs -- Self Reconfiguring EPIC Soft Core Processors -- Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs -- Area/Performance Improvement of NoC Architectures -- Implementation of Inner Product Architecture for Increased Flexibility in Bitwidths of Input Array -- A Flexible Multi-port Caching Scheme for Reconfigurable Platforms -- Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support -- A Reconfigurable Data Cache for Adaptive Processors -- The Emergence of Non-von Neumann Processors -- Scheduling Reconfiguration Activities of Run-Time Reconfigurable RTOS Using an Aperiodic Task Server -- A New Approach to Assess Defragmentation Strategies in Dynamically Reconfigurable FPGAs -- A 1,632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI -- PISC: Polymorphic Instruction Set Computers -- Networks and Communication -- Generic Network Interfaces for Plug and Play NoC Based Architecture -- Providing QoS Guarantees in a NoC by Virtual Channel Reservation -- Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA -- A Reconfigurable Architecture for MIMO Square Root Decoder -- Security -- Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking -- Updates on the Security of FPGAs Against Power Analysis Attacks -- Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems -- FPGA Implementation of a GF(2 m ) Tate Pairing Architecture -- Iterative Modular Division over GF(2 m ): Novel Algorithm and Implementations on FPGA -- Mobile Fingerprint Identification Using a Hardware Accelerated Biometric Service Provider -- UNITE: Uniform Hardware-Based Network Intrusion deTection Engine -- Tools -- Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs -- Automatic Compilation Framework for Bloom Filter Based Intrusion Detection -- A Basic Data Routing Model for a Coarse-Grain Reconfigurable Hardware -- Hardware and a Tool Chain for ADRES -- Integrating Custom Instruction Specifications into C Development Processes -- A Compiler-Oriented Architecture Description for Reconfigurable Systems -- Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software Compatibility -- High-Level Synthesis Using SPARK and Systolic Array -- Super Semi-systolic Array-Based Application-Specific PLD Architecture. |
| Record Nr. | UNINA-9910484564303321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Reconfigurable Computing: Architectures, Tools and Applications [[electronic resource] ] : 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009, Proceedings / / edited by Jürgen Becker, Roger Woods, Peter Athanas, Fearghal Morgan
| Reconfigurable Computing: Architectures, Tools and Applications [[electronic resource] ] : 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009, Proceedings / / edited by Jürgen Becker, Roger Woods, Peter Athanas, Fearghal Morgan |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 |
| Descrizione fisica | 1 online resource (XV, 388 p.) |
| Disciplina | 004 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computers
Microprocessors Computer architecture Computer networks Electronic digital computers—Evaluation Computer systems Computer vision Computer Hardware Processor Architectures Computer Communication Networks System Performance and Evaluation Computer System Implementation Computer Vision |
| ISBN | 3-642-00641-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Keynotes -- FPGA Design Productivity – A Discussion of the State of the Art and a Research Agenda -- Resiliency in Elemental Computing -- The Colour of Embedded Computation -- Applications 1 -- A HyperTransport 3 Physical Layer Interface for FPGAs -- Parametric Design for Reconfigurable Software-Defined Radio -- Applications 2 -- Hardware/Software FPGA Architecture for Robotics Applications -- Reconfigurable Operator Based Multimedia Embedded Processor -- FPGA Security and Bitstream Analysis -- A Protocol for Secure Remote Updates of FPGA Configurations -- FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing -- Fault Tolerant Systems -- An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications -- Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs -- Architectures -- A Novel Local Interconnect Architecture for Variable Grain Logic Cell -- Dynamically Adapted Low Power ASIPs -- Fast Optical Reconfiguration of a Nine-Context DORGA -- Place and Route Techniques -- Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep -- On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks -- A New Datapath Merging Method for Reconfigurable System -- Cryptography -- Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform -- Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm -- Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs -- Resource Allocation and Scheduling -- Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures -- Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems -- Applications 3 -- Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator -- FPGA-Based Anomalous Trajectory Detection Using SOFM -- Posters -- SORU: A Reconfigurable Vector Unit for Adaptable Embedded Systems -- A Parallel Branching Program Machine for Emulation of Sequential Circuits -- Memory Sharing Approach for TMR Softcore Processor -- The Need for Reconfigurable Routers in Networks-on-Chip -- Transparent Dynamic Reconfiguration as a Service of a System-Level Middleware -- Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder -- Tile-Based Fault Tolerant Approach Using Partial Reconfiguration -- Regular Expression Pattern Matching Supporting Constrained Repetitions -- Accelerating Calculations on the RASC Platform: A Case Study of the Exponential Function -- AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications -- CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers -- Object Tracking and Motion Capturing in Hardware-Accelerated Multi-camera System -- Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture -- A Hardware Accelerated Simulation Environment for Spiking Neural Networks -- Survey of Advanced CABAC Accelerator Architectures for Future Multimedia -- Real Time Simulation in Floating Point Precision Using FPGA Computing -- A Hardware Analysis of Twisted Edwards Curves for an Elliptic Curve Cryptosystem -- A Seamless Virtualization Approach for Transparent Dynamical Function Mapping Targeting Heterogeneous and Reconfigurable Systems -- Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator -- ACCFS – Operating System Integration of Computational Accelerators Using a VFS Approach -- A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms. |
| Record Nr. | UNISA-996465883203316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
