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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers / / edited by José L. Ayala, Delong Shang, Alex Yakovlev
| Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers / / edited by José L. Ayala, Delong Shang, Alex Yakovlev |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 |
| Descrizione fisica | 1 online resource (IX, 258 p. 150 illus.) |
| Disciplina | 004.24 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Electronic digital computers—Evaluation
Computer simulation Computer networks Computer hardware description languages Logic design Compilers (Computer programs) System Performance and Evaluation Computer Modelling Computer Communication Networks Register-Transfer-Level Implementation Logic Design Compilers and Interpreters |
| ISBN | 3-642-36157-9 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Sleep-Transistor Based Power-Gating Tradeoff Analyses -- Modelling and Analysis of Manufacturing Variability Effects from Process to Architectural Level -- Non-invasive Power Simulation at System-Level with SystemC -- A Standard Cell Optimization Method for Near-Threshold Voltage Operations -- An Extended Metastability Simulation Method for Synchronizer Characterization -- Phase Space Based NBTI Model -- Fast Propagation of Hamming and Signal Distances for Register-Transfer Level Datapaths -- Noise Margin Based Library Optimization Considering Variability in Sub-threshold -- TCP Window Based DVFS for Low Power Network Controller SoC -- A Generic Architecture for Robust Asynchronous Communication Links -- Direct Statistical Simulation of Timing Properties in Sequential Circuits -- On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture -- Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications -- Design of a 150 mV Supply, 2 MIPS, 90nm CMOS, Ultra-Low-Power Microprocessor -- Run-Time Measurement of Harvested Energy for Autarkic Sensor Operation -- Observability Conditions and Automatic Operand-Isolation in High-Throughput Asynchronous Pipelines -- Dynamic Power Management of a Computer with Self Power-Managed Components -- Case Studies of Logical Computation on Stochastic Bit Streams. |
| Record Nr. | UNINA-9910484142403321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011, Proceedings / / edited by Jose L. Ayala, Braulio Garcia-Camara, Manuel Prieto, Martino Ruggiero, Gilles Sicard
| Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011, Proceedings / / edited by Jose L. Ayala, Braulio Garcia-Camara, Manuel Prieto, Martino Ruggiero, Gilles Sicard |
| Edizione | [1st ed. 2011.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2011 |
| Descrizione fisica | 1 online resource (XI, 352 p. 189 illus., 108 illus. in color.) |
| Disciplina | 621.39/5 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Electronic digital computers—Evaluation
Computer simulation Computer networks Software engineering Algorithms Computer science System Performance and Evaluation Computer Modelling Computer Communication Networks Software Engineering Computer Science Logic and Foundations of Programming |
| ISBN | 3-642-24154-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996465375703316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers / / edited by Lars Svensson, José Monteiro
| Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers / / edited by Lars Svensson, José Monteiro |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 |
| Descrizione fisica | 1 online resource (XIII, 462 p.) |
| Disciplina | 620/.004202825536 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Logic design
Microprocessors Computer architecture Electronic digital computers—Evaluation Computer arithmetic and logic units Computer storage devices Memory management (Computer science) Electronic circuits Logic Design Processor Architectures System Performance and Evaluation Arithmetic and Logic Structures Computer Memory Structure Electronic Circuits and Systems |
| ISBN | 3-540-95948-3 |
| Classificazione |
DAT 190f
ELT 272f SS 4800 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Session 1: Low-Leakage and Subthreshold Circuits -- Subthreshold FIR Filter Architecture for Ultra Low Power Applications -- Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs -- Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits -- Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction -- Session 2: Low-Power Methods and Models -- Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating -- Intelligate: Scalable Dynamic Invariant Learning for Power Reduction -- Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption -- Power-Aware Design via Micro-architectural Link to Implementation -- Untraditional Approach to Computer Energy Reduction -- Session 3: Arithmetic and Memories -- Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication -- Power Optimization of Parallel Multipliers in Systems with Variable Word-Length -- A Design Space Comparison of 6T and 8T SRAM Core-Cells -- Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization -- Session 4: Variability and Statistical Timing -- Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic -- A Study on CMOS Time Uncertainty with Technology Scaling -- Static Timing Model Extraction for Combinational Circuits -- A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA -- Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power -- Session 5: Synchronization and Interconnect -- Logic Synthesis of Handshake Components Using Structural Clustering Techniques -- Fast Universal Synchronizers -- A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router -- PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels -- Session 6: Power Supplies and Switching Noise -- Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits -- A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint -- Generating Worst-Case Stimuli for Accurate Power Grid Analysis -- Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization -- Session 7: Low-Power Circuits; Reconfigurable Architectures -- Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements -- A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation -- Energy Efficient Elliptic Curve Processor -- Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing -- Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures -- Poster Session 1: Circuits and Methods -- Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers -- Ultra Low Voltage High Speed Differential CMOS Inverter -- Differential Capacitance Analysis -- Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey -- Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses -- Poster Session 2: Power and Delay Modeling -- Analytical High-Level Power Model for LUT-Based Components -- A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption -- Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates -- Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level -- Data Dependence of Delay Distribution for a Planar Bus -- Special Session: Power Optimizations Addressing Reconfigurable Architectures -- Towards Novel Approaches in Design Automation for FPGA Power Optimization -- Smart Enumeration: A Systematic Approach to Exhaustive Search -- An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs -- Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor -- Keynotes (Abstracts) -- Integration of Power Management Units onto the SoC -- Model to Hardware Matching for nm Scale Technologies -- Power and Profit: Engineering in the Envelope. |
| Record Nr. | UNISA-996465962903316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers / / edited by Lars Svensson, José Monteiro
| Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers / / edited by Lars Svensson, José Monteiro |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 |
| Descrizione fisica | 1 online resource (XIII, 462 p.) |
| Disciplina | 620/.004202825536 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Logic design
Microprocessors Computer architecture Electronic digital computers—Evaluation Computer arithmetic and logic units Computer storage devices Memory management (Computer science) Electronic circuits Logic Design Processor Architectures System Performance and Evaluation Arithmetic and Logic Structures Computer Memory Structure Electronic Circuits and Systems |
| ISBN | 3-540-95948-3 |
| Classificazione |
DAT 190f
ELT 272f SS 4800 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Session 1: Low-Leakage and Subthreshold Circuits -- Subthreshold FIR Filter Architecture for Ultra Low Power Applications -- Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs -- Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits -- Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction -- Session 2: Low-Power Methods and Models -- Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating -- Intelligate: Scalable Dynamic Invariant Learning for Power Reduction -- Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption -- Power-Aware Design via Micro-architectural Link to Implementation -- Untraditional Approach to Computer Energy Reduction -- Session 3: Arithmetic and Memories -- Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication -- Power Optimization of Parallel Multipliers in Systems with Variable Word-Length -- A Design Space Comparison of 6T and 8T SRAM Core-Cells -- Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization -- Session 4: Variability and Statistical Timing -- Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic -- A Study on CMOS Time Uncertainty with Technology Scaling -- Static Timing Model Extraction for Combinational Circuits -- A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA -- Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power -- Session 5: Synchronization and Interconnect -- Logic Synthesis of Handshake Components Using Structural Clustering Techniques -- Fast Universal Synchronizers -- A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router -- PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels -- Session 6: Power Supplies and Switching Noise -- Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits -- A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint -- Generating Worst-Case Stimuli for Accurate Power Grid Analysis -- Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization -- Session 7: Low-Power Circuits; Reconfigurable Architectures -- Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements -- A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation -- Energy Efficient Elliptic Curve Processor -- Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing -- Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures -- Poster Session 1: Circuits and Methods -- Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers -- Ultra Low Voltage High Speed Differential CMOS Inverter -- Differential Capacitance Analysis -- Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey -- Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses -- Poster Session 2: Power and Delay Modeling -- Analytical High-Level Power Model for LUT-Based Components -- A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption -- Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates -- Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level -- Data Dependence of Delay Distribution for a Planar Bus -- Special Session: Power Optimizations Addressing Reconfigurable Architectures -- Towards Novel Approaches in Design Automation for FPGA Power Optimization -- Smart Enumeration: A Systematic Approach to Exhaustive Search -- An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs -- Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor -- Keynotes (Abstracts) -- Integration of Power Management Units onto the SoC -- Model to Hardware Matching for nm Scale Technologies -- Power and Profit: Engineering in the Envelope. |
| Record Nr. | UNINA-9910485025903321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings / / edited by Nadine Azemard, Lars Svensson
| Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings / / edited by Nadine Azemard, Lars Svensson |
| Edizione | [1st ed. 2007.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 |
| Descrizione fisica | 1 online resource (XIV, 586 p.) |
| Disciplina | 621.395 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Logic design
Microprocessors Computer architecture Electronic digital computers—Evaluation Computer arithmetic and logic units Computer storage devices Memory management (Computer science) Electronic circuits Logic Design Processor Architectures System Performance and Evaluation Arithmetic and Logic Structures Computer Memory Structure Electronic Circuits and Systems |
| ISBN | 3-540-74442-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Session 1 - High-Level Design (1) -- System-Level Application-Specific NoC Design for Network and Multimedia Applications -- Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements -- A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms -- An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture -- Session 2 - Low Power Design Techniques -- Template Vertical Dictionary-Based Program Compression Scheme on the TTA -- Asynchronous Functional Coupling for Low Power Sensor Network Processors -- A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs -- Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports -- The Design and Implementation of a Power Efficient Embedded SRAM -- Session 3 - Low Power Analog Circuits -- Design of a Linear Power Amplifier with ±1.5V Power Supply Using ALADIN -- Settling Time Minimization of Operational Amplifiers -- Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs -- Session 4 - Statistical Static Timing Analysis -- Computation of Joint Timing Yield of Sequential Networks Considering Process Variations -- A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation -- A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits -- Session 5 - Power Modeling and Optimization -- A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect -- Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components -- Logic Style Comparison for Ultra Low Power Operation in 65nm Technology -- Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation -- Session 6 - Low Power Routing Optimization -- Clock Distribution Techniques for Low-EMI Design -- Crosstalk Waveform Modeling Using Wave Fitting -- Weakness Identification for Effective Repair of Power Distribution Network -- New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses -- On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects -- Session 7 - High Level Design (2) -- Soft Error-Aware Power Optimization Using Gate Sizing -- Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices -- RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating -- Functional Verification of Low Power Designs at RTL -- XEEMU: An Improved XScale Power Simulator -- Session 8 - Security and Asynchronous Design -- Low Power Elliptic Curve Cryptography -- Design and Test of Self-checking Asynchronous Control Circuit -- An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips -- Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA -- Session 9 - Low Power Applications -- Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform -- The Energy Scalability of Wavelet-Based, Scalable Video Decoding -- Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption -- Poster 1 - Modeling and Optimization -- Exploiting Input Variations for Energy Reduction -- A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates -- Static Power Consumption in CMOS Gates Using Independent Bodies -- Moderate Inversion: Highlights for Low Voltage Design -- On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time Systems -- Semi Custom Design: A Case Study on SIMD Shufflers -- Poster 2 - High Level Design -- Optimization for Real-Time Systems with Non-convex Power Versus Speed Models -- Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS -- A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits -- Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates -- A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW Partitioning -- Fast Calculation of Permissible Slowdown Factors for Hard Real-Time Systems -- Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate -- Poster 3 - Low Power Techniques and Applications -- A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations -- Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data -- Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply -- Low-Power Digital Filtering Based on the Logarithmic Number System -- A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling -- Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers -- Keynotes -- Design and Industrialization Challenges of Memory Dominated SOCs -- Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies -- Analog Power Modelling -- Industrial Session - Design Challenges in Real-Life Projects -- Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms -- System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving Parameters. |
| Record Nr. | UNISA-996465995703316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings / / edited by Nadine Azemard, Lars Svensson
| Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings / / edited by Nadine Azemard, Lars Svensson |
| Edizione | [1st ed. 2007.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 |
| Descrizione fisica | 1 online resource (XIV, 586 p.) |
| Disciplina | 621.395 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Logic design
Microprocessors Computer architecture Electronic digital computers—Evaluation Computer arithmetic and logic units Computer storage devices Memory management (Computer science) Electronic circuits Logic Design Processor Architectures System Performance and Evaluation Arithmetic and Logic Structures Computer Memory Structure Electronic Circuits and Systems |
| ISBN | 3-540-74442-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Session 1 - High-Level Design (1) -- System-Level Application-Specific NoC Design for Network and Multimedia Applications -- Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements -- A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms -- An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture -- Session 2 - Low Power Design Techniques -- Template Vertical Dictionary-Based Program Compression Scheme on the TTA -- Asynchronous Functional Coupling for Low Power Sensor Network Processors -- A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs -- Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports -- The Design and Implementation of a Power Efficient Embedded SRAM -- Session 3 - Low Power Analog Circuits -- Design of a Linear Power Amplifier with ±1.5V Power Supply Using ALADIN -- Settling Time Minimization of Operational Amplifiers -- Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs -- Session 4 - Statistical Static Timing Analysis -- Computation of Joint Timing Yield of Sequential Networks Considering Process Variations -- A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation -- A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits -- Session 5 - Power Modeling and Optimization -- A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect -- Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components -- Logic Style Comparison for Ultra Low Power Operation in 65nm Technology -- Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation -- Session 6 - Low Power Routing Optimization -- Clock Distribution Techniques for Low-EMI Design -- Crosstalk Waveform Modeling Using Wave Fitting -- Weakness Identification for Effective Repair of Power Distribution Network -- New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses -- On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects -- Session 7 - High Level Design (2) -- Soft Error-Aware Power Optimization Using Gate Sizing -- Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices -- RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating -- Functional Verification of Low Power Designs at RTL -- XEEMU: An Improved XScale Power Simulator -- Session 8 - Security and Asynchronous Design -- Low Power Elliptic Curve Cryptography -- Design and Test of Self-checking Asynchronous Control Circuit -- An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips -- Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA -- Session 9 - Low Power Applications -- Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform -- The Energy Scalability of Wavelet-Based, Scalable Video Decoding -- Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption -- Poster 1 - Modeling and Optimization -- Exploiting Input Variations for Energy Reduction -- A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates -- Static Power Consumption in CMOS Gates Using Independent Bodies -- Moderate Inversion: Highlights for Low Voltage Design -- On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time Systems -- Semi Custom Design: A Case Study on SIMD Shufflers -- Poster 2 - High Level Design -- Optimization for Real-Time Systems with Non-convex Power Versus Speed Models -- Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS -- A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits -- Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates -- A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW Partitioning -- Fast Calculation of Permissible Slowdown Factors for Hard Real-Time Systems -- Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate -- Poster 3 - Low Power Techniques and Applications -- A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations -- Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data -- Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply -- Low-Power Digital Filtering Based on the Logarithmic Number System -- A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling -- Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers -- Keynotes -- Design and Industrialization Challenges of Memory Dominated SOCs -- Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies -- Analog Power Modelling -- Industrial Session - Design Challenges in Real-Life Projects -- Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms -- System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving Parameters. |
| Record Nr. | UNINA-9910484643403321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings / / edited by Johan Vounckx, Nadine Azemard, Philippe Maurine
| Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings / / edited by Johan Vounckx, Nadine Azemard, Philippe Maurine |
| Edizione | [1st ed. 2006.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006 |
| Descrizione fisica | 1 online resource (XVI, 677 p.) |
| Disciplina | 621.395 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Logic design Microprocessors Computer architecture Electronic digital computers—Evaluation Computer arithmetic and logic units Computer storage devices Memory management (Computer science) Theory of Computation Logic Design Processor Architectures System Performance and Evaluation Arithmetic and Logic Structures Computer Memory Structure |
| ISBN | 3-540-39097-9 |
| Classificazione | SS 4800 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Session 1 – High-Level Design -- Session 2 – Power Estimation / Modeling -- Session 3 – Memory and Register Files -- Session 4 – Low-Power Digital Circuits -- Session 5 – Busses and Interconnects -- Session 6 – Low Power Techniques -- Session 7 – Applications and SoC Design -- Session 8 – Modeling -- Session 9 – Digital Circuits -- Session 10 – Reconfigurable and Programmable Devices -- Poster 1 -- Poster 2 -- Poster 3 -- Keynotes -- Industrial Session. |
| Record Nr. | UNISA-996466116403316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings / / edited by Johan Vounckx, Nadine Azemard, Philippe Maurine
| Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings / / edited by Johan Vounckx, Nadine Azemard, Philippe Maurine |
| Edizione | [1st ed. 2006.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006 |
| Descrizione fisica | 1 online resource (XVI, 677 p.) |
| Disciplina | 621.395 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Logic design Microprocessors Computer architecture Electronic digital computers—Evaluation Computer arithmetic and logic units Computer storage devices Memory management (Computer science) Theory of Computation Logic Design Processor Architectures System Performance and Evaluation Arithmetic and Logic Structures Computer Memory Structure |
| ISBN | 3-540-39097-9 |
| Classificazione | SS 4800 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Session 1 – High-Level Design -- Session 2 – Power Estimation / Modeling -- Session 3 – Memory and Register Files -- Session 4 – Low-Power Digital Circuits -- Session 5 – Busses and Interconnects -- Session 6 – Low Power Techniques -- Session 7 – Applications and SoC Design -- Session 8 – Modeling -- Session 9 – Digital Circuits -- Session 10 – Reconfigurable and Programmable Devices -- Poster 1 -- Poster 2 -- Poster 3 -- Keynotes -- Industrial Session. |
| Record Nr. | UNINA-9910483091303321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation [[electronic resource] ] : 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers / / edited by Rene van Leuken, Gilles Sicard
| Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation [[electronic resource] ] : 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers / / edited by Rene van Leuken, Gilles Sicard |
| Edizione | [1st ed. 2011.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2011 |
| Descrizione fisica | 1 online resource (XII, 260 p. 130 illus., 53 illus. in color.) |
| Disciplina | 004.24 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Electronic digital computers—Evaluation
Computer simulation Computer networks Software engineering Computer science Algorithms System Performance and Evaluation Computer Modelling Computer Communication Networks Software Engineering Computer Science Logic and Foundations of Programming |
| ISBN | 3-642-17752-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996466038903316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Interactive Theorem Proving [[electronic resource] ] : 9th International Conference, ITP 2018, Held as Part of the Federated Logic Conference, FloC 2018, Oxford, UK, July 9-12, 2018, Proceedings / / edited by Jeremy Avigad, Assia Mahboubi
| Interactive Theorem Proving [[electronic resource] ] : 9th International Conference, ITP 2018, Held as Part of the Federated Logic Conference, FloC 2018, Oxford, UK, July 9-12, 2018, Proceedings / / edited by Jeremy Avigad, Assia Mahboubi |
| Edizione | [1st ed. 2018.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018 |
| Descrizione fisica | 1 online resource (XVII, 642 p. 103 illus.) |
| Disciplina | 004.015113 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Machine theory
Software engineering Artificial intelligence Computer science Compilers (Computer programs) Electronic digital computers—Evaluation Formal Languages and Automata Theory Software Engineering Artificial Intelligence Computer Science Logic and Foundations of Programming Compilers and Interpreters System Performance and Evaluation |
| ISBN | 3-319-94821-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996465696803316 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
