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Design, Automation, and Test in Europe Conference and Exhibition 2003 : proceedings : Munich, Germany, March 3-7, 2003
| Design, Automation, and Test in Europe Conference and Exhibition 2003 : proceedings : Munich, Germany, March 3-7, 2003 |
| Pubbl/distr/stampa | [Place of publication not identified] : , : IEEE Computer Society, , 2003 |
| Descrizione fisica | 1 online resource (305 pages) |
| Disciplina | 621.381 |
| Collana | ACM Conferences. |
| Soggetto topico |
Electronic systems - Design and construction
Electronic circuit design - Data processing Computer-aided design - Automation Electronic industries Electrical & Computer Engineering Electrical Engineering Engineering & Applied Sciences |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | [vol. 1.] Proceedings -- [vol. 2.] Designers forum. |
| Altri titoli varianti | DATE '03 |
| Record Nr. | UNINA-9910146223203321 |
| [Place of publication not identified] : , : IEEE Computer Society, , 2003 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Design, Automation, and Test in Europe Conference and Exhibition 2004 : proceedings : Paris, France, February 16-20, 2004, sponsored by EDAA ... [et al
| Design, Automation, and Test in Europe Conference and Exhibition 2004 : proceedings : Paris, France, February 16-20, 2004, sponsored by EDAA ... [et al |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society, 2004 |
| Descrizione fisica | 1 online resource (10748 pages) |
| Disciplina | 621.381 |
| Collana | ACM Conferences |
| Soggetto topico |
Electronic systems - Design and construction
Electronic circuit design - Data processing Computer-aided design - Automation Electronic industries Electrical & Computer Engineering Electrical Engineering Engineering & Applied Sciences |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | [vol. 1.] Proceedings -- [vol. 2.] Proceedings -- [vol. 3.] Designers forum. |
| Altri titoli varianti | DATE '04 |
| Record Nr. | UNINA-9910146383303321 |
| [Place of publication not identified], : IEEE Computer Society, 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Design, Automation, and Test in Europe Conference and Exhibition 2004 : proceedings : Paris, France, February 16-20, 2004, sponsored by EDAA ... [et al
| Design, Automation, and Test in Europe Conference and Exhibition 2004 : proceedings : Paris, France, February 16-20, 2004, sponsored by EDAA ... [et al |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society, 2004 |
| Descrizione fisica | 1 online resource (10748 pages) |
| Disciplina | 621.381 |
| Collana | ACM Conferences |
| Soggetto topico |
Electronic systems - Design and construction
Electronic circuit design - Data processing Computer-aided design - Automation Electronic industries Electrical & Computer Engineering Electrical Engineering Engineering & Applied Sciences |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | [vol. 1.] Proceedings -- [vol. 2.] Proceedings -- [vol. 3.] Designers forum. |
| Altri titoli varianti | DATE '04 |
| Record Nr. | UNISA-996214778603316 |
| [Place of publication not identified], : IEEE Computer Society, 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Design, Automation, and Test in Europe Conference and Exhibition : proceedings, March 9-12, 1999, Munich, Germany
| Design, Automation, and Test in Europe Conference and Exhibition : proceedings, March 9-12, 1999, Munich, Germany |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society, 1999 |
| Disciplina | 621.381 |
| Soggetto topico |
Electronic systems - Design and construction
Electronic circuit design - Data processing Computer-aided design - Automation Electronic industries Electrical & Computer Engineering Electrical Engineering Engineering & Applied Sciences |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996217489003316 |
| [Place of publication not identified], : IEEE Computer Society, 1999 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Electronic circuits with MATLAB, PSpice, and Smith Chart / / Won Y. Yang [and nine others]
| Electronic circuits with MATLAB, PSpice, and Smith Chart / / Won Y. Yang [and nine others] |
| Autore | Yang Wŏn-yŏng <1953-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, NJ : , : Wiley, , [2020] |
| Descrizione fisica | 1 online resource (863 pages) |
| Disciplina | 621.3815 |
| Soggetto topico | Electronic circuit design - Data processing |
| ISBN |
1-5231-3297-3
1-119-59896-6 1-119-59897-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910555126003321 |
Yang Wŏn-yŏng <1953->
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| Hoboken, NJ : , : Wiley, , [2020] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Electronic circuits with MATLAB, PSpice, and Smith Chart / / Won Y. Yang [and nine others]
| Electronic circuits with MATLAB, PSpice, and Smith Chart / / Won Y. Yang [and nine others] |
| Autore | Yang Wŏn-yŏng <1953-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, NJ : , : Wiley, , [2020] |
| Descrizione fisica | 1 online resource (863 pages) |
| Disciplina | 621.3815 |
| Soggetto topico | Electronic circuit design - Data processing |
| ISBN |
1-5231-3297-3
1-119-59896-6 1-119-59897-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910810678303321 |
|
Yang Wŏn-yŏng <1953->
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| Hoboken, NJ : , : Wiley, , [2020] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Electronic design automation [[electronic resource] ] : synthesis, verification, and test / / edited by Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting (Tim) Cheng
| Electronic design automation [[electronic resource] ] : synthesis, verification, and test / / edited by Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting (Tim) Cheng |
| Autore | Wang Laung-Terng |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam, : Morgan Kaufmann/Elsevier, c2009 |
| Descrizione fisica | 1 online resource (971 p.) |
| Disciplina |
621.3810285
621.39/5 22 |
| Altri autori (Persone) |
WangLaung-Terng
ChangYao-Wen <1966-> ChengKwang-Ting <1961-> |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Electronic circuit design - Data processing
Computer-aided design |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-282-54215-X
9786612542152 0-08-092200-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Electronic Design Automation: Synthesis, Verification, and Test; Copyright Page; Contents; Preface; In the Classroom; Acknowledgments; Contributors; About the Editors; CHAPTER 1 Introduction; 1.1 Overview of electronic design automation; 1.2 Logic design automation; 1.3 Test automation; 1.4 Physical design automation; 1.5 Concluding remarks; 1.6 Exercises; Acknowledgments; References; CHAPTER 2 Fundamentals of CMOS design; 2.1 Introduction; 2.2 Integrated circuit technology; 2.3 CMOS logic; 2.4 Integrated circuit design techniques; 2.5 CMOS physical design
2.6 Low-power circuit design techniques2.7 Concluding remarks; 2.8 Exercises; Acknowledgments; References; CHAPTER 3 Design for testability; 3.1 Introduction; 3.2 Testability analysis; 3.3 Scan design; 3.4 Logic built-in self-test; 3.5 Test Compression; 3.6 Concluding remarks; 3.7 Exercises; Acknowledgments; References; CHAPTER 4 Fundamentals of algorithms; 4.1 Introduction; 4.2 Computational complexity; 4.3 Graph algorithms; 4.4 Heuristic algorithms; 4.5 Mathematical programming; 4.6 Concluding remarks; 4.7 Exercises; Acknowledgments; References CHAPTER 5 Electronic system-level design and high-level synthesis5.1 Introduction; 5.2 Fundamentals of High-level synthesis; 5.3 High-level synthesis algorithm overview; 5.4 Scheduling; 5.5 Register binding; 5.6 Functional unit binding; 5.7 Concluding remarks; 5.8 Exercises; Acknowledgments; References; CHAPTER 6 Logic synthesis in a nutshell; 6.1 Introduction; 6.2 Data Structures for Boolean representation and reasoning; 6.3 Combinational logic minimization; 6.4 Technology mapping; 6.5 Timing analysis; 6.6 Timing optimization; 6.7 Concluding remarks; 6.8 Exercises; Acknowledgments ReferencesCHAPTER 7 Test synthesis; 7.1 Introduction; 7.2 Scan design; 7.3 Logic built-in self-test (BIST) design.; 7.4 RTL Design for testability; 7.5 Concluding remarks; 7.6 Exercises; Acknowledgments; References; CHAPTER 8 Logic and circuit simulation; 8.1 Introduction; 8.2 Logic simulation models; 8.3 Logic simulation techniques; 8.4 Hardware-accelerated logic simulation; 8.5 Circuit simulation models; 8.6 Numerical methods for transient analysis; 8.7 Simulation of VLSI interconnects; 8.8 Simulation of nonlinear devices; 8.9 Concluding remarks; 8.10 Exercises; Acknowledgments; References CHAPTER 9 Functional verification9.1 Introduction; 9.2 Verification hierarchy; 9.3 Measuring verification quality; 9.4 Simulation-based approach; 9.5 Formal approaches; 9.6 Advanced research; 9.7 Concluding remarks; 9.8 Exercises; Acknowledgments; References; CHAPTER 10 Floorplanning; 10.1 Introduction; 10.2 Simulated annealing approach; 10.3 Analytical approach; 10.4 Modern floorplanning considerations; 10.5 Concluding remarks; 10.6 Exercises; Acknowledgments; References; CHAPTER 11 Placement; 11.1 Introduction; 11.2 Problem formulations; 11.3 Global placement: partitioning-based approach 11.4 Global placement: simulated annealing approach |
| Record Nr. | UNINA-9910480182803321 |
|
Wang Laung-Terng
|
||
| Amsterdam, : Morgan Kaufmann/Elsevier, c2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Electronic design automation [[electronic resource] ] : synthesis, verification, and test / / edited by Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting (Tim) Cheng
| Electronic design automation [[electronic resource] ] : synthesis, verification, and test / / edited by Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting (Tim) Cheng |
| Autore | Wang Laung-Terng |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam, : Morgan Kaufmann/Elsevier, c2009 |
| Descrizione fisica | 1 online resource (971 p.) |
| Disciplina |
621.3810285
621.39/5 22 |
| Altri autori (Persone) |
WangLaung-Terng
ChangYao-Wen <1966-> ChengKwang-Ting <1961-> |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Electronic circuit design - Data processing
Computer-aided design |
| ISBN |
1-282-54215-X
9786612542152 0-08-092200-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Electronic Design Automation: Synthesis, Verification, and Test; Copyright Page; Contents; Preface; In the Classroom; Acknowledgments; Contributors; About the Editors; CHAPTER 1 Introduction; 1.1 Overview of electronic design automation; 1.2 Logic design automation; 1.3 Test automation; 1.4 Physical design automation; 1.5 Concluding remarks; 1.6 Exercises; Acknowledgments; References; CHAPTER 2 Fundamentals of CMOS design; 2.1 Introduction; 2.2 Integrated circuit technology; 2.3 CMOS logic; 2.4 Integrated circuit design techniques; 2.5 CMOS physical design
2.6 Low-power circuit design techniques2.7 Concluding remarks; 2.8 Exercises; Acknowledgments; References; CHAPTER 3 Design for testability; 3.1 Introduction; 3.2 Testability analysis; 3.3 Scan design; 3.4 Logic built-in self-test; 3.5 Test Compression; 3.6 Concluding remarks; 3.7 Exercises; Acknowledgments; References; CHAPTER 4 Fundamentals of algorithms; 4.1 Introduction; 4.2 Computational complexity; 4.3 Graph algorithms; 4.4 Heuristic algorithms; 4.5 Mathematical programming; 4.6 Concluding remarks; 4.7 Exercises; Acknowledgments; References CHAPTER 5 Electronic system-level design and high-level synthesis5.1 Introduction; 5.2 Fundamentals of High-level synthesis; 5.3 High-level synthesis algorithm overview; 5.4 Scheduling; 5.5 Register binding; 5.6 Functional unit binding; 5.7 Concluding remarks; 5.8 Exercises; Acknowledgments; References; CHAPTER 6 Logic synthesis in a nutshell; 6.1 Introduction; 6.2 Data Structures for Boolean representation and reasoning; 6.3 Combinational logic minimization; 6.4 Technology mapping; 6.5 Timing analysis; 6.6 Timing optimization; 6.7 Concluding remarks; 6.8 Exercises; Acknowledgments ReferencesCHAPTER 7 Test synthesis; 7.1 Introduction; 7.2 Scan design; 7.3 Logic built-in self-test (BIST) design.; 7.4 RTL Design for testability; 7.5 Concluding remarks; 7.6 Exercises; Acknowledgments; References; CHAPTER 8 Logic and circuit simulation; 8.1 Introduction; 8.2 Logic simulation models; 8.3 Logic simulation techniques; 8.4 Hardware-accelerated logic simulation; 8.5 Circuit simulation models; 8.6 Numerical methods for transient analysis; 8.7 Simulation of VLSI interconnects; 8.8 Simulation of nonlinear devices; 8.9 Concluding remarks; 8.10 Exercises; Acknowledgments; References CHAPTER 9 Functional verification9.1 Introduction; 9.2 Verification hierarchy; 9.3 Measuring verification quality; 9.4 Simulation-based approach; 9.5 Formal approaches; 9.6 Advanced research; 9.7 Concluding remarks; 9.8 Exercises; Acknowledgments; References; CHAPTER 10 Floorplanning; 10.1 Introduction; 10.2 Simulated annealing approach; 10.3 Analytical approach; 10.4 Modern floorplanning considerations; 10.5 Concluding remarks; 10.6 Exercises; Acknowledgments; References; CHAPTER 11 Placement; 11.1 Introduction; 11.2 Problem formulations; 11.3 Global placement: partitioning-based approach 11.4 Global placement: simulated annealing approach |
| Record Nr. | UNINA-9910783095403321 |
|
Wang Laung-Terng
|
||
| Amsterdam, : Morgan Kaufmann/Elsevier, c2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Electronic design automation [[electronic resource] ] : synthesis, verification, and test / / edited by Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting (Tim) Cheng
| Electronic design automation [[electronic resource] ] : synthesis, verification, and test / / edited by Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting (Tim) Cheng |
| Autore | Wang Laung-Terng |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam, : Morgan Kaufmann/Elsevier, c2009 |
| Descrizione fisica | 1 online resource (971 p.) |
| Disciplina |
621.3810285
621.39/5 22 |
| Altri autori (Persone) |
WangLaung-Terng
ChangYao-Wen <1966-> ChengKwang-Ting <1961-> |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Electronic circuit design - Data processing
Computer-aided design |
| ISBN |
1-282-54215-X
9786612542152 0-08-092200-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Electronic Design Automation: Synthesis, Verification, and Test; Copyright Page; Contents; Preface; In the Classroom; Acknowledgments; Contributors; About the Editors; CHAPTER 1 Introduction; 1.1 Overview of electronic design automation; 1.2 Logic design automation; 1.3 Test automation; 1.4 Physical design automation; 1.5 Concluding remarks; 1.6 Exercises; Acknowledgments; References; CHAPTER 2 Fundamentals of CMOS design; 2.1 Introduction; 2.2 Integrated circuit technology; 2.3 CMOS logic; 2.4 Integrated circuit design techniques; 2.5 CMOS physical design
2.6 Low-power circuit design techniques2.7 Concluding remarks; 2.8 Exercises; Acknowledgments; References; CHAPTER 3 Design for testability; 3.1 Introduction; 3.2 Testability analysis; 3.3 Scan design; 3.4 Logic built-in self-test; 3.5 Test Compression; 3.6 Concluding remarks; 3.7 Exercises; Acknowledgments; References; CHAPTER 4 Fundamentals of algorithms; 4.1 Introduction; 4.2 Computational complexity; 4.3 Graph algorithms; 4.4 Heuristic algorithms; 4.5 Mathematical programming; 4.6 Concluding remarks; 4.7 Exercises; Acknowledgments; References CHAPTER 5 Electronic system-level design and high-level synthesis5.1 Introduction; 5.2 Fundamentals of High-level synthesis; 5.3 High-level synthesis algorithm overview; 5.4 Scheduling; 5.5 Register binding; 5.6 Functional unit binding; 5.7 Concluding remarks; 5.8 Exercises; Acknowledgments; References; CHAPTER 6 Logic synthesis in a nutshell; 6.1 Introduction; 6.2 Data Structures for Boolean representation and reasoning; 6.3 Combinational logic minimization; 6.4 Technology mapping; 6.5 Timing analysis; 6.6 Timing optimization; 6.7 Concluding remarks; 6.8 Exercises; Acknowledgments ReferencesCHAPTER 7 Test synthesis; 7.1 Introduction; 7.2 Scan design; 7.3 Logic built-in self-test (BIST) design.; 7.4 RTL Design for testability; 7.5 Concluding remarks; 7.6 Exercises; Acknowledgments; References; CHAPTER 8 Logic and circuit simulation; 8.1 Introduction; 8.2 Logic simulation models; 8.3 Logic simulation techniques; 8.4 Hardware-accelerated logic simulation; 8.5 Circuit simulation models; 8.6 Numerical methods for transient analysis; 8.7 Simulation of VLSI interconnects; 8.8 Simulation of nonlinear devices; 8.9 Concluding remarks; 8.10 Exercises; Acknowledgments; References CHAPTER 9 Functional verification9.1 Introduction; 9.2 Verification hierarchy; 9.3 Measuring verification quality; 9.4 Simulation-based approach; 9.5 Formal approaches; 9.6 Advanced research; 9.7 Concluding remarks; 9.8 Exercises; Acknowledgments; References; CHAPTER 10 Floorplanning; 10.1 Introduction; 10.2 Simulated annealing approach; 10.3 Analytical approach; 10.4 Modern floorplanning considerations; 10.5 Concluding remarks; 10.6 Exercises; Acknowledgments; References; CHAPTER 11 Placement; 11.1 Introduction; 11.2 Problem formulations; 11.3 Global placement: partitioning-based approach 11.4 Global placement: simulated annealing approach |
| Record Nr. | UNINA-9910809356603321 |
|
Wang Laung-Terng
|
||
| Amsterdam, : Morgan Kaufmann/Elsevier, c2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
European Conference on Design Automation, 3rd (EDAC '92)
| European Conference on Design Automation, 3rd (EDAC '92) |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society Press, 1992 |
| Descrizione fisica | 1 online resource (592 pages) |
| Disciplina | 620.0042 |
| Soggetto topico |
Computer-aided design
Electronic circuit design - Data processing |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996202453603316 |
| [Place of publication not identified], : IEEE Computer Society Press, 1992 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
