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MARC Lista (tabellare)
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers / / edited by Lars Svensson, José Monteiro
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers / / edited by Lars Svensson, José Monteiro
Edizione [1st ed. 2009.]
Pubbl/distr/stampa Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009
Descrizione fisica 1 online resource (XIII, 462 p.)
Disciplina 620/.004202825536
Collana Theoretical Computer Science and General Issues
Soggetto topico Logic design
Microprocessors
Computer architecture
Electronic digital computers—Evaluation
Computer arithmetic and logic units
Computer storage devices
Memory management (Computer science)
Electronic circuits
Logic Design
Processor Architectures
System Performance and Evaluation
Arithmetic and Logic Structures
Computer Memory Structure
Electronic Circuits and Systems
ISBN 3-540-95948-3
Classificazione DAT 190f
ELT 272f
SS 4800
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Session 1: Low-Leakage and Subthreshold Circuits -- Subthreshold FIR Filter Architecture for Ultra Low Power Applications -- Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs -- Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits -- Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction -- Session 2: Low-Power Methods and Models -- Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating -- Intelligate: Scalable Dynamic Invariant Learning for Power Reduction -- Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption -- Power-Aware Design via Micro-architectural Link to Implementation -- Untraditional Approach to Computer Energy Reduction -- Session 3: Arithmetic and Memories -- Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication -- Power Optimization of Parallel Multipliers in Systems with Variable Word-Length -- A Design Space Comparison of 6T and 8T SRAM Core-Cells -- Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization -- Session 4: Variability and Statistical Timing -- Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic -- A Study on CMOS Time Uncertainty with Technology Scaling -- Static Timing Model Extraction for Combinational Circuits -- A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA -- Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power -- Session 5: Synchronization and Interconnect -- Logic Synthesis of Handshake Components Using Structural Clustering Techniques -- Fast Universal Synchronizers -- A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router -- PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels -- Session 6: Power Supplies and Switching Noise -- Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits -- A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint -- Generating Worst-Case Stimuli for Accurate Power Grid Analysis -- Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization -- Session 7: Low-Power Circuits; Reconfigurable Architectures -- Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements -- A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation -- Energy Efficient Elliptic Curve Processor -- Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing -- Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures -- Poster Session 1: Circuits and Methods -- Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers -- Ultra Low Voltage High Speed Differential CMOS Inverter -- Differential Capacitance Analysis -- Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey -- Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses -- Poster Session 2: Power and Delay Modeling -- Analytical High-Level Power Model for LUT-Based Components -- A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption -- Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates -- Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level -- Data Dependence of Delay Distribution for a Planar Bus -- Special Session: Power Optimizations Addressing Reconfigurable Architectures -- Towards Novel Approaches in Design Automation for FPGA Power Optimization -- Smart Enumeration: A Systematic Approach to Exhaustive Search -- An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs -- Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor -- Keynotes (Abstracts) -- Integration of Power Management Units onto the SoC -- Model to Hardware Matching for nm Scale Technologies -- Power and Profit: Engineering in the Envelope.
Record Nr. UNINA-9910485025903321
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings / / edited by Nadine Azemard, Lars Svensson
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings / / edited by Nadine Azemard, Lars Svensson
Edizione [1st ed. 2007.]
Pubbl/distr/stampa Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007
Descrizione fisica 1 online resource (XIV, 586 p.)
Disciplina 621.395
Collana Theoretical Computer Science and General Issues
Soggetto topico Logic design
Microprocessors
Computer architecture
Electronic digital computers—Evaluation
Computer arithmetic and logic units
Computer storage devices
Memory management (Computer science)
Electronic circuits
Logic Design
Processor Architectures
System Performance and Evaluation
Arithmetic and Logic Structures
Computer Memory Structure
Electronic Circuits and Systems
ISBN 3-540-74442-8
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Session 1 - High-Level Design (1) -- System-Level Application-Specific NoC Design for Network and Multimedia Applications -- Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements -- A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms -- An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture -- Session 2 - Low Power Design Techniques -- Template Vertical Dictionary-Based Program Compression Scheme on the TTA -- Asynchronous Functional Coupling for Low Power Sensor Network Processors -- A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs -- Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports -- The Design and Implementation of a Power Efficient Embedded SRAM -- Session 3 - Low Power Analog Circuits -- Design of a Linear Power Amplifier with ±1.5V Power Supply Using ALADIN -- Settling Time Minimization of Operational Amplifiers -- Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs -- Session 4 - Statistical Static Timing Analysis -- Computation of Joint Timing Yield of Sequential Networks Considering Process Variations -- A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation -- A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits -- Session 5 - Power Modeling and Optimization -- A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect -- Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components -- Logic Style Comparison for Ultra Low Power Operation in 65nm Technology -- Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation -- Session 6 - Low Power Routing Optimization -- Clock Distribution Techniques for Low-EMI Design -- Crosstalk Waveform Modeling Using Wave Fitting -- Weakness Identification for Effective Repair of Power Distribution Network -- New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses -- On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects -- Session 7 - High Level Design (2) -- Soft Error-Aware Power Optimization Using Gate Sizing -- Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices -- RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating -- Functional Verification of Low Power Designs at RTL -- XEEMU: An Improved XScale Power Simulator -- Session 8 - Security and Asynchronous Design -- Low Power Elliptic Curve Cryptography -- Design and Test of Self-checking Asynchronous Control Circuit -- An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips -- Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA -- Session 9 - Low Power Applications -- Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform -- The Energy Scalability of Wavelet-Based, Scalable Video Decoding -- Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption -- Poster 1 - Modeling and Optimization -- Exploiting Input Variations for Energy Reduction -- A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates -- Static Power Consumption in CMOS Gates Using Independent Bodies -- Moderate Inversion: Highlights for Low Voltage Design -- On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time Systems -- Semi Custom Design: A Case Study on SIMD Shufflers -- Poster 2 - High Level Design -- Optimization for Real-Time Systems with Non-convex Power Versus Speed Models -- Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS -- A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits -- Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates -- A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW Partitioning -- Fast Calculation of Permissible Slowdown Factors for Hard Real-Time Systems -- Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate -- Poster 3 - Low Power Techniques and Applications -- A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations -- Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data -- Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply -- Low-Power Digital Filtering Based on the Logarithmic Number System -- A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling -- Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers -- Keynotes -- Design and Industrialization Challenges of Memory Dominated SOCs -- Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies -- Analog Power Modelling -- Industrial Session - Design Challenges in Real-Life Projects -- Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms -- System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving Parameters.
Record Nr. UNISA-996465995703316
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings / / edited by Nadine Azemard, Lars Svensson
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings / / edited by Nadine Azemard, Lars Svensson
Edizione [1st ed. 2007.]
Pubbl/distr/stampa Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007
Descrizione fisica 1 online resource (XIV, 586 p.)
Disciplina 621.395
Collana Theoretical Computer Science and General Issues
Soggetto topico Logic design
Microprocessors
Computer architecture
Electronic digital computers—Evaluation
Computer arithmetic and logic units
Computer storage devices
Memory management (Computer science)
Electronic circuits
Logic Design
Processor Architectures
System Performance and Evaluation
Arithmetic and Logic Structures
Computer Memory Structure
Electronic Circuits and Systems
ISBN 3-540-74442-8
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Session 1 - High-Level Design (1) -- System-Level Application-Specific NoC Design for Network and Multimedia Applications -- Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements -- A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms -- An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture -- Session 2 - Low Power Design Techniques -- Template Vertical Dictionary-Based Program Compression Scheme on the TTA -- Asynchronous Functional Coupling for Low Power Sensor Network Processors -- A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs -- Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports -- The Design and Implementation of a Power Efficient Embedded SRAM -- Session 3 - Low Power Analog Circuits -- Design of a Linear Power Amplifier with ±1.5V Power Supply Using ALADIN -- Settling Time Minimization of Operational Amplifiers -- Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs -- Session 4 - Statistical Static Timing Analysis -- Computation of Joint Timing Yield of Sequential Networks Considering Process Variations -- A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation -- A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits -- Session 5 - Power Modeling and Optimization -- A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect -- Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components -- Logic Style Comparison for Ultra Low Power Operation in 65nm Technology -- Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation -- Session 6 - Low Power Routing Optimization -- Clock Distribution Techniques for Low-EMI Design -- Crosstalk Waveform Modeling Using Wave Fitting -- Weakness Identification for Effective Repair of Power Distribution Network -- New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses -- On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects -- Session 7 - High Level Design (2) -- Soft Error-Aware Power Optimization Using Gate Sizing -- Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices -- RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating -- Functional Verification of Low Power Designs at RTL -- XEEMU: An Improved XScale Power Simulator -- Session 8 - Security and Asynchronous Design -- Low Power Elliptic Curve Cryptography -- Design and Test of Self-checking Asynchronous Control Circuit -- An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips -- Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA -- Session 9 - Low Power Applications -- Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform -- The Energy Scalability of Wavelet-Based, Scalable Video Decoding -- Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption -- Poster 1 - Modeling and Optimization -- Exploiting Input Variations for Energy Reduction -- A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates -- Static Power Consumption in CMOS Gates Using Independent Bodies -- Moderate Inversion: Highlights for Low Voltage Design -- On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time Systems -- Semi Custom Design: A Case Study on SIMD Shufflers -- Poster 2 - High Level Design -- Optimization for Real-Time Systems with Non-convex Power Versus Speed Models -- Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS -- A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits -- Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates -- A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW Partitioning -- Fast Calculation of Permissible Slowdown Factors for Hard Real-Time Systems -- Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate -- Poster 3 - Low Power Techniques and Applications -- A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations -- Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data -- Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply -- Low-Power Digital Filtering Based on the Logarithmic Number System -- A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling -- Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers -- Keynotes -- Design and Industrialization Challenges of Memory Dominated SOCs -- Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies -- Analog Power Modelling -- Industrial Session - Design Challenges in Real-Life Projects -- Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms -- System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving Parameters.
Record Nr. UNINA-9910484643403321
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Interconnect Technologies for Integrated Circuits and Flexible Electronics [[electronic resource] /] / edited by Yash Agrawal, Kavicharan Mummaneni, P. Uma Sathyakam
Interconnect Technologies for Integrated Circuits and Flexible Electronics [[electronic resource] /] / edited by Yash Agrawal, Kavicharan Mummaneni, P. Uma Sathyakam
Autore Agrawal Yash
Edizione [1st ed. 2024.]
Pubbl/distr/stampa Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2024
Descrizione fisica 1 online resource (286 pages)
Disciplina 621.3815
Altri autori (Persone) MummaneniKavicharan
SathyakamP. Uma
Collana Springer Tracts in Electrical and Electronics Engineering
Soggetto topico Electronic circuits
Telecommunication
Electronic Circuits and Systems
Communications Engineering, Networks
ISBN 981-9944-76-7
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Chapter 1. An Efficient Model Order Reduction of Interconnects using Machine Learning for Timing Analysis -- Chapter 2. Delay and Overshoot Modelling of Asymmetric T-Tree Interconnects -- Chapter 3. Explicit Power-Delay Models for On-chip Copper and SWCNT Bundle Interconnects -- Chapter 4. Modelling and Analysis of Copper and Carbon Nanotube VLSI Interconnects -- Chapter 6. Through Silicon Vias for 3D Integration – A Mini Review -- Chapter 7. Neural Networks for Fast Design Space Exploration of On-chip Interconnect Networks -- Chapter 8. A Comprehensive Analysis of Emerging Variants of Swarm Intelligence for Circuits and Systems -- Chapter 9. PAM3: History, Algorithm, and Performance Comparison to NRZ, PAM4 -- Chapter 10. Emerging Interconnect Technologies for Integrated Circuit and Flexible Electronics -- Chapter 11. Contact and Interconnect Considerations for Organic and Flexible Electronics -- Chapter 12. Stretchable Interconnects: Materials, Geometry, Fabrication and Applications -- Chapter 13. Flexible Electronics: A Critical Review -- Chapter 14. Delay Analysis of Different Stretchable Interconnect Structures -- Chapter 15. Flexible Sensors for Plant Disease Monitoring -- Chapter 16. GaitTracker: A Digital Platform for Measuring, Detecting and Analyzing Gait Changes.
Record Nr. UNINA-9910760287703321
Agrawal Yash  
Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2024
Materiale a stampa
Lo trovi qui: Univ. Federico II
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Introduction to Logic Circuits & Logic Design with Verilog [[electronic resource] /] / by Brock J. LaMeres
Introduction to Logic Circuits & Logic Design with Verilog [[electronic resource] /] / by Brock J. LaMeres
Autore LaMeres Brock J.
Edizione [3rd ed. 2024.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024
Descrizione fisica 1 online resource (536 pages)
Disciplina 621.3815
Soggetto topico Electronic circuits
Microprocessors
Computer architecture
Logic design
Electronic Circuits and Systems
Processor Architectures
Logic Design
ISBN 3-031-43946-5
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction – Analog Vs. Digital -- Number Systems -- Digital Circuitry & Interfacing -- Combinational Logic Design -- Verilog (Part 1) -- MSI Logic -- Sequential Logic Design -- Verilog (Part 2) -- Behavioral Modeling of Sequential Logic -- Memory -- Programmable Logic -- Arithmetic Circuits -- Computer System Design -- Appendix A: List of Worked Examples.
Record Nr. UNINA-9910760271903321
LaMeres Brock J.  
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Introduction to Logic Circuits & Logic Design with VHDL [[electronic resource] /] / by Brock J. LaMeres
Introduction to Logic Circuits & Logic Design with VHDL [[electronic resource] /] / by Brock J. LaMeres
Autore LaMeres Brock J.
Edizione [3rd ed. 2024.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024
Descrizione fisica 1 online resource (544 pages)
Disciplina 371.320973
Soggetto topico Electronic circuits
Microprocessors
Computer architecture
Logic design
Electronic Circuits and Systems
Processor Architectures
Logic Design
ISBN 3-031-42547-2
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction -- Analog Vs. Digital -- Number Systems -- Digital Circuitry & Interfacing -- Combinational Logic Design -- VHDL (Part 1) -- MSI Logic -- Sequential Logic Design -- VHDL (Part 2) -- Behavioral Modeling Of Sequential Logic -- Memory -- Programmable Logic -- Arithmetic Circuits -- Computer System Design -- Floating-Point Systems.
Record Nr. UNINA-9910760250003321
LaMeres Brock J.  
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Joe Pawsey and the Founding of Australian Radio Astronomy [[electronic resource] ] : Early Discoveries, from the Sun to the Cosmos / / by W. M. Goss, Claire Hooker, Ronald D. Ekers
Joe Pawsey and the Founding of Australian Radio Astronomy [[electronic resource] ] : Early Discoveries, from the Sun to the Cosmos / / by W. M. Goss, Claire Hooker, Ronald D. Ekers
Autore Goss W. M
Edizione [1st ed. 2023.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023
Descrizione fisica 1 electronic resource (815 p.)
Disciplina 509
Altri autori (Persone) HookerClaire
EkersRonald D
Collana Historical & Cultural Astronomy
Soggetto topico Physics—History
Astronomy—Observations
Electronic circuits
Measurement
Measuring instruments
History of Physics and Astronomy
Astronomy, Observations and Techniques
Electronic Circuits and Systems
Measurement Science and Instrumentation
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Foreword -- Preface -- Acknowledgements -- Childhood -- Becoming a Scientist -- WWII 1939-1945 -- Hot Corona -- Quiet Leadership -- Towards a Bigger Science -- The Development of Understanding -- Death and Legacy -- Appendix.
Record Nr. UNINA-9910640399803321
Goss W. M  
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023
Materiale a stampa
Lo trovi qui: Univ. Federico II
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Lecture Notes in Analogue Electronics [[electronic resource] ] : Electronic Signal Amplification and Linear Oscillators / / by Vančo Litovski
Lecture Notes in Analogue Electronics [[electronic resource] ] : Electronic Signal Amplification and Linear Oscillators / / by Vančo Litovski
Autore Litovski Vančo
Edizione [1st ed. 2023.]
Pubbl/distr/stampa Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2023
Descrizione fisica 1 online resource (691 pages)
Disciplina 621.381533
Collana Lecture Notes in Electrical Engineering
Soggetto topico Power electronics
Electronic circuits
Signal processing
Power Electronics
Electronic Circuits and Systems
Digital and Analog Signal Processing
ISBN 981-9950-95-3
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction to LNAE -- Biasing The Basic Electronic Amplifier Configurations -- Frequency Domain Analysis Of The Basic Amplifier Configurations -- Feedback Amplifiers -- Linear Oscillators.
Record Nr. UNINA-9910760290903321
Litovski Vančo  
Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2023
Materiale a stampa
Lo trovi qui: Univ. Federico II
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Logic Functions and Equations [[electronic resource] ] : Fundamentals and Applications using the XBOOLE-Monitor / / by Bernd Steinbach, Christian Posthoff
Logic Functions and Equations [[electronic resource] ] : Fundamentals and Applications using the XBOOLE-Monitor / / by Bernd Steinbach, Christian Posthoff
Autore Steinbach Bernd
Edizione [3rd ed. 2022.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2022
Descrizione fisica 1 online resource (818 pages)
Disciplina 511.324
Soggetto topico Electronic circuits
Logic design
Computer science - Mathematics
Discrete mathematics
Electronic Circuits and Systems
Logic Design
Discrete Mathematics in Computer Science
Àlgebra de Boole
Lògica matemàtica
Teoria de màquines
Soggetto genere / forma Llibres electrònics
ISBN 3-030-88945-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Part I Theoretical Foundations -- 1. Basic Algebraic Structures -- 2. Logic Functions -- 3. Logic Equations -- 4. Boolean Differential Calculus -- 5. Sets, Lattices, and Classes of Logic Functions -- Part II Applications -- 6. Logic, Arithmetic, and Special Functions -- 7. SAT-Problems -- 8. Extremely Complex Problems -- 9. Combinational Circuits -- 10. Sequential Circuits -- References -- Index.
Record Nr. UNISA-996479368403316
Steinbach Bernd  
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2022
Materiale a stampa
Lo trovi qui: Univ. di Salerno
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Logic Functions and Equations [[electronic resource] ] : Fundamentals and Applications using the XBOOLE-Monitor / / by Bernd Steinbach, Christian Posthoff
Logic Functions and Equations [[electronic resource] ] : Fundamentals and Applications using the XBOOLE-Monitor / / by Bernd Steinbach, Christian Posthoff
Autore Steinbach Bernd
Edizione [3rd ed. 2022.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2022
Descrizione fisica 1 online resource (818 pages)
Disciplina 511.324
Soggetto topico Electronic circuits
Logic design
Computer science - Mathematics
Discrete mathematics
Electronic Circuits and Systems
Logic Design
Discrete Mathematics in Computer Science
Àlgebra de Boole
Lògica matemàtica
Teoria de màquines
Soggetto genere / forma Llibres electrònics
ISBN 3-030-88945-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Part I Theoretical Foundations -- 1. Basic Algebraic Structures -- 2. Logic Functions -- 3. Logic Equations -- 4. Boolean Differential Calculus -- 5. Sets, Lattices, and Classes of Logic Functions -- Part II Applications -- 6. Logic, Arithmetic, and Special Functions -- 7. SAT-Problems -- 8. Extremely Complex Problems -- 9. Combinational Circuits -- 10. Sequential Circuits -- References -- Index.
Record Nr. UNINA-9910574861303321
Steinbach Bernd  
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2022
Materiale a stampa
Lo trovi qui: Univ. Federico II
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