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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings / / edited by Nadine Azemard, Lars Svensson
| Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings / / edited by Nadine Azemard, Lars Svensson |
| Edizione | [1st ed. 2007.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 |
| Descrizione fisica | 1 online resource (XIV, 586 p.) |
| Disciplina | 621.395 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Logic design
Microprocessors Computer architecture Electronic digital computers—Evaluation Computer arithmetic and logic units Computer storage devices Memory management (Computer science) Electronic circuits Logic Design Processor Architectures System Performance and Evaluation Arithmetic and Logic Structures Computer Memory Structure Electronic Circuits and Systems |
| ISBN | 3-540-74442-8 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Session 1 - High-Level Design (1) -- System-Level Application-Specific NoC Design for Network and Multimedia Applications -- Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements -- A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms -- An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture -- Session 2 - Low Power Design Techniques -- Template Vertical Dictionary-Based Program Compression Scheme on the TTA -- Asynchronous Functional Coupling for Low Power Sensor Network Processors -- A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs -- Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports -- The Design and Implementation of a Power Efficient Embedded SRAM -- Session 3 - Low Power Analog Circuits -- Design of a Linear Power Amplifier with ±1.5V Power Supply Using ALADIN -- Settling Time Minimization of Operational Amplifiers -- Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs -- Session 4 - Statistical Static Timing Analysis -- Computation of Joint Timing Yield of Sequential Networks Considering Process Variations -- A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation -- A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits -- Session 5 - Power Modeling and Optimization -- A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect -- Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components -- Logic Style Comparison for Ultra Low Power Operation in 65nm Technology -- Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation -- Session 6 - Low Power Routing Optimization -- Clock Distribution Techniques for Low-EMI Design -- Crosstalk Waveform Modeling Using Wave Fitting -- Weakness Identification for Effective Repair of Power Distribution Network -- New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses -- On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects -- Session 7 - High Level Design (2) -- Soft Error-Aware Power Optimization Using Gate Sizing -- Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices -- RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating -- Functional Verification of Low Power Designs at RTL -- XEEMU: An Improved XScale Power Simulator -- Session 8 - Security and Asynchronous Design -- Low Power Elliptic Curve Cryptography -- Design and Test of Self-checking Asynchronous Control Circuit -- An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips -- Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA -- Session 9 - Low Power Applications -- Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform -- The Energy Scalability of Wavelet-Based, Scalable Video Decoding -- Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption -- Poster 1 - Modeling and Optimization -- Exploiting Input Variations for Energy Reduction -- A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates -- Static Power Consumption in CMOS Gates Using Independent Bodies -- Moderate Inversion: Highlights for Low Voltage Design -- On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time Systems -- Semi Custom Design: A Case Study on SIMD Shufflers -- Poster 2 - High Level Design -- Optimization for Real-Time Systems with Non-convex Power Versus Speed Models -- Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS -- A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits -- Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates -- A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW Partitioning -- Fast Calculation of Permissible Slowdown Factors for Hard Real-Time Systems -- Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate -- Poster 3 - Low Power Techniques and Applications -- A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations -- Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data -- Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply -- Low-Power Digital Filtering Based on the Logarithmic Number System -- A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling -- Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers -- Keynotes -- Design and Industrialization Challenges of Memory Dominated SOCs -- Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies -- Analog Power Modelling -- Industrial Session - Design Challenges in Real-Life Projects -- Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms -- System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving Parameters. |
| Record Nr. | UNISA-996465995703316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings / / edited by Nadine Azemard, Lars Svensson
| Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings / / edited by Nadine Azemard, Lars Svensson |
| Edizione | [1st ed. 2007.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 |
| Descrizione fisica | 1 online resource (XIV, 586 p.) |
| Disciplina | 621.395 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Logic design
Microprocessors Computer architecture Electronic digital computers—Evaluation Computer arithmetic and logic units Computer storage devices Memory management (Computer science) Electronic circuits Logic Design Processor Architectures System Performance and Evaluation Arithmetic and Logic Structures Computer Memory Structure Electronic Circuits and Systems |
| ISBN | 3-540-74442-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Session 1 - High-Level Design (1) -- System-Level Application-Specific NoC Design for Network and Multimedia Applications -- Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements -- A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms -- An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture -- Session 2 - Low Power Design Techniques -- Template Vertical Dictionary-Based Program Compression Scheme on the TTA -- Asynchronous Functional Coupling for Low Power Sensor Network Processors -- A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs -- Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports -- The Design and Implementation of a Power Efficient Embedded SRAM -- Session 3 - Low Power Analog Circuits -- Design of a Linear Power Amplifier with ±1.5V Power Supply Using ALADIN -- Settling Time Minimization of Operational Amplifiers -- Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs -- Session 4 - Statistical Static Timing Analysis -- Computation of Joint Timing Yield of Sequential Networks Considering Process Variations -- A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation -- A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits -- Session 5 - Power Modeling and Optimization -- A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect -- Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components -- Logic Style Comparison for Ultra Low Power Operation in 65nm Technology -- Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation -- Session 6 - Low Power Routing Optimization -- Clock Distribution Techniques for Low-EMI Design -- Crosstalk Waveform Modeling Using Wave Fitting -- Weakness Identification for Effective Repair of Power Distribution Network -- New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses -- On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects -- Session 7 - High Level Design (2) -- Soft Error-Aware Power Optimization Using Gate Sizing -- Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices -- RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating -- Functional Verification of Low Power Designs at RTL -- XEEMU: An Improved XScale Power Simulator -- Session 8 - Security and Asynchronous Design -- Low Power Elliptic Curve Cryptography -- Design and Test of Self-checking Asynchronous Control Circuit -- An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips -- Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA -- Session 9 - Low Power Applications -- Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform -- The Energy Scalability of Wavelet-Based, Scalable Video Decoding -- Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption -- Poster 1 - Modeling and Optimization -- Exploiting Input Variations for Energy Reduction -- A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates -- Static Power Consumption in CMOS Gates Using Independent Bodies -- Moderate Inversion: Highlights for Low Voltage Design -- On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time Systems -- Semi Custom Design: A Case Study on SIMD Shufflers -- Poster 2 - High Level Design -- Optimization for Real-Time Systems with Non-convex Power Versus Speed Models -- Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS -- A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits -- Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates -- A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW Partitioning -- Fast Calculation of Permissible Slowdown Factors for Hard Real-Time Systems -- Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate -- Poster 3 - Low Power Techniques and Applications -- A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations -- Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data -- Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply -- Low-Power Digital Filtering Based on the Logarithmic Number System -- A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling -- Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers -- Keynotes -- Design and Industrialization Challenges of Memory Dominated SOCs -- Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies -- Analog Power Modelling -- Industrial Session - Design Challenges in Real-Life Projects -- Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms -- System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving Parameters. |
| Record Nr. | UNINA-9910484643403321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Introduction to Logic Circuits & Logic Design with Verilog / / by Brock J. LaMeres
| Introduction to Logic Circuits & Logic Design with Verilog / / by Brock J. LaMeres |
| Autore | LaMeres Brock J. |
| Edizione | [3rd ed. 2024.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024 |
| Descrizione fisica | 1 online resource (536 pages) |
| Disciplina | 621.3815 |
| Soggetto topico |
Electronic circuits
Microprocessors Computer architecture Logic design Electronic Circuits and Systems Processor Architectures Logic Design |
| ISBN | 3-031-43946-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction – Analog Vs. Digital -- Number Systems -- Digital Circuitry & Interfacing -- Combinational Logic Design -- Verilog (Part 1) -- MSI Logic -- Sequential Logic Design -- Verilog (Part 2) -- Behavioral Modeling of Sequential Logic -- Memory -- Programmable Logic -- Arithmetic Circuits -- Computer System Design -- Appendix A: List of Worked Examples. |
| Record Nr. | UNINA-9910760271903321 |
LaMeres Brock J.
|
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Introduction to Logic Circuits & Logic Design with VHDL / / by Brock J. LaMeres
| Introduction to Logic Circuits & Logic Design with VHDL / / by Brock J. LaMeres |
| Autore | LaMeres Brock J. |
| Edizione | [3rd ed. 2024.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024 |
| Descrizione fisica | 1 online resource (544 pages) |
| Disciplina | 371.320973 |
| Soggetto topico |
Electronic circuits
Microprocessors Computer architecture Logic design Electronic Circuits and Systems Processor Architectures Logic Design |
| ISBN | 3-031-42547-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Analog Vs. Digital -- Number Systems -- Digital Circuitry & Interfacing -- Combinational Logic Design -- VHDL (Part 1) -- MSI Logic -- Sequential Logic Design -- VHDL (Part 2) -- Behavioral Modeling Of Sequential Logic -- Memory -- Programmable Logic -- Arithmetic Circuits -- Computer System Design -- Floating-Point Systems. |
| Record Nr. | UNINA-9910760250003321 |
|
LaMeres Brock J.
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Introduction to Logic Circuits & Logic Design with VHDL / / by Brock J. LaMeres
| Introduction to Logic Circuits & Logic Design with VHDL / / by Brock J. LaMeres |
| Autore | LaMeres Brock J |
| Edizione | [2nd ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (XVI, 499 p. 505 illus., 454 illus. in color.) |
| Disciplina | 621.395 |
| Soggetto topico |
Electronic circuits
Microprocessors Computer architecture Logic design Electronic Circuits and Systems Processor Architectures Logic Design |
| ISBN | 3-030-12489-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Analog Vs. Digital -- Number Systems -- Digital Circuitry & Interfacing -- Combinational Logic Design -- VHDL (Part 1) -- MSI Logic -- Sequential Logic Design -- VHDL (Part 2) -- Behavioral Modeling Of Sequential Logic -- Memory -- Programmable Logic -- Arithmetic Circuits -- Computer System Design. . |
| Record Nr. | UNINA-9910337640603321 |
|
LaMeres Brock J
|
||
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Introduction to Logic Circuits & Logic Design with VHDL / / by Brock J. LaMeres
| Introduction to Logic Circuits & Logic Design with VHDL / / by Brock J. LaMeres |
| Autore | LaMeres Brock J |
| Edizione | [1st ed. 2017.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2017 |
| Descrizione fisica | 1 online resource (XVI, 475 p. 485 illus., 427 illus. in color.) |
| Disciplina | 621.395 |
| Soggetto topico |
Electronic circuits
Microprocessors Computer architecture Logic design Electronic Circuits and Systems Processor Architectures Logic Design |
| ISBN | 3-319-34195-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Analog Vs. Digital -- Number Systems -- Digital Circuitry & Interfacing -- Combinational Logic Design -- VHDL (Part 1) -- MSI Logic -- Sequential Logic Design -- VHDL (Part 2) -- Behavioral Modeling Of Sequential Logic -- Memory -- Programmable Logic -- Arithmetic Circuits -- Computer System Design. . |
| Record Nr. | UNINA-9910254173503321 |
|
LaMeres Brock J
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2017 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Machine Learning for Model Order Reduction / / by Khaled Salah Mohamed
| Machine Learning for Model Order Reduction / / by Khaled Salah Mohamed |
| Autore | Mohamed Khaled Salah |
| Edizione | [1st ed. 2018.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018 |
| Descrizione fisica | 1 online resource (99 pages) |
| Disciplina | 006.31 |
| Soggetto topico |
Electronic circuits
Microprocessors Computer architecture Electronics Electronic Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation |
| ISBN | 3-319-75714-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Chapter1: Introduction -- Chapter2: Bio-Inspired Machine Learning Algorithm: Genetic Algorithm -- Chapter3: Thermo-Inspired Machine Learning Algorithm: Simulated Annealing -- Chapter4: Nature-Inspired Machine Learning Algorithm: Particle Swarm Optimization, Artificial Bee Colony -- Chapter5: Control-Inspired Machine Learning Algorithm: Fuzzy Logic Optimization -- Chapter6: Brain-Inspired Machine Learning Algorithm: Neural Network Optimization -- Chapter7: Comparisons, Hybrid Solutions, Hardware architectures and New Directions -- Chapter8: Conclusions. |
| Record Nr. | UNINA-9910299953303321 |
|
Mohamed Khaled Salah
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Machine Learning Support for Fault Diagnosis of System-on-Chip / / edited by Patrick Girard, Shawn Blanton, Li-C. Wang
| Machine Learning Support for Fault Diagnosis of System-on-Chip / / edited by Patrick Girard, Shawn Blanton, Li-C. Wang |
| Edizione | [1st ed. 2023.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023 |
| Descrizione fisica | 1 online resource (320 pages) |
| Disciplina | 006.31 |
| Soggetto topico |
Electronic circuits
Electronic circuit design Microprocessors Computer architecture Electronic Circuits and Systems Electronics Design and Verification Processor Architectures |
| ISBN | 3-031-19639-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Prerequisites on Fault Diagnosis -- Conventional Methods for Fault Diagnosis -- Machine Learning and Its Applications in Test -- Machine Learning Support for Logic Diagnosis -- Machine Learning Support for Cell-Aware Diagnosis -- Machine Learning Support for Volume Diagnosis -- Machine Learning Support for Diagnosis of Analog Circuits -- Machine Learning Support for Board-level Functional Fault Diagnosis -- Machine Learning Support for Wafer-level Failure Cluster Identification -- Conclusion. |
| Record Nr. | UNINA-9910682590803321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
On-Chip Training NPU - Algorithm, Architecture and SoC Design / / by Donghyeon Han, Hoi-Jun Yoo
| On-Chip Training NPU - Algorithm, Architecture and SoC Design / / by Donghyeon Han, Hoi-Jun Yoo |
| Autore | Han Donghyeon |
| Edizione | [1st ed. 2023.] |
| Pubbl/distr/stampa | Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2023 |
| Descrizione fisica | 1 online resource (249 pages) |
| Disciplina | 621.3815 |
| Altri autori (Persone) | YooHoi-Jun |
| Soggetto topico |
Electronic circuits
Embedded computer systems Microprocessors Computer architecture Electronic Circuits and Systems Embedded Systems Processor Architectures |
| ISBN | 3-031-34237-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Chapter 1 Introduction -- Chapter 2 A Theoretical Study on Artificial Intelligence Training -- Chapter 3 New Algorithm 1: Binary Direct Feedback Alignment for Fully-Connected layer -- Chapter 4 New Algorithm 2: Extension of Direct Feedback Alignment to Convolutional Recurrent Neural Network -- Chapter 5 DF-LNPU: A Pipelined Direct Feedback Alignment based Deep Neural Network Learning Processor for Fast Online Learning -- Chapter 6 HNPU-V1: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-point and Active Bit-precision Searching -- Chapter 7 HNPU-V2: An Energy-efficient DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation -- Chapter 8 An Overview of Energy-efficient DNN Training Processors -- Chapter 9 Conclusion. |
| Record Nr. | UNINA-9910736029603321 |
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Han Donghyeon
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| Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2023 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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A Primer on Memory Consistency and Cache Coherence, Second Edition / / by Vijay Nagarajan, Daniel J. Sorin, Mark D. Hill, David A. Wood
| A Primer on Memory Consistency and Cache Coherence, Second Edition / / by Vijay Nagarajan, Daniel J. Sorin, Mark D. Hill, David A. Wood |
| Autore | Nagarajan Vijay |
| Edizione | [2nd ed. 2020.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 |
| Descrizione fisica | 1 online resource (XX, 276 p.) |
| Disciplina | 621.3815 |
| Collana | Synthesis Lectures on Computer Architecture |
| Soggetto topico |
Electronic circuits
Microprocessors Computer architecture Electronic Circuits and Systems Processor Architectures |
| ISBN | 3-031-01764-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Preface to the Second Edition -- Preface to the First Edition -- Introduction to Consistency and Coherence -- Coherence Basics -- Memory Consistency Motivation and Sequential Consistency -- Total Store Order and the \lowercase {X -- Relaxed Memory Consistency -- Coherence Protocols -- Snooping Coherence Protocols -- Directory Coherence Protocols -- Advanced Topics in Coherence -- Consistency and Coherence for Heterogeneous Systems -- Specifying and Validating Memory Consistency Models and Cache Coherence -- Authors' Biographies . |
| Record Nr. | UNINA-9910647487003321 |
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Nagarajan Vijay
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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