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Application-Specific Arithmetic [[electronic resource] ] : Computing Just Right for the Reconfigurable Computer and the Dark Silicon Era / / by Florent de Dinechin, Martin Kumm
| Application-Specific Arithmetic [[electronic resource] ] : Computing Just Right for the Reconfigurable Computer and the Dark Silicon Era / / by Florent de Dinechin, Martin Kumm |
| Autore | de Dinechin Florent |
| Edizione | [1st ed. 2024.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024 |
| Descrizione fisica | 1 online resource (810 pages) |
| Disciplina | 004.0151 |
| Altri autori (Persone) | KummMartin |
| Soggetto topico |
Electronic circuits
Microprocessors Computer architecture Electronics Electronic Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation |
| ISBN | 3-031-42808-0 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Chapter 1 Introduction -- Chapter 2 Number Formats -- Chapter 3 Computing Just Right: Accuracy Specification and Error Analysis -- Chapter 4 Field Programmable Gate Arrays -- Part 1 Revisiting Classic Arithmetic -- Chapter 5 Fixed-Point Addition -- Chapter 6 Fixed-Point Comparison -- Chapter 7 Sums of Weighted Bits -- Chapter 8 Fixed-Point Multiplication -- Chapter 9 Fixed-Point Division -- Chapter 10 Shifters and Leading Bit Counters -- Chapter 11 Basic Floating-Point Operators -- Part 2 Operator Specialization -- Chapter 12 Multiplication by Constants -- Chapter 13 Division by Constants -- Chapter 14 Fixed-Point Squares, Cubes, and Other Integer Powers -- Chapter 15 Specialization and Fusion of Floating-Point Operators -- Part 3 Generic Methods for Fixed-Point Function Approximation -- Chapter 16 Generalities on Fixed-Point Function Approximation -- Chapter 17 Function Evaluation Using Tables and Additions -- Chapter 18 Polynomial-Based Architectures for Function Evaluation -- Chapter 19 Digit Recurrence for Algebraic Functions -- Part 4 Example Composite Operators -- Chapter 20 Fixed-Point Sine and Cosine -- Chapter 21 Floating-Point Accumulation and Sum-of-Products -- Chapter 22 Floating-Point Exponential -- Part 5 Application Domains -- Chapter 23 Arithmetic in The Design of Linear Time-Invariant Filters -- Chapter 24 Arithmetic for Deep Learning -- Part 6 Appendix -- Chapter 25 Appendix A Custom Arithmetic Datapath Design with FloPoCo -- Chapter 26 Appendix B Optimization Using Integer Linear Programming. |
| Record Nr. | UNINA-9910845080503321 |
de Dinechin Florent
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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CAD for Hardware Security [[electronic resource] /] / by Farimah Farahmandi, M. Sazadur Rahman, Sree Ranjani Rajendran, Mark Tehranipoor
| CAD for Hardware Security [[electronic resource] /] / by Farimah Farahmandi, M. Sazadur Rahman, Sree Ranjani Rajendran, Mark Tehranipoor |
| Autore | Farahmandi Farimah |
| Edizione | [1st ed. 2023.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023 |
| Descrizione fisica | 1 online resource (415 pages) |
| Disciplina | 005.8 |
| Soggetto topico |
Electronic circuits
Internet of things Microprocessors Computer architecture Electronic Circuits and Systems Internet of Things Processor Architectures |
| Soggetto non controllato | Mathematics |
| ISBN | 3-031-26896-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- CAD for Information Leakage Assessment -- CAD for Power Side Channel Leakage Assessment -- CAD for Electromagnetic Radiation Leakage Assessment -- CAD for Timing Leakage Assessment -- CAD for Fault Injection Attack Analysis -- CAD for Obfuscation -- CAD for Watermarking -- CAD for HW Metering -- CAD for Detecting HLS Vulnerabilities -- CAD for Counterfeit Detection and Prevention -- CAD for Trojan Detection and Prevention -- CAD for Physical Assurance -- CAD for Anti-Probing -- CAD for Formal Security Verification -- CAD for Reverse Engineering. |
| Record Nr. | UNINA-9910726295403321 |
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Farahmandi Farimah
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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The Datacenter as a Computer [[electronic resource] ] : Designing Warehouse-Scale Machines, Third Edition / / by Luiz André Barroso, Urs Hölzle, Parthasarathy Ranganathan
| The Datacenter as a Computer [[electronic resource] ] : Designing Warehouse-Scale Machines, Third Edition / / by Luiz André Barroso, Urs Hölzle, Parthasarathy Ranganathan |
| Autore | Barroso Luiz André |
| Edizione | [3rd ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (201 pages) |
| Disciplina | 004 |
| Collana | Synthesis Lectures on Computer Architecture |
| Soggetto topico |
Electronic circuits
Microprocessors Computer architecture Electronic Circuits and Systems Processor Architectures |
| ISBN | 3-031-01761-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Acknowlegements -- Introduction -- Workloads and Software Infrastructure -- WSC Hardware Building Blocks -- Data Center Basics: Building, Power, and Cooling -- Energy and Power Efficiency -- Modeling Costs -- Dealing with Failures and Repairs -- Closing Remarks -- Bibliography -- Author Biographies. |
| Record Nr. | UNINA-9910669810203321 |
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Barroso Luiz André
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Deep Reinforcement Learning Processor Design for Mobile Applications [[electronic resource] /] / by Juhyoung Lee, Hoi-Jun Yoo
| Deep Reinforcement Learning Processor Design for Mobile Applications [[electronic resource] /] / by Juhyoung Lee, Hoi-Jun Yoo |
| Autore | Lee Juhyoung |
| Edizione | [1st ed. 2023.] |
| Pubbl/distr/stampa | Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2023 |
| Descrizione fisica | 1 online resource (105 pages) |
| Disciplina | 621.38456 |
| Altri autori (Persone) | YooHoi-Jun |
| Soggetto topico |
Electronic circuits
Embedded computer systems Microprocessors Computer architecture Electronic Circuits and Systems Embedded Systems Processor Architectures |
| ISBN | 3-031-36793-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Background of Deep Reinforcement Learning -- Group-Sparse Training Algorithm for Accelerating Deep Reinforcement Learning -- An Energy-Efficient Deep Reinforcement Learning Processor Design -- Low-power Autonomous Adaptation System with Deep Reinforcement Learning -- Low-power Autonomous Adaptation System with Deep Reinforcement Learning -- Exponent-Computing-in-Memory for DNN Training Processor with Energy-Efficient Heterogeneous Floating-point Computing Architecture. |
| Record Nr. | UNINA-9910739463803321 |
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Lee Juhyoung
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| Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2023 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Design Automation and Applications for Emerging Reconfigurable Nanotechnologies [[electronic resource] /] / by Shubham Rai, Akash Kumar
| Design Automation and Applications for Emerging Reconfigurable Nanotechnologies [[electronic resource] /] / by Shubham Rai, Akash Kumar |
| Autore | Rai Shubham |
| Edizione | [1st ed. 2024.] |
| Pubbl/distr/stampa | Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2024 |
| Descrizione fisica | 1 online resource (230 pages) |
| Disciplina | 006.3 |
| Soggetto topico |
Electronic circuits
Embedded computer systems Microprocessors Computer architecture Electronic Circuits and Systems Embedded Systems Processor Architectures |
| ISBN | 3-031-37924-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Chapter 1. Introduction -- Chapter 2. Preliminaries -- Chapter 3. Exploring Circuit Design Topologies for RFETs -- Chapter 4. Standard Cells and Technology Mapping -- Chapter 5. Logic Synthesis with XOR-Majority Graphs -- Chapter 6. Physical synthesis flow and liberty generation -- Chapter 7. Polymporphic Primitives for Hardware Security -- Chapter 8. Conclusion. |
| Record Nr. | UNINA-9910760262603321 |
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Rai Shubham
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| Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Distributed Embedded Controller Development with Petri Nets [[electronic resource] ] : Application to Globally-Asynchronous Locally-Synchronous Systems / / by Filipe de Carvalho Moutinho, Luís Filipe Santos Gomes
| Distributed Embedded Controller Development with Petri Nets [[electronic resource] ] : Application to Globally-Asynchronous Locally-Synchronous Systems / / by Filipe de Carvalho Moutinho, Luís Filipe Santos Gomes |
| Autore | Moutinho Filipe de Carvalho |
| Edizione | [1st ed. 2016.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016 |
| Descrizione fisica | 1 online resource (90 p.) |
| Disciplina | 004.16 |
| Collana | SpringerBriefs in Electrical and Computer Engineering |
| Soggetto topico |
Electronic circuits
Microprocessors Computer architecture Electronics Electronic Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation |
| ISBN | 3-319-20822-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Related work -- Development of distributed embedded controllers -- Application Example -- Conclusions and future work. |
| Record Nr. | UNINA-9910254234003321 |
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Moutinho Filipe de Carvalho
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Engineering Design [[electronic resource] ] : A Survival Guide to Senior Capstone / / by Cory J. Mettler
| Engineering Design [[electronic resource] ] : A Survival Guide to Senior Capstone / / by Cory J. Mettler |
| Autore | Mettler Cory J. |
| Edizione | [1st ed. 2023.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023 |
| Descrizione fisica | 1 online resource (442 pages) |
| Disciplina | 620.0042 |
| Soggetto topico |
Electronic circuits
Engineering design Microprocessors Computer architecture Electronic Circuits and Systems Engineering Design Processor Architectures |
| ISBN | 3-031-23309-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction to Senior Design -- Meeting your design team for the first time (How to run an effective meeting) -- Daily Documentation (Engineering Notebooks) -- The Initiation Phase -- The Planning Phase -- The Execution Phase -- The Closing Phase. |
| Record Nr. | UNINA-9910728952203321 |
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Mettler Cory J.
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Hardware Security Primitives [[electronic resource] /] / by Mark Tehranipoor, Nitin Pundir, Nidish Vashistha, Farimah Farahmandi
| Hardware Security Primitives [[electronic resource] /] / by Mark Tehranipoor, Nitin Pundir, Nidish Vashistha, Farimah Farahmandi |
| Autore | Tehranipoor Mohammad H. <1974-> |
| Edizione | [1st ed. 2023.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023 |
| Descrizione fisica | 1 online resource (356 pages) |
| Disciplina | 929.605 |
| Soggetto topico |
Electronic circuits
Electronic circuit design Microprocessors Computer architecture Electronic Circuits and Systems Electronics Design and Verification Processor Architectures |
| ISBN | 3-031-19185-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Hardware Security Primitives and their Applications -- Racetrack PUF -- TERO PUF -- Direct Characterization PUF -- Volatile Memory Based PUF -- Emerging Memory Based PUF -- Extrinsic Characterization of PUF -- Radio PUFs and CoAs -- Optical PUFs -- True Random Number Generators -- Hardware Camouflaging -- Temper Detection Methods -- Embedded Watermarking -- Counterfeit and Recycled IC Detection -- Package-Level Counterfeit IC Detection -- Side Channels Protection in Cryptographic Hardware -- Fault Injection Resistant Cryptographic Hardware -- Energy and Performance Optimization for Cryptography -- Lightweight Cryptography -- Post-Quantum Cryptography -- Virtual Proof of Reality -- Analog Security. |
| Record Nr. | UNINA-9910635396903321 |
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Tehranipoor Mohammad H. <1974->
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers / / edited by Lars Svensson, José Monteiro
| Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers / / edited by Lars Svensson, José Monteiro |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 |
| Descrizione fisica | 1 online resource (XIII, 462 p.) |
| Disciplina | 620/.004202825536 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Logic design
Microprocessors Computer architecture Electronic digital computers—Evaluation Computer arithmetic and logic units Computer storage devices Memory management (Computer science) Electronic circuits Logic Design Processor Architectures System Performance and Evaluation Arithmetic and Logic Structures Computer Memory Structure Electronic Circuits and Systems |
| ISBN | 3-540-95948-3 |
| Classificazione |
DAT 190f
ELT 272f SS 4800 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Session 1: Low-Leakage and Subthreshold Circuits -- Subthreshold FIR Filter Architecture for Ultra Low Power Applications -- Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs -- Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits -- Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction -- Session 2: Low-Power Methods and Models -- Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating -- Intelligate: Scalable Dynamic Invariant Learning for Power Reduction -- Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption -- Power-Aware Design via Micro-architectural Link to Implementation -- Untraditional Approach to Computer Energy Reduction -- Session 3: Arithmetic and Memories -- Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication -- Power Optimization of Parallel Multipliers in Systems with Variable Word-Length -- A Design Space Comparison of 6T and 8T SRAM Core-Cells -- Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization -- Session 4: Variability and Statistical Timing -- Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic -- A Study on CMOS Time Uncertainty with Technology Scaling -- Static Timing Model Extraction for Combinational Circuits -- A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA -- Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power -- Session 5: Synchronization and Interconnect -- Logic Synthesis of Handshake Components Using Structural Clustering Techniques -- Fast Universal Synchronizers -- A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router -- PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels -- Session 6: Power Supplies and Switching Noise -- Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits -- A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint -- Generating Worst-Case Stimuli for Accurate Power Grid Analysis -- Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization -- Session 7: Low-Power Circuits; Reconfigurable Architectures -- Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements -- A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation -- Energy Efficient Elliptic Curve Processor -- Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing -- Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures -- Poster Session 1: Circuits and Methods -- Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers -- Ultra Low Voltage High Speed Differential CMOS Inverter -- Differential Capacitance Analysis -- Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey -- Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses -- Poster Session 2: Power and Delay Modeling -- Analytical High-Level Power Model for LUT-Based Components -- A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption -- Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates -- Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level -- Data Dependence of Delay Distribution for a Planar Bus -- Special Session: Power Optimizations Addressing Reconfigurable Architectures -- Towards Novel Approaches in Design Automation for FPGA Power Optimization -- Smart Enumeration: A Systematic Approach to Exhaustive Search -- An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs -- Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor -- Keynotes (Abstracts) -- Integration of Power Management Units onto the SoC -- Model to Hardware Matching for nm Scale Technologies -- Power and Profit: Engineering in the Envelope. |
| Record Nr. | UNISA-996465962903316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers / / edited by Lars Svensson, José Monteiro
| Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers / / edited by Lars Svensson, José Monteiro |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 |
| Descrizione fisica | 1 online resource (XIII, 462 p.) |
| Disciplina | 620/.004202825536 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Logic design
Microprocessors Computer architecture Electronic digital computers—Evaluation Computer arithmetic and logic units Computer storage devices Memory management (Computer science) Electronic circuits Logic Design Processor Architectures System Performance and Evaluation Arithmetic and Logic Structures Computer Memory Structure Electronic Circuits and Systems |
| ISBN | 3-540-95948-3 |
| Classificazione |
DAT 190f
ELT 272f SS 4800 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Session 1: Low-Leakage and Subthreshold Circuits -- Subthreshold FIR Filter Architecture for Ultra Low Power Applications -- Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs -- Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits -- Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction -- Session 2: Low-Power Methods and Models -- Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating -- Intelligate: Scalable Dynamic Invariant Learning for Power Reduction -- Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption -- Power-Aware Design via Micro-architectural Link to Implementation -- Untraditional Approach to Computer Energy Reduction -- Session 3: Arithmetic and Memories -- Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication -- Power Optimization of Parallel Multipliers in Systems with Variable Word-Length -- A Design Space Comparison of 6T and 8T SRAM Core-Cells -- Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization -- Session 4: Variability and Statistical Timing -- Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic -- A Study on CMOS Time Uncertainty with Technology Scaling -- Static Timing Model Extraction for Combinational Circuits -- A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA -- Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power -- Session 5: Synchronization and Interconnect -- Logic Synthesis of Handshake Components Using Structural Clustering Techniques -- Fast Universal Synchronizers -- A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router -- PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels -- Session 6: Power Supplies and Switching Noise -- Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits -- A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint -- Generating Worst-Case Stimuli for Accurate Power Grid Analysis -- Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization -- Session 7: Low-Power Circuits; Reconfigurable Architectures -- Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements -- A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation -- Energy Efficient Elliptic Curve Processor -- Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing -- Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures -- Poster Session 1: Circuits and Methods -- Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers -- Ultra Low Voltage High Speed Differential CMOS Inverter -- Differential Capacitance Analysis -- Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey -- Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses -- Poster Session 2: Power and Delay Modeling -- Analytical High-Level Power Model for LUT-Based Components -- A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption -- Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates -- Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level -- Data Dependence of Delay Distribution for a Planar Bus -- Special Session: Power Optimizations Addressing Reconfigurable Architectures -- Towards Novel Approaches in Design Automation for FPGA Power Optimization -- Smart Enumeration: A Systematic Approach to Exhaustive Search -- An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs -- Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor -- Keynotes (Abstracts) -- Integration of Power Management Units onto the SoC -- Model to Hardware Matching for nm Scale Technologies -- Power and Profit: Engineering in the Envelope. |
| Record Nr. | UNINA-9910485025903321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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